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FEATURES Low Noise 0.9 nV/Hz typ (1.2 nV/Hz max) Input Voltage Noise at 1 kHz 50 nV p-p Input Voltage Noise, 0.1 Hz to 10 Hz Low Distortion -120 dB Total Harmonic Distortion at 20 kHz Excellent AC Characteristics 800 ns Settling Time to 16 Bits (10 V Step) 110 MHz Gain Bandwidth (G = 1000) 8 MHz Bandwidth (G = 10) 280 kHz Full Power Bandwidth at 20 V p-p 20 V/ s Slew Rate Excellent DC Precision 80 V max Input Offset Voltage 1.0 V/ C VOS Drift Specified for 5 V and 15 V Power Supplies High Output Drive Current of 50 mA APPLICATIONS Professional Audio Preamplifiers IR, CCD, and Sonar Imaging Systems Spectrum Analyzers Ultrasound Preamplifiers Seismic Detectors ADC/DAC Buffers PRODUCT DESCRIPTION
Ultralow Distortion, Ultralow Noise Op Amp AD797*
CONNECTION DIAGRAM 8-Pin Plastic Mini-DIP (N), Cerdip (Q) and SOIC (R) Packages
OFFSET NULL -IN +IN -VS
1 2 3 4
AD797
8 7 6
DECOMPENSATION & DISTORTION NEUTRALIZATION +VS OUTPUT OFFSET NULL
TOP VIEW
5
necessary for preamps in microphones and mixing consoles. Furthermore, the AD797's excellent slew rate of 20 V/s and 110 MHz gain bandwidth make it highly suitable for low frequency ultrasound applications. The AD797 is also useful in IR and Sonar Imaging applications where the widest dynamic range is necessary. The low distortion and 16-bit settling time of the AD797 make it ideal for buffering the inputs to ADCs or the outputs of high resolution DACs especially when they are used in critical applications such as seismic detection and spectrum analyzers. Key features such as a 50 mA output current drive and the specified power supply voltage range of 5 to 15 volts make the AD797 an excellent general purpose amplifier.
-90
The AD797 is a very low noise, low distortion operational amplifier ideal for use as a preamplifier. The low noise of 0.9 nV/Hz and low total harmonic distortion of -120 dB at audio bandwidths give the AD797 the wide dynamic range
5
Hz
4
-100 0.001
INPUT VOLTAGE NOISE - nV/
THD - dB
-110
0.0003
2
1
-120 MEASUREMENT LIMIT
0.0001
0 10 100 1k 10k 100k 1M 10M FREQUENCY - Hz
-130 100
300
1k
3k 10k FREQUENCY - Hz
30k
100k
300k
AD797 Voltage Noise Spectral Density
*Patent pending.
THD vs. Frequency
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
THD - %
3
AD797-SPECIFICATIONS (@ T = +25 C and V =
A S
15 V dc, unless otherwise noted)
Min AD797A/S1 Typ Max 25 50 0.2 0.25 0.5 100 120 1 1 1 1 14000 20 6 15 5 20000 110 450 8 280 20 800 130 120 130 120 50 1.7 0.9 1.0 2.0 11 2.5 12 11 2.5 30 12 3 13 13 3 80 50 -98 -120 -90 -110 11 2.5 12 11 2.5 30 80 125/180 1.0 1.5 3.0 400 600/700 2 2 2 2 14000 Min AD797B Typ Max 10 30 0.2 40 60 0.6 Units V V V/C A A nA nA V/V V/V V/V V/V V/V MHz MHz MHz kHz V/s ns dB dB dB dB 2.5 1.2 1.2 nV p-p nV/Hz nV/Hz V rms pA/Hz V V V V V mA mA -90 dB dB
Model INPUT OFFSET VOLTAGE
Conditions TMIN to TMAX
VS 5 V, 15 V 5 V, 15 V 5 V, 15 V
Offset Voltage Drift INPUT BIAS CURRENT TMIN to TMAX INPUT OFFSET CURRENT TMIN to TMAX OPEN-LOOP GAIN VOUT = 10 V RLOAD = 2 k TMIN to TMAX RLOAD = 600 TMIN to TMAX @ 20 kHz2 G = 1000 G = 10002 G = 10 VO = 20 V p-p, RLOAD = 1 k RLOAD = 1 k 10 V Step VCM = CMVR TMIN to TMAX VS = 5 V to 18 V TMIN to TMAX f = 0. 1 Hz to 10 Hz f = 10 Hz f = 1 kHz f = 10 Hz-1 MHz f = 1 kHz
0.25 0.9 0.25 2.0 80 120 20 10 15 7 20000 110 450 8 280 20 800 130 120 130 120 50 1.7 0.9 1.0 2.0 12 3 13 13 3 80 50 -98 200 300
5 V, 15 V 15 V
DYNAMIC PERFORMANCE Gain Bandwidth Product -3 dB Bandwidth Full Power Bandwidth3 Slew Rate Settling Time to 0.0015% COMMON-MODE REJECTION POWER SUPPLY REJECTION INPUT VOLTAGE NOISE
15 V 15 V 15 V 15 V 15 V 15 V 5 V, 15 V
12.5 114 110 114 110
12.5 1200 120 114 120 114
1200
15 V 15 V 15 V 15 V 15 V 15 V 5 V
1.2 1.3
INPUT CURRENT NOISE INPUT COMMON-MODE VOLTAGE RANGE OUTPUT VOLTAGE SWING
RLOAD = 2 k RLOAD = 600 RLOAD = 600
Short-Circuit Current Output Current4 TOTAL HARMONIC DISTORTION RLOAD = 1 k, CN = 50 pF f = 250 kHz, 3 V rms RLOAD = 1 k f = 20 kHz, 3 V rms
15 V 15 V 5 V 5 V, 15 V 5 V, 15 V 15 V 15 V
-120 -110
INPUT CHARACTERISTICS Input Resistance (Differential) Input Resistance (Common Mode) Input Capacitance (Differential)5 Input Capacitance (Common Mode) OUTPUT RESISTANCE POWER SUPPLY Operating Range Quiescent Current AV = +1, f = 1 kHz 5
7.5 100 20 5 3 18 10.5 5
7.5 100 20 5 3 18 10.5
k M pF pF m V mA
5 V, 15 V
8.2
8.2
NOTES 1 See standard military drawing for 883B specifications. 2 Specified using external decompensation capacitor, see Applications section. 3 Full Power Bandwidth = Slew Rate/2 VPEAK. 4 Output Current for |V S - VOUT| >4 V, A OL > 200 k. 5 Differential input capacitance consists of 1.5 pF package capacitance and 18.5 pF from the input differential pair. Specifications subject to change without notice.
-2-
REV. C
AD797
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation @ +25C2 Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . 0.7 V Output Short Circuit Duration . . . . . . . Indefinite Within max Internal Power Dissipation Storage Temperature Range (Cerdip) . . . . . . -65C to +150C Storage Temperature Range (N, R Suffix) . . -65C to +125C Operating Temperature Range AD797A/B . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C AD797S . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature Range (Soldering 60 sec) . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Internal Power Dissipation: 8-Pin SOIC = 0.9 Watts (T A-25C)/JA 8-Pin Plastic DIP and Cerdip = 1.3 Watts - (T A-25C)/JA Thermal Characteristics 8-Pin Plastic DIP Package: JA = 95C/W 8-Pin Cerdip Package: JA = 110C/W 8-Pin Small Outline Package: JA = 155C/W
ABSOLUTE MAXIMUM RATINGS 1
3
The AD797's inputs are protected by back-to-back diodes. To achieve low noise, internal current limiting resistors are not incorporated into the design of this amplifier. If the differential input voltage exceeds 0.7 V, the input current should be limited to less than 25 mA by series protection resistors. Note, however, that this will degrade the low noise performance of the device.
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. Although the AD797 features proprietary ESD protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality.
ORDERING GUIDE
Model AD797AN AD797BN AD797BR AD797BR-REEL AD797BR-REEL7 AD797AR AD797AR-REEL AD797AR-REEL7 5962-9313301MPA Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C Package Description 8-Pin Plastic DIP 8-Pin Plastic DIP 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Cerdip Package Option N-8 N-8 SO-8 SO-8 SO-8 SO-8 SO-8 SO-8 Q-8
METALIZATION PHOTO
Contact factory for latest dimensions. Dimensions shown in inches and (mm).
NOTE The AD797 has double layer metal. Only one layer is shown here for clarity.
REV. C
-3-
AD797-Typical Characteristics
20
INPUT COMMON-MODE RANGE - Volts
15
10
5
0 0 5 10 SUPPLY VOLTAGE - Volts 15 20
VERTICAL SCALE - 0.01V/DIV
HORIZONTAL SCALE - 5 sec/DIV
Figure 1. Common-Mode Voltage Range vs. Supply
20
Figure 4. 0.1 Hz to 10 Hz Noise
0.0
OUTPUT VOLTAGE SWING - Volts
15
INPUT BIAS CURRENT - A
15 20
-0.5
10 +VOUT -V OUT 5
-1.0
-1.5
0 0 5 10 SUPPLY VOLTAGE - Volts
-2.0 -60
-40
-20
0
20 40 60 80 TEMPERATURE - C
100
120
140
Figure 2. Output Voltage Swing vs. Supply
30
OUTPUT VOLTAGE SWING - Volts p-p
Figure 5. Input Bias Current vs. Temperature
140
VS = 15V 20
SHORT CIRCUIT CURRENT - mA
120
100 SOURCE CURRENT SINK CURRENT 80
10 V S = 5V
60
0 10 100 1k LOAD RESISTANCE - 10k
40 -60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE - C
Figure 3. Output Voltage Swing vs. Load Resistance
Figure 6. Short Circuit Current vs. Temperature
-4-
REV. C
AD797
11
QUIESCENT SUPPLY CURRENT - mA
140
POWER SUPPLY REJECTION - dB
10
+125C
120 PSR -SUPPLY PSR +SUPPLY 150 COMMON MODE REJECTION - dB
100
9
80 CMR 60
125
8
+25C
100
7 -55C 6 0
40
75
5
10 SUPPLY VOLTAGE - Volts
15
20
20 1 10 100 1k 10k 100k FREQUENCY - Hz
50 1M
Figure 7. Quiescent Supply Current vs. Supply Voltage
Figure 10. Power Supply and Common-Mode Rejection vs. Frequency
-60 RL = 600 G = +10 FREQ = 10kHz NOISE BW = 100kHz
THD + NOISE - dB
12 FREQ = 1kHz RL = 600
OUTPUT VOLTAGE - Volts rms
G = +10 9
-80
6
VS = 5V -100 VS = 15V
3
0 0 5 10 SUPPLY VOLTAGE - Volts 15 20
-120 0.01
0.1
1.0
10
OUTPUT LEVEL - Volts
Figure 8. Output Voltage vs. Supply for 0.01% Distortion
Figure 11. Total Harmonic Distortion (THD) + Noise vs. Output Level
30 15V SUPPLIES
1.0
0.8 SETTLING TIME - s 0.0015% 0.6 0.01% 0.4
RL = 600
20
10 5V SUPPLIES
0.2
0.0 0 2 4 6 8 10 STEP SIZE - Volts
0 10k
100k
1M
10M
Figure 9. Settling Time vs. Step Size ()
Figure 12. Large Signal Frequency Response
REV. C
-5-
AD797-Typical Characteristics
4 30
SLEW RATE - V/s
GAIN/BANDWIDTH PRODUCT 110
3
SLEW RATE RISING EDGE 25 SLEW RATE FALLING EDGE 20 90 100
2
1
0 10 100 1k 10k 100k 1M 10M FREQUENCY - Hz
15 -60
-40
-20
0
20
40
60
80
100
120
80 140
TEMPERATURE - C
Figure 13. Input Voltage Noise Spectral Density
120 PHASE MARGIN
PHASE MARGIN - DEGREES
Figure 16. Slew Rate & Gain/Bandwidth Product vs. Temperature
160
+100
100
OPEN-LOOP GAIN - dB
WITHOUT RS* WITH RS*
+80
80
+60
OPEN-LOOP GAIN - dB
140
60 GAIN 40 *RS = 100 SEE FIGURE 22 WITHOUT RS* WITH RS* 0 100 1k 10k 100k 1M 10M
+40
+20
120
20
0
100M
100
100
1k LOAD RESISTANCE - Ohms
10k
FREQUENCY - Hz
Figure 14. Open-Loop Gain & Phase vs. Frequency
MAGNITUDE OF OUTPUT IMPEDANCE - Ohms
300
Figure 17. Open-Loop Gain vs. Resistive Load
100
INPUT OFFSET CURRENT - nA
OVER COMPENSATED 150
10 * SEE FIGURE 29
0
1 WITHOUT CN*
-150 UNDER COMPENSATED
0.1 WITH CN*
-300 -60
0.01
-40 -20 0 20 40 60 80 100 120 140
10
100
1k
10k
100k
TEMPERATURE - C
FREQUENCY - Hz
Figure 15. Input Offset Current vs. Temperature
Figure 18. Magnitude of Output Impedance vs. Frequency
-6-
REV. C
GAIN/BANDWIDTH PRODUCT - MHz (G = 1000)
5
35
120
INPUT VOLTAGE NOISE - nV/
Hz
1M
AD797
20pF
1s
1k +V S 1k VIN 2 7
100 90
50mV
100 90
100ns
**
AD797
3 4
6 **
VOUT
10 0%
10 0%
** SEE FIGURE 32
-VS
5V
Figure 19. Inverter Connection
Figure 20. Inverter Large Signal Pulse Response
Figure 21. Inverter Small Signal Pulse Response
100
5V
+V S **
100 90
1s
100 90
50mV
100ns
2 RS* V IN 3
7 VOUT
AD797
4
6 ** 600
10
10 0%
-VS * VALUE OF SOURCE RESISTANCE - SEE TEXT ** SEE FIGURE 32
0%
Figure 22. Follower Connection
Figure 23. Follower Large Signal Pulse Response
Figure 24. Follower Small Signal Pulse Response
5mV
100 90
500ns
100 90
5mV
500ns
See Figure 40 for settling time test circuit.
10 0%
10 0%
Figure 25. 16-Bit Settling Time Positive Input Pulse
Figure 26. 16-Bit Settling Time Negative Input Pulse
REV. C
-7-
AD797
THEORY OF OPERATION
The new architecture of the AD797 was developed to overcome inherent limitations in previous amplifier designs. Previous precision amplifiers used three stages to ensure high open-loop gain, Figure 27b, at the expense of additional frequency compensation components. Slew rate and settling performance are usually compromised, and dynamic performance is not adequate beyond audio frequencies. As can be seen in Figure 27b, the first stage gain is rolled off at high frequencies by the compensation network. Second stage noise and distortion will then appear at the input and degrade performance. The AD797 on the other hand, uses a single ultrahigh gain stage to achieve dc as well as dynamic precision. As shown in the simplified schematic (Figure 28), nodes A, B, and C all track in voltage forcing the operating points of all pairs of devices in the signal path to match. By exploiting the inherent matching of devices fabricated on the same IC chip, high open-loop gain, CMRR, PSRR, and low VOS are all guaranteed by pairwise device matching (i.e., NPN to NPN & PNP to PNP), and not absolute parameters such as beta and early voltage.
This matching benefits not just dc precision but since it holds up dynamically, both distortion and settling time are also reduced. This single stage has a voltage gain of >5 x 106 and VOS <80 V, while at the same time providing THD + noise of less than -120 dB and true 16 bit settling in less than 800 ns. The elimination of second stage noise effects has the additional benefit of making the low noise of the AD797 (<0.9 nV/Hz) extend to beyond 1 MHz. This means new levels of performance for sampled data and imaging systems. All of this performance as well as load drive in excess of 30 mA are made possible by Analog Devices' advanced Complementary Bipolar (CB) process. Another unique feature of this circuit is that the addition of a single capacitor, CN (Figure 28), enables cancellation of distortion due to the output stage. This can best be explained by referring to a simplified representation of the AD797 using idealized blocks for the different circuit elements (Figure 29). A single equation yields the open-loop transfer function of this amplifier, solving it (at Node B) yields: VO gm = V IN CN C j - CN j - C j A A gm = the transconductance of Q1 and Q2 A = the gain of the output stage, (~1) VO = voltage at the output VIN = differential input voltage
gm R1 C1
BUFFER RL
VOUT
GAIN = gmR1 5 x 10 6
a.
C2
gm R1 C1 R2
A2
A3
BUFFER RL
VOUT
GAIN = gmR1 *A2 *A3
b. Figure 27. Model of AD797 vs. That of a Typical Three-Stage Amplifier
VCC R2 R3
When CN is equal to CC this gives the ideal single pole op amp response: VO gm = VIN jC The terms in A, which include the properties of the output stage such as output impedance and distortion, cancel by simple subtraction, and therefore the distortion cancellation does not affect the stability or frequency response of the amplifier. With only 500 A of output stage bias the AD797 delivers a 1 kHz sine wave into 600 at 7 V rms with only 1 ppm of distortion.
I1
I2
CN
CN R1 Q4 Q3 Q7 Q10 OUT I5
A B
Q9 Q12 Q8 Q11 I6 I3
B
OUT
A
+IN Q1 Q2 -IN Q5 Q6
A
+IN Q1 Q2 -IN CURRENT MIRROR CC
CC
1 C
I4
I1
C
I7
I4 VSS
Figure 29. AD797 Block Diagram
Figure 28. AD797 Simplified Schematic
-8-
REV. C
AD797
NOISE AND SOURCE IMPEDANCE CONSIDERATIONS LOW FREQUENCY NOISE
The AD797's ultralow voltage noise of 0.9 nV/Hz is achieved with special input transistors running at nearly 1 mA of collector current. It is important then to consider the total input referred noise (eNtotal), which includes contributions from voltage noise (eN), current noise (iN), and resistor noise (4 kTrS). eNtotal = [eN2 + 4 kTrS + 4 (iNrS)2]l/2 where rS = total input source resistance. This equation is plotted for the AD797 in Figure 30. Since optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from Equation 1 that eliminating the balancing source resistance will lower the total noise by reducing the total rS by a factor of two. At very low source resistance (rS <50 ), the amplifiers' voltage noise dominates. As source resistance increases the Johnson noise of rS dominates until at higher resistances (rS >2 k) the current noise component is larger than the resistor noise.
100
Equation 1
Analog Devices specifies low frequency noise as a peak to peak (p-p) quantity in a 0.1 Hz to 10 Hz bandwidth. Several techniques can be used to make this measurement. The usual technique involves amplifying, filtering, and measuring the amplifiers noise for a predetermined test time. The noise bandwidth of the filter is corrected for and the test time is carefully controlled since the measurement time acts as an additional low frequency roll-off. The plot in Figure 4 was made using a slightly different technique. Here an FFT based instrument (Figure 31) is used to generate a 10 Hz "brickwall" filter. A low frequency pole at 0.1 Hz is generated with an external ac coupling capacitor, the instrument being dc coupled. Several precautions are necessary to get optimum low frequency noise performance: 1. Care must be used to account for the effects of rS, even a 10 resistor has 0.4 nV/Hz of noise (an error of 9% when root sum squared with 0.9 nV/Hz). 2. The test set up must be fully warmed up to prevent eOS drift from erroneously contributing to input noise.
NOISE - nV/
Hz
10
TOTAL NOISE
1
RESISTOR NOISE ONLY
3. Circuitry must be shielded from air currents. Heat flow out of the package through its leads creates the opportunity for a thermoelectric potential at every junction of different metals. Selective heating and cooling of these by random air currents will appear as 1/f noise and obscure the true device noise. 4. The results must be interpreted using valid statistical techniques.
100k
0.1 10 100 1000 10000
+VS ** 1 2 7 1.5F 6 ** VOUT HP 3465 DYNAMIC SIGNAL ANALYZER (10Hz)
SOURCE RESISTANCE -
Figure 30. Noise vs. Source Resistance
The AD797 is the optimum choice for low noise performance provided the source resistance is kept <1 k. At higher values of source resistance, optimum performance with respect to noise alone is obtained with other amplifiers from Analog Devices (see Table I).
Table I. Recommended Amplifiers for Different Source Impedances
AD797
3 4
-V S ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 31. Test Setup for Measuring 0.1 Hz to 10 Hz Noise
WIDEBAND NOISE
rS, ohms 0 to <1 k 1 k to <10 k 10 k to <100 k >100 k
Recommended Amplifier AD797 AD707, AD743/AD745, OP27/OP37, OP07 AD705, AD743/AD745, OP07 AD548, AD549, AD645, AD711, AD743/ AD745
The AD797, due to its single stage design, has the property that its noise is flat over frequencies from less than 10 Hz to beyond 1 MHz. This is not true of most dc precision amplifiers where second stage noise contributes to input referred noise beyond the audio frequency range. The AD797 offers new levels of performance in wideband imaging applications. In sampled data systems, where aliasing of out of band noise into the signal band is a problem, the AD797 will out perform all previously available IC op amps.
REV. C
-9-
AD797
BYPASSING CONSIDERATIONS
To take full advantage of the very wide bandwidth and dynamic range capabilities of the AD797 requires some precautions. First, multiple bypassing is recommended in any precision application. A 1.0 F-4.7 F tantalum in parallel with 0.1 F ceramic bypass capacitors are sufficient in most applications. When driving heavy loads a larger demand is placed on the supply bypassing. In this case selective use of larger values of tantalum capacitors and damping of their lead inductance with small value (1.1 to 4.7 ) carbon resistors can be an improvement. Figure 32 summarizes bypassing recommendations. The symbol (**) is used throughout this data sheet to represent the parallel combination of a 0.1 F and a 4.7 F capacitor.
VS VS
follower. Operation on 5 volt supplies allows the use of a 100 or less feedback network (R1 + R2). Since the AD797 shows no unusual behavior when operating near its maximum rated current, it is suitable for driving the AD600/AD602 (Figure 47) while preserving their low noise performance. Optimum flatness and stability at noise gains >1 sometimes requires a small capacitor (CL) connected across the feedback resistor (R1, Figure 35). Table II includes recommended values of CL for several gains. In general, when R2 is greater than 100 and CL is greater than 33 pF, a 100 resistor should be placed in series with CL. Source resistance matching is assumed, and the AD797 should never be operated with unbalanced source resistance >200 k/G.
CL
OR
0.1F 4.7F
0.1F
4.7 - 22.0F
100
1.1 - 4.7 KELVIN RETURN USE SHORT LEAD LENGTHS (<5mm) USE SHORT LEAD RETURNS (<5mm) KELVIN RETURN
+VS **
2
7
LOAD CURRENT
LOAD CURRENT
VIN
RS* 3 CS*
AD797
4
6 ** 600
VOUT
Figure 32. Recommended Power Supply Bypassing
THE NONINVERTING CONFIGURATION
-VS * SEE TEXT ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Ultralow noise requires very low values of rBB' (the internal parasitic resistance) for the input transistors (6 ). This implies very little damping of input and output reactive interactions. With the AD797, additional input series damping is required for stability with direct input to output feedback. A 100 resistor in the inverting input (Figure 33) is sufficient; the 100 balancing resistor (R2) is recommended, but is not required for stability. The noise penalty is minimal (eNtotal 2.1 nV/Hz), which is usually insignificant. Best response flatness is obtained with the addition of a small capacitor (CL < 33 pF) in parallel with the 100 resistor (Figure 34). The input source resistance and capacitance will also affect the response slightly and experimentation may be necessary for best results.
R1 100 +V S ** 2 R2 100 VIN 3 7
Figure 34. Alternative Voltage Follower Connection
CL
R2
+VS R1 2 7
**
AD797
VIN 3 4
6 ** RL
VOUT
-VS ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 35. Low Noise Preamplifier
Table II. Values for Follower With Gain Circuit
AD797
4
6 ** RL 600
VOUT
Gain 2 2 10 20 >35
R1 1 k 300 33.2 16.5 10
R2
CL
Noise (Excluding rS) 3.0 nV/Hz 1.8 nV/Hz 1.2 nV/Hz 1.0 nV/Hz 0.98 nV/Hz
-VS ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 33. Voltage Follower Connection
Low noise preamplification is usually done in the noninverting mode (Figure 35). For lowest noise the equivalent resistance of the feedback network should be as low as possible. The 30 mA minimum drive current of the AD797 makes it easier to achieve this. The feedback resistors can be made as low as possible with due consideration to load drive and power consumption. Table II gives some representative values for the AD797 as a low noise
1 k 20 pF 300 10 pF 300 5 pF 316 (G-1) * 10
The I-to-V converter is a special case of the follower configuration. When the AD797 is used in an I-to-V converter, for instance as a DAC buffer, the circuit of Figure 36 should be used. The value of CL depends on the DAC and again, if CL is -10- REV. C
AD797
20-120pF R1 100
DRIVING CAPACITIVE LOADS
+VS IIN 2 7
**
The capacitive load driving capabilities of the AD797 are displayed in Figure 38. At gains over 10 usually no special precautions are necessary. If more drive is desirable the circuit in Figure 39 should be used. Here a 5000 pF load can be driven cleanly at any noise gain 2.
VOUT
AD797
3 CS* RS* -VS 4
6 ** 600
100nF
CAPACITIVE LOAD DRIVE CAPABILITY
10nF
* SEE TEXT ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
1nF
Figure 36. I-to-V Converter Connection
100pF
greater than 33 pF a 100 series resistor is required. A bypassed balancing resistor (RS and CS) can be included to minimize dc errors.
THE INVERTING CONFIGURATION
10pF
1pF 1 10 100 1k CLOSED-LOOP GAIN
The inverting configuration (Figure 37) presents a low input impedance, R1, to the source. For this reason, the goals of both low noise and input buffering are at odds with one another. Nonetheless, the excellent dynamics of the AD797 will make it the preferred choice in many inverting applications, and with careful selection of feedback resistors the noise penalties will be minimal. Some examples are presented in Table II and Figure 37.
CL R2
Figure 38. Capacitive Load Drive Capability vs. Closed Loop Gain
20pF
1k 200pF +VS 1k 100
**
+VS ** R1 2 VIN 3 RS* -VS * SEE TEXT ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32. 7
VIN
2
7
AD797
3 4
33 6 ** C1 VOUT
AD797
4
6 ** RL
VOUT
-VS ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 39. Recommended Circuit for Driving a High Capacitance Load
SETTLING TIME
Figure 37. Inverting Amplifier Connection
Table III. Values for Inverting Circuit
Gain -1 -1 -10
R1 1 k 300 150
R2 1 k 300 1500
CL 20 pF 10 pF 5 pF
Noise (Excluding rS) 3.0 nV/Hz 1.8 nV/Hz 1.8 nV/Hz
The AD797 is unique among ultralow noise amplifiers in that it settles to 16 bits (<150 V) in less than 800 ns. Measuring this performance presents a challenge. A special test setup (Figure 40) was developed for this purpose. The input signal was obtained from a resonant reed switch pulse generator, available from Tektronix as calibration Fixture No. 067-0608-00. When open, the switch is simply 50 to ground and settling is purely a passive pulse decay and inherently flat. The low repetition rate signal was captured on a digital oscilloscope after being amplified and clamped twice. The selection of plug-in for the oscilloscope was made for minimum overload recovery.
REV. C
-11-
AD797
TO TEKTRONIX 7A26 OSCILLOSCOPE PREAMP INPUT SECTION 4.26k
R1
1M 20pF
50pF R2 2 8
226
(VIA LESS THAN 1FT 50 COAXIAL CABLE) 2
AD797
VIN 3
6
A2 AD829
7 4
250 6
VERROR X 5 2x HP2835
3 2x HP2835 0.47F
0.47F
a.
R1 C2
+VS -VS 1k TEKTRONIX CALIBRATION FIXTURE 100 1k 1k NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
R2 2
C1 8
AD797
VIN 3
6
VIN
1k 2
20pF
A1 AD797
3 4 7
6 51pF
C1, SEE TABLE C2 = 50pF - C1
1F 1F 0.1F +VS -VS
0.1F
b. Figure 41. Recommended Connections for Distortion Cancellation and Bandwidth Enhancement
Table IV. Recommended External Compensation
Figure 40. Settling Time Test Circuit
DISTORTION REDUCTION
The AD797 has distortion performance (THD < -120 dB, @ 20 kHz, 3 V rms, RL = 600 ) unequaled by most voltage feedback amplifiers. At higher gains and higher frequencies THD will increase due to reduction in loop gain. However in contrast to most conventional voltage feedback amplifiers the AD797 provides two effective means of reducing distortion, as gain and frequency are increased; cancellation of the output stage's distortion and gain bandwidth enhancement by decompensation. By applying these techniques gain bandwidth can be increased to 450 MHz at G = 1000 and distortion can be held to -100 dB at 20 kHz for G = 100. The unique design of the AD797 provides for cancellation of the output stage's distortion (patent pending). To achieve this a capacitance equal to the effective compensation capacitance, usually 50 pF, is connected between Pin 8 and the output (C2 in Figure 41). Use of this feature will improve distortion performance when the closed loop gain is more than 10 or when frequencies of interest are greater than 30 kHz. Bandwidth enhancement via decompensation is achieved by connecting a capacitor from Pin 8 to ground (C1 in Figure 41) effectively subtracting from the value of the internal compensation capacitance (50 pF), yielding a smaller effective compensation capacitance and, therefore, a larger bandwidth. The benefits of this begin at closed loop gains of 100 and up. A maximum value of 33 pF at gains of 1000 and up is recommended. At a gain of 1000 the bandwidth is 450 kHz. Table IV and Figure 42 summarize the performance of the AD797 with distortion cancellation and decompensation.
A/B R1 R2
A C1 C2 3 dB (pF) BW 50 50 50
B C1 C2 3 dB (pF) BW 50 6 MHz 33 1.5 MHz 15 450 kHz
G = 10 909 100 0 G = 100 1 k 10 0 G = 1000 10 k 10 0
6 MHz 0 1 MHz 15 110 kHz 33
-80 G=1000 RL=600 -90 NOISE LIMIT, G=1000 G=1000 RL =10k G=100 RL =600 NOISE LIMIT, G=100 -110
0.01
0.003
THD - dB
-100
0.001
0.0003
-120
G=10 RL =600
0.0001
100
300
1k
3k
10k
30k
100k
300k
FREQUENCY - Hz
Figure 42. Total Harmonic Distortion (THD) vs. Frequency @ 3 V rms for Figure 41b
-12-
REV. C
THD - %
AD797
Differential Line Receiver
The differential receiver circuit of Figure 43 is useful for many applications from audio to MRI imaging. It allows extraction of a low level signal in the presence of common-mode noise. As shown in Figure 44, the AD797 provides this function with only 9 nV/Hz noise at the output. Figure 45 shows the AD797's 20-bit THD performance over the audio band and 16-bit accuracy to 250 kHz.
20pF
A General Purpose ATE/Instrumentation Input/Output Driver
The ultralow noise and distortion of the AD797 may be combined with the wide bandwidth, slew rate, and load drive of a current feedback amplifier to yield a very wide dynamic range general purpose driver. The circuit of Figure 46 combines the AD797 with the AD811 in just such an application. Using the
-90 0.003
1k +VS
1k -100
WITHOUT OPTIONAL 50pF CN
0.001
THD - dB
DIFFERENTIAL INPUT
7 2 8
-110
MEASUREMENT LIMIT
0.0003
AD797
3 4
6 OUTPUT -120 *OPTIONAL ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32. -130 100 WITH OPTIONAL 50C N 300 1k 3k 10k FREQUENCY - Hz 30k 100k 300k 0.0001
** 1k 1k
-VS
20pF
Figure 43. Differential Line Receiver
16
Figure 45. Total Harmonic Distortion (THD) vs. Frequency for Differential Line Receiver
OUTPUT VOLTAGE NOISE -- nV/ Hz
14
component values shown, this circuit is capable of better than -90 dB THD with a 5 V, 500 kHz output signal. The circuit is therefore suitable for driving high resolution A/D converters and as an output driver in automatic test equipment (ATE) systems. Using a 100 kHz sine wave, the circuit will drive a 600 load to a level of 7 V rms with less than -109 dB THD, and a 10 k load at less than -117 dB THD.
22pF
12
10
R2 +VS ** 2k +VS 2 7 ** 6 ** 2 -V S ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32. 649 649 -VS 3 7
8
6 10 100 1k 10k 100k FREQUENCY -- Hz 1M 10M
1k 3 INPUT
AD797
4
AD811
4
6 OUTPUT **
Figure 44. Output Voltage Noise Spectral Density for Differential Line Receiver
Figure 46. A General Purpose ATE/lnstrumentation Input/ Output Driver
REV. C
-13-
THD - %
**
50pF*
AD797
Ultrasound/Sonar Imaging Preamp
VOLTAGE NOISE - Vrms (0.1Hz - Freq)
The AD600 variable gain amplifier provides the time controlled gain (TCG) function necessary for very wide dynamic range sonar and low frequency ultrasound applications. Under some circumstances, it is necessary to buffer the input of the AD600 to preserve its low noise performance. To optimize dynamic range this buffer should have at most 6 dB of gain. The combination of low noise and low gain is difficult to achieve. The input buffer circuit shown in Figure 47 provides 1 nV/Hz noise performance at a gain of two (dc to 1 MHz) by using 26.1 resistors in its feedback path. Distortion is only -50 dBc @ 1 MHz at a 2 volt p-p output level and drops rapidly to better than -70 dBc at an output level of 200 mV p-p.
26.1 +VS ** 26.1 2 7 **
-30
100
-40 VOUT NOISE
80
VOUT - dB Re 1V/A
-50
60
-60
40
-70
20
-80 100 1k 10k 100k 1M FREQUENCY - Hz 10M
0 100M
Figure 49. Total Integrated Voltage Noise & VOUT of Amorphous Detector Preamp
AD600
AD797
INPUT 3 4
6 **
Professional Audio Signal Processing--DAC Buffers
VOUT
-VS * USE POWER SUPPLY ** BYPASSING SHOWN IN FIGURE 32. VS = 6Vdc
**
Figure 47. An Ultrasound Preamplifier Circuit
Large area photodiodes CS 500 pF and certain image detectors (amorphous Si), have optimum performance when used in conjunction with amplifiers with very low voltage rather than very low current noise. Figure 48 shows the AD797 used with an amorphous Si (CS = 1000 pF) detector. The response is adjusted for flatness using capacitor CL, while the noise is dominated by voltage noise amplified by the ac noise gain. The 797's excellent input noise performance gives 27 V rms total noise in a 1 MHz bandwidth, as shown by Figure 49.
CL 50pF
Amorphous (Photodiode) Detector
The low noise and low distortion of the AD797 make it an ideal choice for professional audio signal processing. An ideal I-to-V converter for a current output DAC would simply be a resistor to ground, were it not for the fact that most DACs do not operate linearly with voltage on their output. Standard practice is to operate an op amp as an I-to-V converter creating a virtual ground at its inverting input. Normally, clock energy and current steps must be absorbed by the op amp's output stage. However, in the configuration of Figure 50, Capacitor CF shunts high frequency energy to ground, while correctly reproducing the desired output with extremely low THD and IMD.
CF 82pF
100
3k
+VS **
100
AD1862 DAC
2 C1 2000pF 3
7
10k
AD797
4
6 **
+VS **
-V S
2 IS CS 1000pF
7
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
AD797
3 4
6 **
Figure 50. A Professional Audio DAC Buffer
-VS ** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 48. Amorphous Detector Preamp
Figure 51. Offset Null Configuration
-14-
REV. C
AD797
OPERATIONAL AMPLIFIERS LOW NOISE
LOW VOLTAGE NOISE - V N (V N 10 nV/ Hz @ 1 kHz)
AUDIO AMPLIFIERS AD797 OP275 SSM2015 SSM2016 SSM2017 SSM2134 SSM2139 PRECISION AD797 AD OP27 AD OP37 OP27 OP37 OP227 (Dual) OP270 (Dual) OP271 (Dual) OP275 (Dual) OP467 (Quad) OP470 (Quad) OP471 (Quad) High Output Current AD797 OP50 FET INPUT AD645 AD743 AD795 AD796 (Dual) Fast AD745 LOW POWER AD548 AD795 OP80 AD648 (Dual) AD796 (Dual) Faster (Slew Rate 8 V/s) OP282 (Dual) OP482 (Quad) PRECISION AD548 AD795 AD820 AD648 (Dual) AD796 (Dual) AD822 (Dual) FAST AD711 AD712 (Dual) OP249 (Dual) AD713 (Quad) Faster LOW VN ELECTROMETER AD645 AD795 AD796 (Dual) Lower V N AD743 Faster AD745 Low Power OP80 General Purpose AD515A AD545A AD546
LOW CURRENT NOISE - IN LOW INPUT BIAS CURRENT - IBIAS (IN 10 fA/ Hz @ 1 kHz, IBIAS 100 pA)
FAST (Slew Rate 45 V/s) OP61 OP467 (Quad)
Faster (Slew Rate 230 V/s) ULTRALOW V N 0.9 nV/ Hz AD797 AD829 AD840 AD844 AD846 AD848 AD849 AD5539 Ultrafast (Slew Rate 1000 V/s) AD810 AD811 AD844 AD9610 AD9617 AD9618
Lowest I BIAS AD744 60 fA Max OP42 OP44 AD549 AD746 (Dual)
REV. C
-15-
AD797
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Cerdip (Q) Package*
0.005 (0.13) MIN 0.055 (1.4) MAX
8
5 0.310 (7.87) 0.220 (5.59)
1
4 0.070 (1.78) 0.030 (0.76)
0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC
0.320 (8.13) 0.290 (7.37)
0.015 (0.38) 0.008 (0.20)
0.023 (0.58) 0.014 (0.36)
0 - 15 SEATING PLANE
Plastic Mini-DIP (N) Package
8
5 0.25 (6.35) 0.31 (7.87)
1
4
0.39 (9.91) MAX 0.035 0.01 (0.89 0.25)
0.30 (7.62) REF
0.165 0.01 (4.19 0.25) SEATING PLANE 0.125 (3.18) MIN
0.011 0.003 (4.57 0.76) 0.18 0.03 (4.57 0.76)
0.018 0.003 (0.46 0.08) 0.033 (0.84) NOM
0.10 (2.54) TYP
0 - 15
8-Pin SOIC (R) Package
0.198 (5.03) 0.188 (4.77)
8
5
0.158 (4.00) 0.150 (3.80) 0.244 (6.200) 0.228 (5.80)
1
4
0.050 (1.27) TYP
0.018 (0.46) 0.014 (0.36)
0.205 (5.20) 0.181 (4.60)
0.010 (0.25) 0.004 (0.10)
0.069 (1.75) 0.053 (1.35)
0.015 (0.38) 0.007 (0.18)
0.045 (1.15) 0.020 (0.50)
*See military data sheet for 883B specifications.
-16-
REV. C
PRINTED IN U.S.A.
C1677-24-6/92

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