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EtronTech
Etron Confidential
EM658160
(Rev. 1.1 Jan./2002)
4M x 16 DDR Synchronous DRAM (SDRAM)
Features
Fast clock rate: 300/285/250/200/166/143/125MHz Differential Clock CK & /CK Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture Four internal banks, 1M x 16-bit for each bank Programmable Mode and Extended Mode registers - /CAS Latency: 2, 2.5, 3 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved * Individual byte write mask control * DM Write Latency = 0 * Auto Refresh and Self Refresh * 4096 refresh cycles / 64ms * Precharge & active power down * Power supplies: VDD = 3.3V 0.3V VDDQ = 2.5V 0.2V * Interface: SSTL_2 I/O Interface * Package: 66 Pin TSOP II, 0.65mm pin pitch * * * * * * * *
Pin Assignment (Top View)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
Ordering Information
Part Number EM658160TS-3.3 EM658160TS-3.5 EM658160TS-4 EM658160TS-5 EM658160TS-6 EM658160TS-7 EM658160TS-8 Frequency 300MHz 285MHz 250MHz 200MHz 166MHz 143MHz 125MHz Package TSOP II TSOP II TSOP II TSOP II TSOP II TSOP II TSOP II
Overview
The EM658160 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 64 Mbits. It is internally configured as a quad 1M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and /CK. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM658160 provides programmable Read or Write burst lengths of 2, 4, 8, full page. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM658160 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
Block Diagram
4Mx16 DDR SDRAM
EM658160
Column Decoder
Row Decoder
1MX16 CELL ARRAY (BANK #0) Sense Amplifier
CK /CK CKE
DLL CLOCK BUFFER
CONTROL SIGNAL GENERATOR Sense Amplifier
Row Decoder Row Decoder
/CS /RAS /CAS /WE
COMMAND DECODER MODE REGISTER
1MX16 CELL ARRAY (BANK #1) Column Decoder
COLUMN COUNTER A10/AP Column Decoder 1MX16 CELL ARRAY (BANK #2) Sense Amplifier REFRESH COUNTER
A0 A11 BS0 BS1
ADDRESS BUFFER
DQ BUFFER
Row Decoder
LDQS, UDQS
DATA STROBE BUFFER DQ0 DQ15
Sense Amplifier 1MX16 CELL ARRAY (BANK #3) Column Decoder
D
LDM, UDM
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Pin Descriptions
Symbol CK, /CK Type Input
4Mx16 DDR SDRAM
EM658160
Table 1. Pin Details of EM658160 Description Differential Clock: CK, /CK are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. Both CK and /CK increment the internal burst counter and controls the output registers. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A7with A10 defining Auto Precharge). Chip Select: /CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when /CS is sampled HIGH. /CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The /RAS signal defines the operation commands in conjunction with the /CAS and /WE signals and is latched at the positive edges of CK. When /RAS and /CS are asserted "LOW" and /CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the /WE signal. When the /WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the /WE is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Column Address Strobe: The /CAS signal defines the operation commands in conjunction with the /RAS and /WE signals and is latched at the positive edges of CK. When /RAS is held "HIGH" and /CS is asserted "LOW," the column access is started by asserting /CAS "LOW." Then, the Read or Write command is selected by asserting /WE "HIGH " or LOW"." Write Enable: The /WE signal defines the operation commands in conjunction with the /RAS and /CAS signals and is latched at the positive edges of CK. The /WE input is used to select the BankActivate or Precharge command and Read or Write command. Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive edges of CK and /CK. The I/Os are byte-maskable during Writes.
CKE
Input
BS0, BS1 A0-A11
Input Input
/CS
Input
/RAS
Input
/CAS
Input
/WE
Input
LDQS, UDQS LDM, UDM DQ0 - DQ15
Input / Output Input
Input / Output
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VDD VSS VDDQ VSSQ VREF NC Supply Supply Supply Supply Supply Ground
4Mx16 DDR SDRAM
EM658160
Power Supply: +3.3V 0.3V DQ Power: +2.5V 0.2V. Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Reference Voltage for Inputs: +0.5*VDDQ No Connect: These pins should be left unconnected.
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Operation Mode
4Mx16 DDR SDRAM
EM658160
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command
BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set Extended MRS No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit
State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Idle Any Active(4) Any Idle Idle Idle
(SelfRefresh)
CKEn-1 CKEn H H H H H H H H H H H H H H L H H L L H X X X X X X X X X X X X H L H L L H H X
DM BS0,1 A10 A0-9,11 /CS /RAS /CAS /WE X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X V V X V V V V Row address L H L H L H X X
Column address (A0 ~ A7) Column address (A0 ~ A7)
L L L L L L L L L
L L L H H H H L L H H X L L X H X X H X X H X
H H H L L L L L L H H X L L X H X X H X X H X X
H L L L L H H L L H L X H H X H X X H X X H X X
OP code OP code X X X X X X X X X X X X X X X X X X X X X X
L L H L L H L X H L X H L X
Clock Suspend Mode Entry Power Down Mode Entry
Active Any(5) Active Any
(PowerDown)
Clock Suspend Mode Exit Power Down Mode Exit
Data Write/Output Enable Data Mask/Output Disable
Active
Active H X H X X X X X Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode.
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Mode Register Set (MRS)
4Mx16 DDR SDRAM
EM658160
The mode register is divided into various fields depending on functionality. * Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8. A2 0 0 0 0 1 1 1 1 * A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved
Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, both Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2,4 and 8. A3 0 1 Addressing Mode Sequential Interleave
--- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. Data n Column Address 0
n
1
n+1
2
n+2
3
n+3
4
n+4
5
n+5
6
n+6
7
n+7
2 words Burst Length 4 words 8 words Full Page (Even starting address) --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A7 A7 A7 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A5 A5 A5 Column Address A4 A4 A4 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A1 A1 A0 A0# 4 words 8 words Burst Length
A1# A0 A1# A0# A0 A0#
A2# A1 A2# A1
A2# A1# A0 A2# A1# A0#
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*
4Mx16 DDR SDRAM
EM658160
CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) CAS Latency X tCK A6 0 0 0 1 1 1 A5 0 1 1 0 1 1 A4 0 0 1 1 0 1 CAS Latency Reserved 2 clocks 3 clocks Reserved 2.5 clocks Reserved (3.5 clocks)
*
Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. A8 0 1 X A7 0 0 1 BS0 0 1 Test Mode Normal mode DLL Reset Test mode An ~ A0 MRS Cycle Extended Functions (EMRS)
*
( BS0, BS1) BS1 RFU RFU
Extended Mode Register Set (EMRS)
BS1 RFU RFU
BS0 1 1
A11~ A1 RFU RFU
A0 0 1 DLL Enable DLL Disable
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Absolute Maximum Rating
Symbol VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT Item
4Mx16 DDR SDRAM
EM658160
Rating - 0.3~ VDD + 0.3 - 0.3~3.6 0~70 - 55~150 260 1 50
Unit V V C C C W mA
Note 1 1 1 1 1 1 1
Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current
Recommended D.C. Operating Conditions (Ta = 0 ~ 70 C)
Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Reference Voltage Termination Voltage Input High Voltage (DC) Input Low Voltage (DC) Input Voltage Level, CLK and CLK# inputs Input Different Voltage, CLK and CLK# inputs Input leakage current Output leakage current Output High Voltage Output Low Voltage Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) II IOZ VOH VOL Min. 3.0 2.3 1.15 VREF - 0.04 VREF + 0.18 -0.3 -0.3 -0.36 -5 -5 VTT + 0.76 Max. 3.6 2.7 1.35 VREF + 0.04 VDDQ + 0.3 VREF - 0.18 VDDQ + 0.3 VDDQ + 0.6 5 5 VTT - 0.76 Unit V V V V V V V V A A V V IOH = -15.2 mA IOL = +15.2 mA Note
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Symbol CIN CI/O Parameter Input Capacitance (CK pin) DQ, DQS, DM Capacitance
4Mx16 DDR SDRAM
EM658160
Unit pF pF pF
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25 C)
Min. 2.5 2.5 4 Max. 5 4 6.5 Input Capacitance (except for CK pin)
Note: These parameters are periodically sampled and are not 100% tested.
Recommended D.C. Operating Conditions (VDD = 3.3V 0.3, Ta = 0~70 C)
Max. Parameter Operation Current (one bank active) Operation Current (one bank active) Precharge Powerdown Standby Current Idel Standby Current Active Power-down Standby Current Active Standby Current Operation Current (Read) Operation Current (Write) Auto Refresh Current Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W IDD5 tRC = min, tCK = min Active-precharge Burst = 2, tRC = min, CL = 3 IOUT = 0mA, Active-Read-Precharge CKE VIL(max), tCK = min, All banks idle CKE VIH(min), CS# VIH(min), tCK = min All banks ACT, CKE VIL(max), tCK = min One bank; Active-Precharge, tRC = tRAS(max), tCK = min Burst = 2, CL = 3, tCK = min, IOUT = 0mA Burst = 2, CL = 3, tCK = min tRC(min)
- 3.3/3.5/4/5/6/7/8
UNIT
250/240/230/220/190/180/160 320/300/260/250/220/210/200 80/80/80/65/65/60/55 170/160/150/130/110/100/90 80/80/80/65/65/60/55 180/170/160/155/145/140/135 330/310/270/250/220/200/180 330/310/270/250/220/200/180 190/180/170/155/145/140/135
mA
Self Refresh Current
IDD6
CKE 0.2v
2
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(VDD = 3.3 0.3 V, Ta = 0~70 C)
Symbol Parameter
4Mx16 DDR SDRAM
EM658160
Electrical Characteristics and Recommended A.C. Operating Conditions
- 3.3/3.5/4/5/6/7/8 Min. Max. Unit
tRC tRFC tRAS tRCD tRP tRRD twR tCDLR tCCD tCK
Row cycle time Refresh row cycle time Row active time /RAS to /CAS Delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command
Col. Address to Col. Address delay
44/44/44/55/60/70/80 56/56/56/70/84/91/96 32/32/32/40/42/49/56 12/12/12/15/18/21/24 12/12/12/15/18/21/24 6.6/7/8/10/12/14/16 2 2.5tCK-tDQSS 1 3.3/3.5/4/5/6/7/8 5/5/5.5/6/7.5/8/9 6/6/7/8/9/10/11 0.45 0.45 -0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8 -0.6/-0.6/-0.6/-0.7/-0.7/-0.75/-0.8 -0.5/-0.5/-0.5/-0.5/-0.5/-0.5/-0.6 0.9 0.4 0.75 0.4/0.4/0.4/0.4/0.45/0.5/0.55 0.4/0.4/0.4/0.4/0.45/0.5/0.55 0.4 0.4 0.4 1.1 1.1 1 0.4/0.4/0.4/0.4/0.45/0.5/0.55 0.4/0.4/0.4/0.4/0.45/0.5/0.55 0.3 tIS+1tCK 12/12/11/11/10/10/10 200 tIS+2tCK 0.6 0.6 0.6 15 15 15 0.55 0.55 0.6/0.6/0.6/0.7/0.7/0.75/0.8 0.6/0.6/0.6/0.7/0.7/0.75/0.8 0.5/0.5/0.5/0.5/0.5/0.5/0.6 1.1 0.6 1.25 120000
ns ns ns ns ns ns tCK tCK tCK ns
Clock cycle time
CL*=3 CL*=2.5 CL*=2
tCH tCL
Clock high level width Clock low level width
tCK tCK ns ns ns tCK tCK tCK ns ns tCK tCK tCK ns ns tCK ns ns tCK ns tCK tCK
tDQSCK DQS-out access time from CK,/CK tAC tDQSQ tRPRE tRPST tDQSS Output access time from CK,/CK DQS-DQ Skew Read preamble Read postamble CK to valid DQS-in
tWPRES DQS-in setup time tWPREH DQS-in hold time tWPST tDQSH tDQSL tIS tIH tMRD tDS tDH tQH tPDEX tXSA tXSR DQS write postamble DQS in high level pulse width DQS in low level pulse width
Address and Control input setup time Address and Control input hold time
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Output DQS valid window Power down exit time Self refresh exit to active command delay Self refresh exit to read command delay
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Note: 2. All voltages are referenced to VSS.
4Mx16 DDR SDRAM
EM658160
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. Power-up sequence is described in Note 6. 5. A.C. Test Conditions
SSTL_2 Interface
Reference Level of Output Signals (VRFE) Output Load Input Signal Levels Input Signals Slew Rate Reference Level of Input Signals 0.5 * VDDQ Reference to the Under Output Load (A) VREF+0.35 V / VREF-0.35 V 1 V/ns 0.5 * VDDQ
0.5*VDDQ
25 25 Output 30pF
SSTL_2 A.C. Test Load
6.
Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and maintain CKE "LOW". Power applied to VDDQ the same time as VTT and VREF. 2) After power-up, No-Operation of 200 -seconds minimum is required. 3) Start clock and keep CKE "HIGH" to maintain either No-Operation or Device Deselect at the input. 4) Issue EMRS - enable DLL. 5) Issue MRS - reset DLL and set device to idle with bit A8 (An additional 200 cycles min of clock are needed for DLL lock) 6) Precharge all banks of the device. 7) Two or more Auto Refresh commands. 8) Issue MRS - Initialize device operation.
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Timing Waveforms
4Mx16 DDR SDRAM
EM658160
Figure 1. AC Parameters for Read Timing (Burst Length=4, CAS Latency=2.5)
tCH
CK
tCL
tCK
/CK
tIS
CMD
Read
tIH
tIS
ADDR
tIH
/CS
tDQSQ tRPRE tRPST
DQS
Preamble Postamble
tAC
DQ
D0
D1
D2
D3
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4Mx16 DDR SDRAM
EM658160
Figure 2. AC Parameters for Write Timing (Burst Length=4)
CK
/CK
CMD
Write
ADDR
/CS
DQ
D0
D1
D2
D3
tDH tWPRES tDS tDSL tDSH tWPST
tDQSS
DQS
Preamble
Postamble
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4Mx16 DDR SDRAM
EM658160
Figure 3. Read Command to Output Data Latency (Burst Length=2)
CK
/CK
CMD CL=2 DQ
Read
DA0
DA1
DQS
Postamble Preamble
CL=2.5 DQ
DA0
DA1
Postamble
DQS
Preamble
CL=3 DQ
DA0 DA1
Postamble
DQS
Preamble
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4Mx16 DDR SDRAM
EM658160
Figure 4. Read Followed by Write (Burst Lenth=4, CAS Latency=3)
CK /CK
tRRD tRCDR
Activate
CMD
Read
ACT
Write
ADDR
Row/Bank0 Col/Bank0 Rol/Bank1 Col/Bank0
/CS
DQ
D0
D1
D2
D3
DQS
Preamble Postamble
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4Mx16 DDR SDRAM
EM658160
Figure 5. Write followed by Read (Burst Lenth=4, CAS Latency=3)
CK
/CK
tWTR
CMD
Write
Read
ADDR
Col
Col
/CS
DQ
D0 D1 D2
D3
D0 D1
D2 D3
DQS
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4Mx16 DDR SDRAM
EM658160
Figure 6. Precharge Termination of a Burst Read (Burst Length=4, CAS Latency=3)
CK
/CK Precharge CMD Read ACT
ADDR
Col
Bank
Bank
/CS
tRP
DQ D0 D1
DQS
Preamble Postamble
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CK
4Mx16 DDR SDRAM
EM658160
Figure 7. Precharge Termination of a Burst Write (Burst Length=4)
/CK
tRC
Activate Write Precharge Activate
CMD
ADDR
Row/Bank Col/Bank Row/Bank Row/Bank
/CS
tRCD
DQM
tWR tDS
tRP
tQDH tRAS
DQ
D0
D1
masked by DQM
DQS
Preamble Postamble
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4Mx16 DDR SDRAM
EM658160
Figure 8. Auto Precharge after Read Burst (CAS Latency=3)
CK /CK
tRP
BL=2 CMD
ReadA Auto Precharge ACT
DQ
D0 D1
tRP
BL=4 CMD
ReadA Auto Precharge ACT
DQ
D0 D1 D2
D3
tRP
BL=8 CMD
ReadA Auto Precharge ACT
DQ
D0
D1 D2
D3 D4 D5 D6
D7
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4Mx16 DDR SDRAM
EM658160
Figure 9. Auto Precharge after Write Burst
CK
/CK BL=2 CMD
WriteA
Auto Precharge ACT tWR tRP
DQ
D0
D1
Preamble
DQS
Postamble
BL=4 CMD
WriteA
Auto Precharge ACT tWR tRP
DQ
D0 D1 D2
D3
Preamble
DQS
Postamble
BL=8 CMD
WriteA
Auto Precharge ACT tWR tRP
DQ
D0 D1 D2 D3
D4 D5
D6 D7
Preamble
DQS
Postamble
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4Mx16 DDR SDRAM
EM658160
Figure 10. Read Terminated By Burst Stop (Burst Length=8)
CK
/CK
CMD
Read
BST
Col
ADDR
/CS
CL=3 DQ
D0 D1 D2 D3
DQS
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4Mx16 DDR SDRAM
EM658160
Figure 11. Read Terminated by Read (Burst Length=4, CAS Latency=3)
CK
/CK
tCCD
CMD
Read Read
ADDR
Col A
Col B
/CS
DQ
DA0
DA1
DB0
DB1
DB2
DB3
DQS
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4Mx16 DDR SDRAM
EM658160
Figure 12. Mode Register Set Command
CK
/CK
tRP
CMD
Precharge MRS
1 clk
ACT
ADDR
MRS Data
Row
/CS
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4Mx16 DDR SDRAM
EM658160
Figure 13. Active / Precharge Power Down Mode
CK
/CK
tIS
CKE
tPDEX
CMD Activate / Precharge Note 1,2
Any Command
Note:
1. All banks should be in idle state prior to entering precharge power down mode. 2. One of the banks should be in active state prior to entering active power down mode.
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4Mx16 DDR SDRAM
EM658160
Figure 14. Self Refresh Entry and Exit Cycle
CK
/CK
Self Refresh Enter CMD
Auto Refresh
NOP
tRC
CKE
tIS
Self Refresh Exit
tRC is required before any command can be applied, and 200 cycles of clk are required before a READ command can be applied.
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22.22 0.13 66
4Mx16 DDR SDRAM
EM658160
66 Pin TSOP II Package Outline Drawing Information Units: mm
34
0.125
+ 0.085 - 0.005
10.16 0.13
11.76 0.20
1
33
1.00 0.10
1.20 MAX
0.5 0.1 0~8 0.10 MAX 0.05 MIN 0.71 TYP 0.65 TYP 0.30 0.08 0.25 TYP
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0.8 TYP

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Price & Availability of EM658160

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