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HD74ALVCHR162269A
12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs
ADE-205-125 (Z) Preliminary 1st. Edition January 1998 Description
The HD74ALVCHR162269A is a 12-bit to 24-bit registered bus exchanger, which is intended for applications where two separate ports must be multiplexed onto, or de-multiplexed from, a single port. It is particularly suitable as an interface between synchronous DRAMs and high speed microprocessors. The HD74ALVCHR162269A is designed specifically for low voltage (from 2.5 V to 3.3 V) VCC operation. Data is stored in the internal B-port registers on the low to high transition of the CLK input, provided that the appropriate CLKENA inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B-port. For data transfer in the B to A direction, a single storage register is provided. The SEL line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the period that the data will be valid on the bus. The control pins are registered so that all transactions are synchronous with the clock. Data flows is controlled by the active low output enables (OEA, OEB1, OEB2). Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 resistors to reduce overshoot and undershoot.
Features
* All outputs have equivalent 26 series resistors, so no external resistors are required. * Bus hold on data inputs eliminates the need for external pullup / pulldown resistors.
HD74ALVCHR162269A
Function Table
Inputs CLK OEA H H L OEB H L H Outputs A Z Z Active 1B, 2B Z Active Z
Output-enable table
Inputs CLKENA1 L L L L H H H CLKENA2 H H L L L L H CLK X A L H L H L H X
Outputs 1B L H L H 1B0 1B0 1B0
*1 *1 *1
2B 2B0 2B0 L H L H 2B0
*1 *1 *1
A-to-B storage table (OEB = L)
Inputs CLK X X SEL H L H H L 1B X X L H X 2B X X X X L Output A A0 A0 L H L
*1 *1
B-to-A storage (OEA = L)
H : High level L : Low level X : Immaterial Z : High impedance : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established.
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HD74ALVCHR162269A
Pin Arrangement
OEA 1 OEB1 2 2B3 3 GND 4 2B2 5 2B1 6 VCC 7 A1 8 A2 9 A3 10 GND 11 A4 12 A5 13 A6 14 A7 15 A8 16 A9 17 GND 18 A10 19 A11 20 A12 21 VCC 22 1B1 23 1B2 24 GND 25 1B3 26 NC 27 SEL 28
56 OEB2 55 CLKENA2 54 2B4 53 GND 52 2B5 51 2B6 50 VCC 49 2B7 48 2B8 47 2B9 46 GND 45 2B10 44 2B11 43 2B12 42 1B12 41 1B11 40 1B10 39 GND 38 1B9 37 1B8 36 1B7 35 VCC 34 1B6 33 1B5 32 GND 31 1B4 30 CLKENA1 29 CLK
(Top view)
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HD74ALVCHR162269A
Absolute Maximum Ratings
Item Supply voltage range Input voltage range
*1, 2
Symbol VCC VI
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VCC +0.5
Unit V V
Conditions
Except I/O ports I/O ports
Output voltage range Input clamp current Output clamp current
*1, 2
VO I IK I OK IO I CC / IGND PT Tstg
-0.5 to VCC +0.5 -50 50 50 100 1 -65 to 150
V mA mA mA mA W C TSSOP VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
Continuous output current Continuous current through Maximum power dissipation at Ta = 55C (in still air) *3 Storage temperature range Notes:
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum power dissipation is calculated using a junction temperature of 150C and board trace length of 750 mils.
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage High-level output current Symbol VCC VI VO I OH Min 2.3 0 0 -- -- -- Low-level output current I OL -- -- -- Input transition rise or fall rate Operating free-air temperature t / v Ta 0 -40 Max 3.6 VCC VCC -6 -8 -12 6 8 12 10 85 ns / V C mA Unit V V V mA VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V Conditions
Note: Unused or floating control pins must be held high or low.
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HD74ALVCHR162269A
Logic Diagram
CLK OEB1 OEB2 CLKENA1 CLKENA2 SEL OEA
1D C1 C1 1D SEL C1 1D C1 1D
A1
C1 1D
G1 1 1 CE C1 1D
1B1
2B1
CE C1 1D
1 of 12 Channels
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HD74ALVCHR162269A
Electrical Characteristics (Ta = -40 to 85C)
Item Input voltage Symbol VCC (V) VIH 2.3 to 2.7 2.7 to 3.6 VIL 2.3 to 2.7 2.7 to 3.6 Output voltage VOH Min 1.7 2.0 -- -- Max -- -- 0.7 0.8 -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 5.0 -- -- -- -- 500 10 40 750 A A A V I OH = -100 A I OH = -4 mA, VIH = 1.7 V I OH = -6 mA, VIH = 1.7 V I OH = -4 mA, VIH = 2.0 V I OH = -8 mA, VIH = 2.0 V I OH = -6 mA, VIH = 2.0 V I OH = -12 mA, VIH = 2.0 V I OL = 100 A I OL = 4 mA, VIL = 0.7 V I OL = 6 mA, VIL = 0.7 V I OL = 4 mA, VIL = 0.8 V I OL = 8 mA, VIL = 0.8 V I OL = 6 mA, VIL = 0.8 V I OL = 12 mA, VIL = 0.8 V VIN = VCC or GND VIN = 0.7 V VIN = 1.7 V VIN = 0.8 V VIN = 2.0 V VIN = 0 to 3.6 V VOUT = VCC or GND VIN = VCC or GND One input at (V CC-0.6) V, other inputs at V CC or GND Unit V Test Conditions
Min to Max VCC-0.2 2.3 2.3 2.7 2.7 3.0 3.0 1.9 1.7 2.2 2.0 2.4 2.0
VOL
Min to Max -- 2.3 2.3 2.7 2.7 3.0 3.0 -- -- -- -- -- -- -- 45 -45 75 -75 -- -- -- --
Input current
I IN I IN (hold)
3.6 2.3 2.3 3.0 3.0 3.6
Off state output current
*1
I OZ I CC
3.6 3.6 3.0 to 3.6
Quiescent supply current I CC
Notes: 1.
For I/O ports, the parameter I OZ includes the input leakage current.
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HD74ALVCHR162269A
Switching Characteristics (Ta = -40 to 85C)
Item Symbol VCC (V) 2.50.2 2.7 3.30.3 Propagation delay time t PLH t PHL 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Output enable time t ZH t ZL 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Output disable time t HZ t LZ 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Input capacitance Output capacitance CIN CO 3.3 3.3 Min -- -- 135 -- -- 2.0 -- -- 1.0 -- -- 2.0 -- -- 1.0 -- -- 2.0 -- -- 1.0 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.5 9.0 Max -- -- -- -- -- 5.0 -- -- 4.0 -- -- 5.0 -- -- 4.5 -- -- 5.0 -- -- 4.5 -- -- pF pF CLK A ns CLK B CLK A ns CLK B CLK A ns CLK B Unit MHz From (Input) To (Output)
Maximum clock frequency f max
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HD74ALVCHR162269A
Switching Characteristics (Ta = -40 to 85C) (cont)
Item Setup time Symbol t su VCC (V) 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Hold time th 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Pulse width tw 2.50.2 2.7 3.30.3 Min -- -- 1.0 -- -- 1.0 -- -- 1.0 -- -- 1.0 -- -- 1.0 -- -- 0.5 -- -- 0.5 -- -- 0.5 -- -- 0.5 -- -- 0.5 -- -- 2.0 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns CLK "H" or "L" CLKENA1 or CLKENA2 after CLK "H" or "L" OE after CLK "H" or "L" SEL aftrer CLK "H" or "L" B data after CLK "H" or "L" ns A data after CLK "H" or "L" CLKENA1 or CLKENA2 before CLK "H" or "L" OE before CLK "H" or "L" SEL before CLK "H" or "L" B data before CLK "H" or "L" Unit ns FROM (Input) A data before CLK "H" or "L"
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HD74ALVCHR162269A
Test Circuit
See the table below 500 S1 OPEN
*1
GND 500
CL = 50 pF
Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ
Vcc=2.50.2V Vcc=2.7V, 3.30.15V
OPEN GND 4.6 V
OPEN GND 6.0 V
Note: 1. CL includes probe and jig capacitance.
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HD74ALVCHR162269A
Waveforms - 1
tr 90 % 90 % Vref 10 %
tf VIH Vref 10 % GND VIH
CLK
Data Input t PLH t PHL GND
VOH Output Vref Vref VOL
Waveforms - 2
VIH Timing Input tsu Vref Vref th Vref GND tw VIH CLK Vref Vref GND GND VIH Data Input
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HD74ALVCHR162269A
Waveforms - 3
Output Control
VIH GND tr 90 % 90 % Vref 10 % 10 % tf VIH Vref GND
CLK
t ZL Waveform - A t ZH Waveform - B Vref Vref
t LZ V OH1 VOL + 0.3 V t HZ VOH - 0.3 V VOL VOH V OL1 TEST VIH Vref VOH1 VOL1
Vcc=2.50.2V Vcc=2.7V, 3.30.15V
2.3 V 1.2 V 2.3 V GND
2.7 V 1.5 V 3.0 V GND
Note: 1. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, tr 2.5ns, tf 2.5ns. 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The outputs are measured one at a time with one transition per measurement.
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HD74ALVCHR162269A
Package Dimensions
Unit : mm
14.00 -0.1 56
+0.3
29 6.10 +0.3 -0.1
1 0.20 +0.1 -0.05
0.50 28 0.08 M 8.10 0.3 10 Max 0.05 0.05 1.2 Max 0.15 0.05
0.40 Max
0.10
0.50 0.1 Hitachi code EIAJ code JEDEC code TTP-56D -- --
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

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