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Apr. 2001
Ver 1.0
8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS87C1304(2)A HMS87C1204(2)A HMS87C1104(2)A
User's Manual
HMS87C130XA/120XA/110XA
1. OVERVIEW ....................................................................................................................... 1 1.1 1.2 1.3 1.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. BLOCK DIAGRAM ........................................................................................................... 4 3. PIN ASSIGNMENT ........................................................................................................... 5 4. PACKAGE DIAGRAM ...................................................................................................... 6 5. PIN FUNCTION ................................................................................................................. 9 6. PORT STRUCTURES ..................................................................................................... 11 7. ELECTRICAL CHARACTERISTICS .............................................................................. 16 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. MEMORY ORGANIZATION ........................................................................................... 22 8.1 8.2 8.3 8.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9. I/O PORTS ...................................................................................................................... 34 9.1 9.2 9.3 9.4 RA and RAIO registers RB and RBIO registers RC and RCIO registers RD and RDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10. CLOCK GENERATOR ................................................................................................. 38 10.1 Oscillation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11. BASIC INTERVAL TIMER ............................................................................................ 40 12. TIMER / COUNTER ...................................................................................................... 41 12.1 8-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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12.2 12.3 12.4 12.5 12.6
16-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8-bit Compare Output (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 16-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13. BUZZER OUTPUT FUNCTION .................................................................................... 50 14. ANALOG TO DIGITAL CONVERTER .......................................................................... 51 15. INTERRUPTS ............................................................................................................... 54 15.1 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.2 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 16. WATCHDOG TIMER .................................................................................................... 59 17. POWER SAVING MODE .............................................................................................. 60 17.1 Minimizing Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18. RESET .......................................................................................................................... 66 19. POWER FAIL PROCESSOR ........................................................................................ 68 20. OTP PROGRAMMING .................................................................................................. 70 20.1 DEVICE CONFIGURATION AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 APPENDIX Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Apr. 2001 ver 1.0
HMS87C130XA/120XA/110XA
HMS87C1304A / HMS87C1302A HMS87C1204A / HMS87C1202A HMS87C1104A / HMS87C1102A
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
1. OVERVIEW
1.1 Description
The HMS87C1X0XA is an advanced CMOS 8-bit microcontroller with 4K/2K bytes of EPROM. The Hynix HMS87C1X0XA is a powerful microcontroller which provide a highly flexible and cost effective solution to many small applications such as controller for battery charger. The HMS87C1X0XA provides the following standard features: 4K/2K bytes of EPROM, 128bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit high speed PWM output, programmable buzzer driving port, power-on reset circuit, on-chip oscillator and clock circuitry. In addition, the HMS87C1X0XA supports power saving modes to reduce power consumption. This document is only explained for the base of HMS87C1304A, the other's eliminated functions are same as below.
Device name HMS87C1304A HMS87C1302A HMS87C1204A HMS87C1202A HMS87C1104A HMS87C1102A EPROM 4K bytes 2K bytes 4K bytes 2K bytes 4K bytes 2K bytes RAM 128bytes 128bytes 128bytes 128bytes 128bytes 128bytes EXT.INT 2 2 2 2 1 1 BUZ O O O O X X I/O 19 19 15 15 11 11 Operating Voltage 2.0 ~ 5.5V 2.0 ~ 5.5V 2.0 ~ 5.5V 2.0 ~ 5.5V 2.0 ~ 5.5V 2.0 ~ 5.5V Package 24 SKDIP or SOP 24 SKDIP or SOP 20 PDIP or SOP 20 PDIP or SOP 16 PDIP or SOP 16 PDIP or SOP
1.2 Features
* 4K/2K Bytes On-chip Program Memory * 128 Bytes of On-chip Data RAM (Included stack memory) * Instruction Cycle Time: - 250nS at 8MHz * Programmable I/O pins (LED direct driving can be source and sink) - HMS87C1304A/1302A : 19 - HMS87C1204A/1202A : 15 - HMS87C1104A/1102A : 11 * 2.0V to 5.5V Wide Operating Range * 8-bit A/D Converter - 8 channels * One 8-bit Basic Interval Timer * Two 8-bit Timer / Counters * One 10-bit High Speed PWM Outputs * Watchdog timer * Seven Interrupt sources - External input: 2 ( 1 for HMS87C1104/2A ) - A/D Conversion: 1 - Timer: 4 * One Programmable Buzzer Driving port ( except HMS87C1104/2A ) - 500Hz ~ 130kHz
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* Oscillator Type - Crystal - Ceramic Resonator - RC-oscillation ( C can be omitted ) * Power-On Reset
* Noise Immunity Circuit - Power Fail Processor * Power Down Mode - STOP mode - Wake-up Timer mode - Internal RC-WDT mode
1.3 Development Tools
The HMS87C1X0XA is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-DrTM and OTP programmers. The marco assembler operates under the MS-Windows 95/ 98TM. The OTP programmer can be supplied three types of programmer such as emulator add-on board type single programmer (Dr.WriterTM), univeral stand-alone type single programmer (CHOICE-SIGMATM) and gang type programmer (CHOICE-SIGMATM). .
In Circuit Emulators Assembler CHOICE-Dr. TM Hynix Macro Assembler Single Programmer : Dr. WriterTM Universal Programmer : CHOICEOTP Programmer SIGMATM Gang Programmer : CHOICE-GANG4TM Figure 1-2 OTP Single Programmer Dr.WriterTM
Figure 1-3 OTP Gang Programmer CHOICE-GANG4TM
Figure 1-1 In Circuit Emulator CHOICE-Dr.TM
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1.4 Ordering Information
ROM Size Package Type 24 SKDIP 24 SOP 4K bytes (OTP) 20 PDIP 20 SOP 16 PDIP 16 SOP 24 SKDIP 24 SOP 2K bytes (OTP) 20 PDIP 20 SOP 16 PDIP 16 SOP Ordering Device Code HMS87C1304A SK HMS87C1304A D HMS87C1204A HMS87C1204A D HMS87C1104A HMS87C1104A D HMS87C1302A SK HMS87C1302A D HMS87C1202A HMS87C1202A D HMS87C1102A HMS87C1102A D Operating Temperature
-20 ~ +85C
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2. BLOCK DIAGRAM
PSW
ALU
Accumulator
Stack Pointer Data Memory
PC
RESET
System controller System Clock Controller Timing generator 8-bit Basic Interval Timer Inte rrupt C ontroller
Program Memory Data Table
XIN XOUT
Clock Generator Instruction Decoder Watch-dog Timer 8-bit A/D Converter 8-bit Timer/ Counter High Speed PWM B uzzer D river
VDD VSS Power Supply RA0 / EC0 RA1 / AN1 RA2 / AN2 RA3 / AN3 RA4 / AN4 RA5 / AN5 RA6 / AN6 RA7 / AN7 RB0 / AN0 / AVREF RB1 / BUZ RB2 / INT0 RB3 / INT1 RB4 / CMP0 / PWM0 RC0 RC1 RD0 , RD1 , RD2 , RD3 , RA RB RC RD
Note

These pins are not available in HMS87C1204(2)A. These pins are not available in HMS87C1104(2)A.
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3. PIN ASSIGNMENT
HMS87C1304(2)A SK
24 SKDIP
AN4 / RA4 AN5 / RA5 AN6 / RA6 AN7 / RA7 VDD RD0 RD1 AN0 / AVREF/ RB0 BUZ / RB1 INT0 / RB2 INT1 / RB3 PWM0 / COMP0 / RB4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RA3 / AN3 RA2 / AN2 RA1 / AN1 RA0 / EC0 RC1 RC0 VSS RESET XOUT XIN RD3 RD2
HMS87C1304(2)A D
24 SOP
AN4 / RA4 AN5 / RA5 AN6 / RA6 AN7 / RA7 VDD RD0 RD1 AN0 / AVREF / RB0 BUZ / RB1 INT0 / RB2 INT1 / RB3 PWM0 / COMP0 / RB4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RA3 / AN3 RA2 / AN2 RA1 / AN1 RA0 / EC0 RC1 RC0 VSS RESET XOUT XIN RD3 RD2
HMS87C1204(2)A
20 PDIP
AN4 / RA4 AN5 / RA5 AN6 / RA6 AN7 / RA7 VDD AN0 / AVREF / RB0 BUZ / RB1 INT0 / RB2 INT1 / RB3 PWM0 / COMP0 / RB4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA3 / AN3 RA2 / AN2 RA1 / AN1 RA0 / EC0 RC1 RC0 VSS RESET XOUT XIN
HMS87C1204(2)A D
20 SOP
AN4 / RA4 AN5 / RA5 AN6 / RA6 AN7 / RA7 VDD AN0 / AVREF / RB0 BUZ / RB1 INT0 / RB2 INT1 / RB3 PWM0 / COMP0 / RB4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA3 / AN3 RA2 / AN2 RA1 / AN1 RA0 / EC0 RC1 RC0 VSS RESET XOUT XIN
HMS87C1104(2)A
16 PDIP
AN4 / RA4 AN5 / RA5 AN6 / RA6 AN7 / RA7 VDD AN0 / AVREF / RB0 INT0 / RB2 PWM0 / COMP0 / RB4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RA3 / AN3 RA2 / AN2 RA1 / AN1 RA0 / EC0 VSS RESET XOUT XIN
HMS87C1104(2)A D
16 SOP
AN4 / RA4 AN5 / RA5 AN6 / RA6 AN7 / RA7 VDD AN0 / AVREF / RB0 INT0 / RB2 PWM0 / COMP0 / RB4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RA3 / AN3 RA2 / AN2 RA1 / AN1 RA0 / EC0 VSS RESET XOUT XIN
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4. PACKAGE DIAGRAM
24 SKDIP
unit: inch MAX MIN
TYP 0.300 1.265 MIN 0.015 1.160 MAX 0.180 0.300 0.250
0.140
0.120
0.021 0.015 0.065 0.045 TYP 0.100 0 ~ 15
4 0.01 8 0.00
24 SOP
0.292
0.299
0.104 0.093
0.0118 0.004
0.614 0.593
0.419 0.398
0.0125
TYP 0.050
6
0.009
0.019 0.0138
0 ~ 8 0.042 0.016
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20 PDIP
unit: inch MAX MIN
TYP 0.300 1.043 MIN 0.015 1.010 MAX 0.180 0.270 0.245
0.140
0.120
0.021 0.015 0.065 0.050 TYP 0.100 0 ~ 15
4 0.01 .008 0
20 SOP
0.291
0.299
0.104 0.093
0.0118 0.004
0.5118 0.4961
0.419 0.398
0.0125
0.0091
0.020 0.013
0 ~ 8 TYP 0.050 0.042 0.016
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16 PDIP
unit: inch MAX MIN
TYP 0.300 0.765 MIN 0.015 0.745 MAX 0.180 0.260 0.240
0.140
0.120
0.022 0.015 0.065 0.050 TYP 0.100 0 ~ 15
4 0.01 .008 0
16 SOP
0.292
0.299
0.104 0.094
0.0118 0.004
0.412 0.402
0.416 0.398
0.0125
0.0091
0.019 0.014
0 ~ 8 TYP 0.050 0.040 0.016
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5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. RA0~RA7: RA is an 8-bit, CMOS, bidirectional I/O port. RA pins can be used as outputs or inputs according to "1" or "0" written the their Port Direction Register(RAIO).
Port pin RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 Alternate function EC0 ( Event Counter Input Source ) AN1 ( Analog Input Port 1 ) AN2 ( Analog Input Port 2 ) AN3 ( Analog Input Port 3 ) AN4 ( Analog Input Port 4 ) AN5 ( Analog Input Port 5 ) AN6 ( Analog Input Port 6 ) AN7 ( Analog Input Port 7 ) Table 5-1 RA Port
RB serves the functions of the various following special features in Table 5-2.
Port pin RB0 RB1 1 RB2 RB3 1 RB4 Alternate function AN0 ( Analog Input Port 0 ) AVREF ( External Analog Reference Pin ) BUZ ( Buzzer Driving Output Port ) INT0 ( External Interrupt Input Port 0 ) INT1 ( External Interrupt Input Port 1 ) PWM0 (PWM0 Output) COMP0 (Timer1 Compare Output) Table 5-2 RB Port
1. These pins are not available in HMS87C1104(2)A.
RC0, RC1: RC is a 2-bit, CMOS, bidirectional I/O port. RC pins can be used as outputs or inputs according to "1" or "0" written the their Port Direction Register(RCIO). And these pins are not available in HMS87C1104(2)A. RD0~RD3: RD is a 4-bit, CMOS, bidirectional I/O port. RC pins can be used as outputs or inputs according to "1" or "0" written the their Port Direction Register(RDIO). And these pins are not available in HMS87C1204(2)A and HMS87C1104(2)A.
In addition, RA serves the functions of the various special features in Table 5-1. RB0~RB4: RB is an 8-bit, CMOS, bidirectional I/O port. RB pins can be used as outputs or inputs according to "1" or "0" written the their Port Direction Register(RBIO).
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HMS87C130XA/120XA/110XA
PIN NUMBER PIN NAME 87C1304(2)A 87C1204(2)A 87C1104(2)A
VDD VSS RESET XIN XOUT RA0 (EC0) RA1 (AN1) RA2 (AN2) RA3 (AN3) RA4 (AN4) RA5 (AN5) RA6 (AN6) RA7 (AN7) RB0 (AVref/AN0) RB1 (BUZ) RB2 (INT0) RB3 (INT1) RB4 (PWM0/ COMP0) RC0 RC1 RD0 RD1 RD2 RD3 5 18 17 15 16 21 22 23 24 1 2 3 4 8 9 10 11 12 19 20 6 7 13 14 5 14 13 11 12 17 18 19 20 1 2 3 4 6 7 8 9 10 15 16 5 12 11 9 10 13 14 15 16 1 2 3 4 6
I I O I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Output) I/O (Output/ Output) I/O I/O I/O I/O I/O I/O
Function In/Out Basic
Supply voltage Circuit ground Reset signal input
Sencondary
External Event Counter input 0 Analog Input Port 1 Analog Input Port 2 8-bit general I/O ports Analog Input Port 3 Analog Input Port 4 Analog Input Port 5 Analog Input Port 6 Analog Input Port 7 Analog Input Port 0 / Analog Reference Buzzer Driving Output 5-bit general I/O ports External Interrupt Input 0 External Interrupt Input 1 PWM0 Output or Timer1 Compare Output 2-bit general I/O ports
4-bit general I/O ports
Table 5-3 Pin Description
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6. PORT STRUCTURES
* RESET
Internal RESET
VSS
* Xin, Xout
Crystal or Ceramic
VDD
Xout
VSS STOP To System CLK Xin
RC Oscillation (refer to Configuration Area)
VDD
Xout
STOP VSS
To System CLK Xin
Internal Capacitor 6 pF
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* RA0/EC0
Open Drain Data Reg. Data Bus
Direction Reg. Data Bus
Data Bus Read EC0 Schmitt Trigger
* RA1/AN1 ~ RA7/AN7
VDD Data Reg. Data Bus
Direction Reg. Data Bus VSS Data Bus Read To A/D Converter
Analog Input Mode (ANSEL7 ~ 1) Analog CH. Selection (ADCM.4 ~ 2)
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* RB0 / AN0 / AVref
VDD Data Reg. Data Bus
AVREFS Data Bus
Direction Reg.
VSS Data Bus Read To A/D Converter
Analog Input Mode (ANSEL0) Analog CH0 Selection (ADCM.4 ~ 2)
1
Internal VDD To Vref of A/D
0
AVREFS
* RB1/BUZ, RB4/PWM0/COMP0
PWM/COMP BUZ Data Reg. Data Bus Function Select Data Bus VSS Data Bus
1
VDD
0
Direction Reg.
Read
Note: RB1/BUZ pin is not available in HMS87C1104(2)A.
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HMS87C130XA/120XA/110XA
* RB2/INT0, RB3/INT1
Open Drain Pull-up Select Data Reg. Data Bus VDD
Weak Pull-up
Function Select Data Bus
Direction Reg.
VSS Data Bus Read INT0, INT1 Schmitt Trigger
Note: RB3/INT1 pin is not available in HMS87C1104(2)A .
* RC0, RD2, RD3
Data Reg. Data Bus
Direction Reg. Data Bus
Data Bus Read
Note: RC0, RD2, RD3 pins are not available in HMS87C1104(2)A
Note: RD2, RD3 pins are not available in HMS87C1204(2)
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* RC1
Open Drain Data Reg. Data Bus VDD
Direction Reg. Data Bus VSS Data Bus Read
* RD0, RD1
Pull-up Select Data Reg. Data Bus VDD
Weak Pull-up
Direction Reg. Data Bus
VSS Data Bus Read
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7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of VSS pin ........................200 mA Maximum current into VDD pin ..........................150 mA Maximum current sunk by (IOL per I/O Pin) ........25 mA Maximum output current sourced by (IOH per I/O Pin) ...............................................................................15 mA Maximum current (IOL) ....................................150 mA Maximum current (IOH).................................... 100 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Specifications Parameter Symbol Condition Min. Supply Voltage VDD fXIN=8MHz fXIN=4.2MHz VDD=4.5~5.5V VDD=2.0~5.5V 4.5 2.0 1 1 -20 Max. 5.5 5.5 8 4.2 85 V V MHz MHz C Unit
Operating Frequency Operating Temperature
fXIN TOPR
7.3 A/D Converter Characteristics
(TA=25C, VSS=0V, VDD=5.12V @fXIN =8MHz, VDD=3.072V @fXIN =4MHz)
Specifications Parameter Symbol Condition Min. Analog Input Voltage Range VAIN AVREFS=0 AVREFS=1 VDD=5V VDD=3V VSS VSS 3 2.4 fXIN=8MHz fXIN=4MHz AVREFS=1 Typ. 1.0 1.0 1.0 0.5 0.25 1.0 0.5 Max. VDD VREF VDD VDD 1.5 1.5 1.5 1.5 0.5 1.5 10 20 1.0 V V V LSB LSB LSB LSB LSB LSB S mA Unit
Analog Power Supply Input Voltage Range Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time AVREF Input Current
VREF NACC NNLE NDNLE NZOE NFSE NNLE TCONV IREF
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7.4 DC Electrical Characteristics
(TA=-20~85C, VDD=2.0~5.5V, VSS=0V),
Specifications Parameter Symbol VIH1 Input High Voltage VIH2 VIH3 VIL1 Input Low Voltage VIL2 VIL3 Output High Voltage Output Low Voltage Input Pull-up Current2 Input High Leakage Current Input Low Leakage Current Hysteresis PFD Voltage Internal RC WDT Period Operating Current3 Wake-up Timer Mode Current RCWDT Mode Current at STOP Mode Stop Mode Current VOH VOL IP IIH1 IIH2 IIL1 IIL2 | VT | VPFD1 VPFD2 TRCWDT RESET XIN, Hysteresis Input1 Normal Input RESET XIN, Hysteresis Input1 Normal Input All Output Port All Output Port RB2, RB3, RD0, RD1 All Pins (except XIN) XIN All Pins (except XIN) XIN Hysteresis Input1 VDD VDD VDD=5V, IOH=-5mA VDD=5V, IOL=10mA VDD=5V VDD=5V VDD=5V VDD=5V VDD=5V VDD=5V PFD Level = 0, VDD=5V PFD Level = 1, VDD=3V VDD=5.0V, fXIN=8MHz VDD=3.0V, fXIN=4MHz VDD VDD=5.5V, fXIN=8MHz VDD=3.0V, fXIN=4MHz VDD=5.5V, fXIN=8MHz VDD=3.0V, fXIN=4MHz VDD=5.5V IRCWDT VDD VDD=3.0V VDD=5.5V, fXIN=8MHz VDD=3.0V, fXIN=4MHz VDD=5V, R=10K, C=20pF VDD=5V, R=10K Pin Condition Min. 0.8 VDD 0.8 VDD 0.7 VDD 0 0 0 VDD -1
-
Unit Typ. -380 2.5 1.7 Max. VDD VDD VDD 0.2 VDD 0.2 VDD 0.3 VDD 1 -300 5 15 3.0 V 1.5 60 150 3 5 2 1 0.1 0.03 0.7 0.2 1.9 200 300 5 2 0.5 0.1 50 30 1.6 0.8 5 MHz 9 A mA S V V A A A A A V V V
-450 -5 -15 0.5 2.0
IDD
mA
IWKUP
VDD
ISTOP
VDD
A
External RC Oscillator Frequency
FRC
XOUT
1. Hysteresis Input: RA0, RB2, RB3 2. This parameter is valid when the bit PUPSELx is selected and set the input mode or interrupt input function. 3. This value is measured under NOP instruction execution.
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HMS87C130XA/120XA/110XA
7.5 AC Characteristics
(TA=-20~+85C, VDD=5V10%, VSS=0V)
Specifications Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time External Input Pulse Width RESET Input Width Symbol fCP tCPW tRCP,tFCP tST tEPW tRST Pins Min. XIN XIN XIN XIN, XOUT INT0, INT1, EC0 RESET 1 80 2 8 Typ. Max. 8 20 20 MHz nS nS mS tSYS tSYS Unit
1/fCP
tCPW
tCPW VDD-0.5V
XIN
tSYS tRCP tFCP
0.5V
tRST
RESET
0.2VDD
tEPW
tEPW 0.8VDD
INT0, INT1 EC0
0.2VDD
Figure 7-1 Timing Chart
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7.6 Typical Characteristics
This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation
Operating Area
fXIN (MHz) Ta= 25C 10 8 6 4 2 0 2 3 4 5 6 VDD (V) IDD (mA) 4 3
Normal Operation (NOP) IDD-VDD
Ta=25C
fXIN = 8MHz 2 1 4MHz 0 2 3 4 5 VDD 6 (V)
STOP Mode ISTOP-VDD
IDD (A) 2.0 1.5 1.0 0.5 0 2 3 4 5 VDD 6 (V) fXIN = 8MHz -25C 25C 85C 1.5 IDD (mA) 2.0
Wake-up Timer Mode IWKUP-VDD
Ta=25C
fXIN = 8MHz 1.0 0.5 0 2 3 4 5
4MHz VDD 6 (V)
RC-WDT in Stop Mode IRCWDT-VDD
IDD (A) 20 15 10 5 0 2 3 4 5 VDD 6 (V) TRCWDT = 180uS Ta=25C
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IOL-VOL, VDD=5V
IOL (mA) 40 -25C 25C 85C 30 -15 IOH (mA) -20
IOH-VOH, VDD=5V
-25C 25C 85C
20
-10
10 0 0.5 1 1.5 2 VOL 2.5 (V)
-5 0 2 3 4 5 VOH 6 (V)
VIH1 (V) 4 3 2 1 0
VDD-VIH1 XIN, RESET
fXIN=4MHz Ta=25C
VDD-VIH2
VIH2 (V) 4 3 2 1 VDD 6 (V) 0 2 3 f XIN =4M H z Ta=25C
Hysteresis input
VDD-VIH3
VIH3 (V) 4 3 2 1 f XIN =4M H z Ta=25C
Normal input
1
2
3
4
5
4
5
VDD 6 (V)
0 2 3 4 5
VDD 6 (V)
VIL1 (V) 4 3 2 1 0
VDD-VIL1 XIN, RESET
fXIN=4MHz Ta=25C
VDD-VIL2
VIL2 (V) 4 3 2 1 VDD 6 (V) 0 2 3 f XIN =4M H z Ta=25C
Hysteresis input
VDD-VIL3
VIL3 (V) 4 3 2 1 f XIN =4M H z Ta=25C
Normal input
1
2
3
4
5
4
5
VDD 6 (V)
0 2 3 4 5
VDD 6 (V)
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With External Capacitor REXT CEXT 10pF 10K 20pF 40pF 10pF 30K 20pF 40pF 10pF 50K 20pF 40pF fOSC @ 5V,25C 4.9MHz 3.35MHz 2.12MHz 1.81MHz 1.21MHz 0.75MHz 1.11MHz 0.74MHz 0.46MHz fOSC @ 3V,25C 3.94MHz 2.72MHz 1.74MHz 1.57MHz 1.04MHz 0.65MHz 0.98MHz 0.65MHz 0.40MHz
Without External Capcitor fOSC @ 5V,25C fOSC @ 3V,25C
7.29MHz
5.1MHz
2.96MHz
2.37MHz
1.85MHz
1.55MHz
Table 7-1 RC Oscillation Frequencies (with CEXT and without CEXT)
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8. MEMORY ORGANIZATION
The HMS87C1X0XA has separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 2K/4K bytes of Program memory. Data memory can be read and written to up to 128 bytes including the stack area.
8.1 Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD Stack Address (000H ~ 07FH) 15 0 8 7 SP 0
Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00H to 7FH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "7FH" is used.
Figure 8-1 Configuration of Registers
Hardware fixed
Accumulator: The Accumulator is an 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below.
Y
Y A
Note: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP LDX #07FH TXSP ; SP 7FH
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result.
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore).
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MSB PSW NEGATIVE FLAG OVERFLOW FLAG BRK FLAG
LSB
N
V
-
B
H
I
Z
C
RESET VALUE: 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector ad-
dress. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
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8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 4K/2K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-4, shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-5. As shown in Figure 8-4, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. Example: Usage of TCALL
LDA #5 TCALL 0FH : : ;1BYTE INSTR UCTIO N ;INSTEAD OF 3 BYTES ;NOR M AL C ALL
F000H
; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B
1
;TCALL ADDRESS AREA
HMS87C1304A
F800H PROGRAM MEMORY FEFFH FF00H FFC0H FFDFH FFE0H FFFFH PCALL AREA
TCALL AREA INTERRUPT VECTOR AREA
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. As for the area from 0FF00H to 0FFFFH, if any area of them is not going to be used, its service location is available as general purpose Program Memory.
Address 0FFE0H Vector Area Memory Basic Interval Interrupt Vector Area Watchdog Timer Interrupt Vector Area A/D Converter Interrupt Vector Area Timer/Counter 1 Interrupt Vector Area Timer/Counter 0 Interrupt Vector Area External Interrupt 1 Vector Area External Interrupt 0 Vector Area RESET Vector Area
Figure 8-4 Program Memory Map
Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-6.
HMS87C1302A
E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE
NOTE: "-" means reserved area.
Figure 8-5 Interrupt Vector Area
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Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *
Address 0FF00H
PCALL Area Memory
PCALL Area (256 Bytes)
0FFFFH
NOTE: * means that the BRK software interrupt is using same address with TCALL0.
Figure 8-6 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35
4A
01001010
~ ~ ~ ~
0F125H NEXT
~ ~
Reverse
~ ~
0FF00H 0FF35H NEXT
PC: 11111111 11010110 FH FH DH 6H
0FF00H 0FFD6H 25 F1
0FFFFH
0FFD7H 0FFFFH
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Example: The usage software example of Vector address and the initialize part.
ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H NOT_USED NOT_USED NOT_USED BIT_INT WDT_INT AD_INT NOT_USED NOT_USED NOT_USED NOT_USED TMR1_INT TMR0_INT INT1 INT0 NOT_USED RESET 0F000H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; (0FFE0) (0FFE2) (0FFE4) (0FFE6) (0FFE8) (0FFEA) (0FFEC) (0FFEE) (0FFF0) (0FFF2) (0FFF4) (0FFF6) (0FFF8) (0FFFA) (0FFFC) (0FFFE)
Basic Interval Timer Watchdog Timer A/D
Timer-1 Timer-0 Int.1 Int.0 Reset
;******************************************** ; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!007FH) STA {X}+ CMPX #080H BNE RAM_CLR ; LDX #07FH ;Stack Pointer Initialize TXSP ; CALL INITIAL ; ; LDM RA, #0 ;Normal Port A LDM RAIO,#1000_0010B ;Normal Port Direction LDM RB, #0 ;Normal Port B LDM RBIO,#0000_0010B ;Normal Port Direction : : LDM PFDR,#0 ;Enable Power Fail Detector : :
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8.3 Data Memory
Figure 8-7 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM (including Stack) and control registers.
0000H USER MEMORY (including STACK) 007FH 0080H 00BFH 00C0H 00FFH CONTROL REGISTERS PAGE0
Address 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0CAH 0CBH 0CCH 0D0H 0D1H 0D1H 0D1H 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H 0DEH 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH 0EFH
Symbol RA RAIO RB RBIO RC RCIO RD RDIO RAFUNC RBFUNC PUPSEL TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWM0HR BUR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR
R/W R/W W R/W W R/W W R/W W W W W R/W R W R R/W W W R R R/W W W R/W R/W R/W R/W R/W R/W R R W R W R/W
RESET Value Undefined 0000_0000 Undefined 0000_0000 Undefined ----_--00 Undefined ----_0000 0000_0000 0000_0000 ----_0000 --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 0000_---000-_---0000_---000-_-------_0000 --00_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_0100
Addressing m ode byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte byte byte byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit
Figure 8-7 Data Memory Map
User Memory The HMS87C1X0XA has 128 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section.
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
Table 8-1 Control Registers
1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.
Example; To write at CKCTLR
LDM CKCTLR,#09H ;Divide ratio /16
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Note: Several names are given at same address. Refer to below table.
When read Addr. D1H D3H D4H ECH T1
Timer Mode Capture Mode PWM Mode
When write
Timer Mode PWM Mode
Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save.
T0
CDR0 CDR1 BITR
-
TDR0 TDR1
T1PPR T1PDR
T1PDR
-
CKCTLR
Table 8-2 Various Register Name in Same Address
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Address C0H C1H C2H C3H C4H C5H C6H C7H CAH CBH CCH D0H D1H D2H D3H D4H D5H DEH E2H E3H E4H E5H E6H EAH EBH ECH ECH EDH EFH RA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA Port Data Register RA Port Direction Register RB Port Data Register RB Port Direction Register RC Port Data Register RC Port Direction Register RD Port Data Register RD Port Direction Register ANSEL7 TMR2OV ANSEL6 EC1I ANSEL5 PWM1O CAP0 ANSEL4 PWM0O T0CK2 ANSEL3 INT1I ANSEL2 INT0I ANSEL1 BUZO ANSEL0 AVREFS
RAIO RB RBIO RC RCIO RD RDIO RAFUNC RBFUNC PUPSEL TM0 T0/TDR0/ CDR0 TM1 TDR1/ T1PPR T1/CDR1/ T1PDR PWM0HR BUR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR1 CKCTLR1 WDTR PFDR2
PUPSEL3 PUPSEL2 PUPSEL1 PUPSEL0 T0CK1 T0CK0 T0CN T0ST
Timer0 Register / Timer0 Data Register / Capture0 Data Register POL 16BIT PWM0E CAP1 T1CK1 T1CK0 T1CN T1ST
Timer1 Data Register / PWM0 Period Register Timer1 Register / Capture1 Data Register / PWM0 Duty Register PWM0 High Register BUCK1 INT0E ADE INT0IF ADIF BUCK0 INT1E WDTE INT1IF WDTIF BUR5 T0E BITE T0IF BITIF ADEN BUR4 T1E T1IF ADS2 BUR3 IED1H ADS1 BUR2 IED1L ADS0 BUR1 IED0H ADST BUR0 IED0L ADSF
ADC Result Data Register Basic Interval Timer Data Register WDTCL WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0
7-bit Watchdog Counter Register PFDOPR PFDIS PFDM PFDS
Table 8-3 Control Registers of HMS87C1X0XA
These registers of shaded area can not be accessed by bit manipulation instruction as "SET1, CLR1", but should be accessed by register operation instruction as "LDM dp,#imm". 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator.
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8.4 Addressing Mode
The HMS87C1X0XA uses six addressing modes; * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing
0035H data
(3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example;
C535 LDA 35H ;A RAM[35H]
~ ~
~ ~
0F550H 0F551H C5 35
data A
(1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example:
0435 ADC #35H
MEMORY
(4) Absolute Addressing !abs Absolute addressing sets corresponding memory data to Data, i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example;
0735F0 ADC !0F035H ;A ROM[0F035H]
04 35
A+35H+C A
E45535
LDM
35H,#55H
0F035H
data
~ ~
~ ~
0F100H 0035H data data 55H 0F101H 0F102H 07 35 F0
A+data+C A
address: 0F035
0F100H 0F101H 0F102H
~ ~
E4 55 35
~ ~
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H.
983500 INC !0035H ;A RAM[035H]
X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; X=35H
DB LDA {X}+
0035H
data
~ ~
~ ~
0F100H 0F101H 0F102H 98 35 00

data+1 data
35H
data
~ ~
data A
address: 0035
~ ~
DB
36H X
(5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H
D4 LDA {X} ;ACCRAM[X].
X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; X=015H
15H
data
C645
LDA
45H+X
~ ~
data A
~ ~
0F550H D4
5AH data
~ ~
0F550H 0F551H C6 45
~ ~

45H+15H=5AH
data A
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Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H
D500FA LDA !0FA00H+Y
3F35
JMP
[35H]
35H 36H
0A F3
~ ~
0F30AH NEXT
~ ~
jump to address 0F30AH
~ ~
0FA00H 3F 35
~ ~
0F100H 0F101H 0F102H
D5 00 FA
0FA00H+55H=0FA55H
X indexed indirect [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; X=10H
1625 ADC [25H+X]
~ ~
0FA55H data
~ ~

data A
(6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example;
0FA00H 35H 36H 05 F4
~ ~
0F405H data
~ 0F405H ~
25 + X(10) = 35H
~ ~
~ ~
16 25
A + data + C A
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Y indexed indirect [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10H
1725 ADC [25H]+Y
Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example;
1F25F0 JMP [!0F025H]
PROGRAM MEMORY
25H 26H
05 F7
0F025H 0F026H
25 F8
~ ~
0F715H data
~ ~
0F705H + Y(10) = 0F715H
~ ~
~ ~
NEXT
jump to address 0F80AH
~ ~
0F825H
~ ~
0FA00H 17 25
~ ~
0FA00H 1F 25 F0
~ ~
A + data + C A
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9. I/O PORTS
The HMS87C1X0XA has four ports, RA, RB, RC and RD. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, when a initial reset state, all ports are used as a general purpose input port. All pins have data direction registers which can set these ports as output or input. An "1" in the port direction register defines the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify as an input pin. For example, to use the even numbered bit of RA as output ports and the odd numbered bits as input ports, write "55H" to address C1H (RA direction register) during initial setting as shown in Figure 9-1. Reading data register reads the status of the pins whereas writing to it will write to the port latch.
WRITE "55H" TO PORT RA DIRECTION REGISTER
C0H C1H C2H C3H
RA DATA RA DIRECTION RB DATA RB DIRECTION
01010101 76543210
BIT
IOI
OIOIO
7 6 5 4 3 2 1 0 PORT I: INPUT PORT O: OUTPUT PORT
Figure 9-1 Example of port I/O assignment
9.1 RA and RAIO registers
RA is an 8-bit bidirectional I/O port (address C0H). Each port can be set individually as input and output through the RAIO register (address C1H). RA1~RA7 ports are multiplexed with Analog Input Port (AN1~AN7) and RA0 port is multiplexed with Event Counter Input Port (EC0).
RA Data Register RA ADDRESS : C0H RESET VALUE : Undefined
select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Analog Input or External Event Counter Input, write "1" to the corresponding bit of RAFUNC.Regardless of the direction register RAIO, RAFUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (RA0/EC0 is controlled by RBFUNC)
PORT RA7/AN7 RAFUNC.7~0 Description
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
INPUT / OUTPUT DATA
0 1 0
RA6/AN6
RAIO ADDRESS : C1H RESET VALUE : 00000000
RA7 (Normal I/O Port) AN7 (ADS2~0=111) RA6 (Normal I/O Port) AN6 (ADS2~0=110) RA5 (Normal I/O Port) AN5 (ADS2~0=101) RA4 (Normal I/O Port) AN4 (ADS2~0=100) RA3 (Normal I/O Port) AN3 (ADS2~0=011) RA2 (Normal I/O Port) AN2 (ADS2~0=010) RA1 (Normal I/O Port) AN1 (ADS2~0=001) RA0 (Normal I/O Port) EC0 (T0CK2~0=111)
RA Direction Register
1 0
DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT
RA5/AN5
1 0
RA4/AN4
RA Function Selection Register RAFUNC
ADDRESS : CAH RESET VALUE : 00000000
1 0
RA3/AN3
ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
1 0
RA2/AN2
0 : RA4 1 : AN4 0 : RA5 1 : AN5 0 : RA6 1 : AN6 0 : RA7 1 : AN7
0 : RB0 1 : AN0 0 : RA1 1 : AN1 0 : RA2 1 : AN2 0 : RA3 1 : AN3
1 0
RA1/AN1
1
RA0/EC01
Figure 9-2 Registers of Port RA
The control register RAFUNC (address CAH) controls to
1. This port is not an Analog Input port, but Event Counter clock source input port. EC0 is controlled by setting TOCK2~0 = 111. The bit RAFUNC.0 (ANSEL0) controls the RB0/AN0/AVref port (Refer to Port RB).
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9.2 RB and RBIO registers
RB is a 5-bit bidirectional I/O port (address C2H). Each pin can be set individually as input and output through the RBIO register (address C3H). In addition, Port RB is multiplexed with various special features. The control register RBFUNC (address CBH) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as External interrupt or Timer compare output, write "1" to the correRB Data Register RB
sponding bit of RBFUNC. Regardless of the direction register RBIO, RBFUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features. And RB2/INT0, RB3/INT1 have a function of pull-up transistor by setting the PUPSEL0 and PUPSEL1 of PUPSEL register.
Pull-up Selection Register
ADDRESS : C2H RESET VALUE : Undefined
PUPSEL
-
ADDRESS : CCH RESET VALUE : ----0000
PUPSEL1 PUPSEL0
-
-
-
RB4 RB3 RB2 RB1 RB0
INPUT / OUTPUT DATA
RB1 / INT1 Pull-up 0 : No Pull-up 1 : With Pull-up
RB0 / INT0 Pull-up 0 : No Pull-up 1 : With Pull-up
RB Direction Register RBIO
Interrupt Edge Selection Register ADDRESS : C3H RESET VALUE : ---00000 IEDS
-
ADDRESS : E6H RESET VALUE : ----0000
IED1H IED1L IED0H IED0L
-
-
-
INT1
INT0
External Interrupt Edge Select DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT RB Function Selection Register RBFUNC
PWM0O INT1I INT0I BUZO AVREFS
ADDRESS : CBH RESET VALUE : ---00000
00 : Normal I/O port 01 : Falling (1-to-0 transition) 10 : Rising (0-to-1 transition) 11 : Both (Rising & Falling)
0 : RB4 1 : PWM0 Output or Compare Output 0 : RB3 1 : INT1
0 : RB0 when ANSEL0 = 0 AN0 when ANSEL0 = 1 1 : AVREF 0 : RB1 1 : BUZ Output 0 : RB2 1 : INT0
Figure 9-3 Registers of Port RB
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PORT
RBFUNC.4~0
Description
RB4/ PWM0/ COMP0 RB3/INT1
0 1 0 1 0 1 0 1 01 12
RB4 (Normal I/O Port) PWM0 Output / Timer1 Compare Output RB3 (Normal I/O Port) External Interrupt Input 1 RB2 (Normal I/O Port) External Interrupt Input 0 RB1 (Normal I/O Port) Buzzer Output RB0 (Normal I/O Port)/ AN0 (ANSEL0=1) External Analog Reference Voltage
RB2/INT0
RB1/BUZ
RB0/AN0/ AVREF
1. When ANSEL0 = "0", this port is defined for normal I/O port (RB0). When ANSEL0 = "1" and ADS2~0 = "000", this port can be used Analog Input Port (AN0). 2. When this bit set to "1", this port defined for AVREF, so it can not be used Analog Input Port AN0 and Normal I/O Port RB0.
9.3 RC and RCIO registers
RC is a 2-bit bidirectional I/O port (address C4H). Each pin can be set individually as input and output through the RCIO register (address C5H).
RC Data Register RC
ADDRESS : C4H RESET VALUE : Undefined
RC Direction Register RCIO
ADDRESS : C5H RESET VALUE : ------00
-
-
-
-
-
-
RC1
RC0
-
-
-
-
-
DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT
INPUT / OUTPUT DATA
Figure 9-4 Registers of Port RC
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9.4 RD and RDIO registers
RD is a 4-bit bidirectional I/O port (address C6H). Each pin can be set individually as input and output through the RDIO register (address C7H) And RD0, RD1 have a function of pull-up transistor by setting the PUPSEL2 and PUPSEL3 of PUPSEL register. .
Pull-up Selection Register ADDRESS : C6H RESET VALUE : Undefined PUPSEL
-
RD Data Register RD
ADDRESS : CCH RESET VALUE : ----0000
PUPSEL3 PUPSEL2 -
-
-
-
-
RD3 RD2 RD1 RD0
INPUT / OUTPUT DATA RD Direction Register RDIO ADDRESS : C7H RESET VALUE : -----0000
RD1 Pull-up 0 : No Pull-up 1 : With Pull-up
RD0 Pull-up 0 : No Pull-up 1 : With Pull-up
-
-
-
-
DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT
Figure 9-5 Registers of Port RD
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10. CLOCK GENERATOR
The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and peripheral hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator connected to the
OSCILLATION CIRCUIT fXIN
Xin and Xout pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the Xin pin and open the Xout pin.
CLOCK PULSE GENERATOR
Internal system clock
PRESCALER STOP WAKEUP
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512
/1024 /2048
Peripheral clock
Figure 10-1 Block Diagram of Clock Pulse Generator
10.1 Oscillation Circuit
XIN and XOUT are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip oscillator, as shown in Figure 10-2.
XOUT R1 XIN Vss
values of external components.
OPEN XOUT
C1 C2
External Clock Source
XIN Vss
Figure 10-3 External Clock Connections
Recommended: C1, C2 = 30pF10pF for Crystals R1 = 1M
Figure 10-2 Oscillator Connections
To drive the device from an external clock source, Xout should be left unconnected while Xin is driven as shown in Figure 10-3. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate
Note: When using a system clock oscillator, carry out wiring in the broken line area in Figure 10-2 to prevent any effects from wiring capacities. - Minimize the wiring length. - Do not allow wiring to intersect with other signal conductors. - Do not allow wiring to come near changing high current. - Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. - Do not fetch signals from the oscillator.
In addition, the HMS87C1X0XA has an ability for the external RC oscillated operation. It offers additional cost savings for timing insensitive applications. The RC
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oscillator frequency is a function of the supply voltage, the external resistor (REXT) and capacitor (CEXT) values, and the operating temperature. The user needs to take into account variation due to tolerance of external R and C components used. Figure 10-4 shows how the RC combination is connected to the HMS87C1X0XA.
Vdd
saving. However, the characteristics of external R only oscillation are more variable than external RC oscillation.
VDD REXT XIN
CINT 6pF
fXIN/4 REXT XIN
XOUT
CEXT
Cint 6pF
Figure 10-5 R Oscillator Connections
fXIN/4 XOUT
The oscillator frequency, divided by 4, is output from the Xout pin, and can be used for test purpose or to synchroze other logic.
Figure 10-4 RC Oscillator Connections
External capacitor (CEXT) can be omitted for more cost
To set the RC oscillation, it should be programmed RCOPT bit to "1" to CONFIG (707FH). ( Refer to Section "20.1". )
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11. BASIC INTERVAL TIMER
The HMS87C1X0XA has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 11-1.The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflows from FF H to 00H, this overflow causes to generate the Basic interval timer interrupt. The BITF is interrupt request flag of Basic interval timer. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL becomes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this mode, all of the block is halted except the oscillator, prescaler (only fxin/2048) and Timer0.
WAKEUP RCWDT STOP BTS[2:0]
If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR register which is located at same address of BITR (address ECH). Address ECH is read as BITR, written to CKCTLR. Therefore, the CKCTLR can not be accessed by bit manipulation instruction.
.
fXIN
/8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024
3
BTCL Clear
To Watchdog Timer
8 MUX
0 BITR (8BIT) 1 BITIF
Basic Interval Timer Interrupt
Internal RC OSC
Figure 11-1 Block Diagram of Basic Interval Timer
Clock Control Register CKCTLR WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available
Basic Interval Timer Clock Selection Symbol WAKEUP RCWDT WDTON BTCL Function Description 1 : Enables Wake-up Timer 0 : Disables Wake-up Timer 1 : Enables Internal RC Watchdog Timer 0 : Disables Internal RC Watchdog Time 1 : Enables Watchdog Timer 0 : Operates as a 7-bit Timer 1 : BITR is cleared and BTCL becomes "0" automatically after one machine cycle, and BITR continue to count-up 000 : fXIN / 8 001 : fXIN / 16 010 : fXIN / 32 011 : fXIN / 64 100 : fXIN / 128 101 : fXIN / 256 110 : fXIN / 512 111 : fXIN / 1024
Figure 11-2 CKCTLR: Clock Control Register
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12. TIMER / COUNTER
The HMS87C1X0XA has two Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either two 8-bit Timer/ Counter or the one 16-bit Timer/Counter by combining them. In the "timer" function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source (1/1 to 1/8). In the "counter" function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0(Timer 0).
Note: If changing the Timer value or starting again, it
should be stop the timer clock firstly, and then set Timer register value.
Ex) LDM LDM LDM TM0,#00001100B TDR,#7FH TM0,#00010111B
In addition the "capture" function, the register is increased in response external interrupt same with timer function. When external interrupt edge input, the count register is captured into capture data register CDRx. Timer1 is shared with "PWM" function and "Compare output" function It has seven operating modes: "8-bit timer/counter", "16bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer mode register TMx as shown in Figure 12-1 and Table 12-1.
Timer 0 Mode Register TM0 CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST ADDRESS : D0H RESET VALUE : --000000
CAP0
Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture Input clock selection 000 : fXIN / 2, 100 : fXIN / 128 001 : fXIN / 4, 010 : fXIN / 8, 110 : fXIN / 2048 101 : fXIN / 512
T0CN
Continue control bit 0 : Stop counting 1 : Start counting continuously Start control bit 0 : Stop counting 1 : Start counting
T0CK[2:0]
T0ST
011 : fXIN / 32, 111 : External Event ( EC0 ) Timer 1 Mode Register TM1 POL 16BIT PWM0E CAP1 T1CK1 T1CK0 T1CN T1ST ADDRESS : D2H RESET VALUE : 00000000
POL
PWM Output Polarity 0 : Duty active low 1 : Duty active high 16-bit mode selection 0 : 8-bit mode 1 : 16-bit mode PWM enable bit 0 : Disables PWM 1 : Enables PWM Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture
T1CK[2:0]
Input clock selection 00 : fXIN 10 : fXIN / 8 01 : fXIN / 2 11 : using the Timer 0 clock
16BIT
T1CN
Continue control bit 0 : Stop counting 1 : Start counting continuously Start control bit 0 : Stop counting 1 : Start counting
PWM0E
T1ST
CAP1
Figure 12-1 Timer Mode Register (TM0, TM1)
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16BIT 0 0 0 0 1 1 1 1
CAP0 0 0 1 X1 0 0 1 0
CAP1 0 1 0 0 0 0 X 0
PWME 0 0 0 1 0 0 0 0
T0CK[2:0] XXX 111 XXX XXX XXX 111 XXX XXX
T1CK[1:0] XX XX XX XX 11 11 11 11
PWMO 0 0 1 1 0 0 0 1
TIMER 0 8-bit Timer 8-bit Event Counter 8-bit Capture 8-bit Timer/Counter 16-bit Timer 16-bit Event Counter 16-bit Capture 16-bit Compare output
TIMER1 8-bit Timer 8-bit Capture 8-bit Compare output 10-bit PWM
Table 12-1 Operating Modes of Timer 0 and Timer 1
1. X: The value "0" or "1" corresponding your operation.
12.1 8-bit Timer/Counter Mode
The HMS87C1X0XA has four 8-bit Timer/Counters, Timer 0 and Timer 1 as shown in Figure 12-2. The "timer" or "counter" function is selected by mode registers TMx as shown in Figure 12-1 and Table 12-1. To use as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits 16BIT of TM1 should be cleared to "0"(Table 12-1).
TM0
-
16BIT 0
CAP0 0 PWME 0 T0CK[2:0]
T0CK2 X CAP1 0
T0CK1 X T1CK1 X
T0CK0 X T1CK0 X
T0CN X T1CN X
T0ST X T1ST X
ADDRESS : D0H RESET VALUE : --000000
TM1
POL X
ADDRESS : D2H RESET VALUE : 00000000
X: The value "0" or "1" corresponding your operation.
T0ST 0 : Stop 1 : Start
1
Edge Detector
EC0
fXIN
/2 /4 /8 / 32 / 128 / 512 / 2048 /1 /2 /8
MUX
T0 (8-bit)
CLEAR
T0IF T0CN TDR0 (8-bit) T1CK[1:0] T1ST 0 : Stop 1 : Start
1
TIMER 0 INTERRUPT
COMPARATOR
COMP0 PIN CLEAR F/F
MUX
T1 (8-bit)
T1IF T1CN TDR1 (8-bit) COMPARATOR
TIMER 1 INTERRUPT
Figure 12-2 8-bit Timer / Counter Mode
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These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by control bits T0CK2, T0CK1 and T0CK0 of register TM0) and 1, 2, 8 (selected by control bits T1CK1 and T1CK0 of register TM1). In the Timer 0, timer register T0 increases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt
(latched in T0F bit). As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx. In counter function, the counter is increased every 0-to 1 (rising edge) transition of EC0 pin. In order to use counter function, the bit RA0 of the RA Direction Register RAIO is set to "0". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not.
TDR1
n n-1
nt
9 8 7 6
PCP
~ ~
~ ~
up
3 2 1 0 Interrupt period = PCP x (n+1) Occur interrupt Occur interrupt Occur interrupt
-c ou
~ ~
5 4
TIME
Timer 1 (T1IF) Interrupt
Figure 12-3 Counting Example of Timer Data Registers
TDR1
disable enable
clear & start stop
up
-c o
un
t
~ ~
~ ~
TIME Timer 1 (T1IF) Interrupt
Occur interrupt Occur interrupt
T1ST Start & Stop
T1ST = 0
T1ST = 1
T1CN Control count
T1CN = 0 T1CN = 1
Figure 12-4 Timer Count Operation
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12.2 16-bit Timer/Counter Mode
The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000H until it matches TDR0, TDR1 and then resets to 0000 H . The match output generates Timer 0 interrupt not Timer 1 interrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0SL0. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively.
TM0
-
16BIT 1
CAP0 0 PWME 0
T0CK2 X CAP1 0
T0CK1 X T1CK1 1
T0CK0 X T1CK0 1
T0CN X T1CN X
T0ST X T1ST X
ADDRESS : D0H RESET VALUE : --000000
TM1
POL X
ADDRESS : D2H RESET VALUE : 00000000
X: The value "0" or "1" corresponding your operation.
T0CK[2:0] Edge Detector T0ST 0 : Stop 1 : Start
1
EC0
fXIN
/2 /4 /8 / 32 / 128 / 512 / 2048
MUX
T1 (8-bit)
T0 (8-bit)
CLEAR
T0CN COMPARATOR
T0IF
TIMER 0 INTERRUPT
F/F TDR1 (8-bit) TDR0 (8-bit) COMP0 PIN
Figure 12-5 16-bit Timer / Counter Mode
12.3 8-bit Compare Output (16-bit)
The HMS87C1X0XA has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(COMP0) as shown in Figure 12-2 and Figure 12-5. Thus, pulse out is generated by the timer match. These operation is implemented to pin, RB4/COMP0/PWM. This pin output the signal having a 50: 50 duty square wave, and output frequency is same as below equation.
Oscillation Frequency fCOMP = ------------------------------------------------------------------------------2 x Prescaler Value x ( TDR + 1 )
In this mode, the bit PWMO of RB function register (RBFUNC) should be set to "1", and the bit PWME of timer1 mode register (TM1) should be set to "0". In addition, 16-bit Compare output mode is available, also.
12.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 12-6. As mentioned above, not only Timer 0 but Timer 1 can also be used as a capture mode. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when timer register T0 (T1) increases and matches TDR0 (TDR1).
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This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 12-8, the pulse width of captured signal is wider than the timer data value (FFH) over 2 times. When external interrupt is occurred, the captured value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be captured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt.
Note: The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation.
TM0
-
16BIT 0
CAP0 1 PWME 0 T0CK[2:0]
T0CK2 X CAP1 1
T0CK1 X T1CK1 X
T0CK0 X T1CK0 X
T0CN X T1CN X T0ST
T0ST X T1ST X
ADDRESS : D0H RESET VALUE : --000000
TM1
POL X
ADDRESS : D2H RESET VALUE : 00000000
Edge Detector
0 : Stop 1 : Start
1
EC0
fXIN
/2 /4 /8 / 32 / 128 / 512
MUX
T0 (8-bit)
CLEAR
T0IF T0CN CAPTURE CDR0 (8-bit) COMPARATOR TDR0 (8-bit)
TIMER 0 INTERRUPT
/ 2048
INT0IF INT0 IEDS[1:0] T0ST 0 : Stop 1 : Start CLEAR INT 0 INTERRUPT
/1 /2 /8
1
MUX
T1 (8-bit)
T1IF T1CK[1:0] T1CN IEDS[3:2] CAPTURE INT1IF INT1 INT 1 INTERRUPT CDR1 (8-bit) COMPARATOR TDR1 (8-bit)
TIMER 1 INTERRUPT
Figure 12-6 8-bit Capture Mode
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T0
nt
n n-1
This value is loaded to CDR0
~ ~
~ ~
9 8 7 6
up -c
3 2 1 0
ou
5 4
~ ~
TIME
Ext. INT0 Pin
Interrupt Request (INT0F) Interrupt Interval Period
Ext. INT0 Pin
Interrupt Request (INT0F) Capture (Timer Stop)
Delay Clear & Start
Figure 12-7 Input Capture Operation
Ext. INT0 Pin
Interrupt Request (INT0F) Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H Interrupt Request (T0F) FFH T0 13H 00H 00H FFH
Figure 12-8 Excess Timer Overflow in Capture Mode
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12.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0.
ADDRESS : D0H RESET VALUE : --000000
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively.
TM0
-
16BIT 1
CAP0 1 PWME 0
T0CK2 X CAP1 X
T0CK1 X T1CK1 1
T0CK0 X T1CK0 1
T0CN X T1CN X
T0ST X T1ST X
TM1
POL X
ADDRESS : D2H RESET VALUE : 00000000
X: The value "0" or "1" corresponding your operation.
T0CK[2:0] Edge Detector T0ST 0 : Stop 1 : Start
1
EC0
fXIN
/2 /4 /8 / 32 / 128 / 512 / 2048
MUX T0CN
T0 + T1 (16-bit)
CLEAR
T0IF COMPARATOR
TIMER 0 INTERRUPT
CAPTURE
CDR1 (8-bit)
CDR0 (8-bit)
TDR1 (8-bit)
TDR0 (8-bit) INT0IF INT 0 INTERRUPT
INT0 IEDS[1:0]
Figure 12-9 16-bit Capture Mode
12.6 PWM Mode
The HMS87C1X0XA has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1. In PWM mode, pin RB4/COMP0/PWM0 outputs up to a 10-bit resolution PWM output. This pin should be configure as a PWM output by setting "1" bit PWM0O in RBFUNC register. The period of the PWM output is determined by the T1PPR (PWM0 Period Register) and PWM0HR[3:2] (bit3,2 of PWM0 High Register) and the duty of the PWM output is determined by the T1PDR (PWM0 Duty Register) and PWM0HR[1:0] (bit1,0 of PWM0 High Register). The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM0HR[3:2]. And writes duty value to the T1PDR and the PWM0HR[1:0] same way. The T1PDR is configure as a double buffering for glitchless PWM output. In Figure 12-10, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle)
PWM Period = [PWM0HR[3:2]T1PPR] X Source Clock PWM Duty = [PWM0HR[1:0]T1PDR] X Source Clock
The relation of frequency and resolution is in inverse proportion. Table 12-2 shows the relation of PWM frequency vs. resolution.
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If it needed more higher frequency of PWM, it should be reduced resolution.
Frequency Resolution 10-bit 9-bit 8-bit 7-bit T1CK[1:0] = 00(125nS) 7.8KHz 15.6KHz 31.2KHz 62.5KHz T1CK[1:0] = 01(250nS) 3.9KHz 7.8KHz 15.6KHz 31.2KHz T1CK[1:0] = 10(1uS) 0.98KHZ 1.95KHz 3.90KHz 7.81KHz
It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 12-12. As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value.
Note: If changing the Timer1 to PWM function, it
Table 12-2 PWM Frequency vs. Resolution at 8MHz
should be stop the timer clock firstly, and then set period and duty register value. If user writes register values while timer is in operation, these register could be set with certain values.
Ex) LDM LDM LDM LDM LDM LDM TM1,#00H T1PPR,#00H T1PDR,#00H PWM0HR,#00H RBFUNC,#0001_1100B TM1,#1010_1011B
The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High).
TM1
POL X
16BIT 0 -
PW ME 1 -
C A P1 0 -
T1CK1 X
T1CK0 X
T 1C N X
T 1S T X
ADDRESS : D2H RESET VALUE : 00000000
PWM0HR
-
PW M 0HR3 PW M0HR2 PW M0HR1 PW M0HR0 X Period High X X Duty High X
ADDRESS : D5H RESET VALUE : ----0000 Bit Manipulation Not Available
PWM0HR[3:2] T1ST T0 clock source 0 : Stop 1 : Clear and Start T1PPR(8-bit)
X: The value "0" or "1" corresponding your operation.
COMPARATOR SQ RB4/ PWM0
1
CLEAR T1 (8-bit)
fXIN
/1 /2 /8
MUX
R PWM0O [RBFUNC.4] POL
COMPARATOR T1CK[1:0] T1CN Slave T1PDR(8-bit)
PWM0HR[1:0] Master
T1PDR(8-bit)
Figure 12-10 PWM Mode
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~ ~
~ ~
fXIN
~~ ~~
~~~ ~~~
T1 PWM POL=1 PWM POL=0
00 01
02
03
04
05
7F
80
81
3FF
00 01
02
03
Duty Cycle [80H x 125nS = 16uS] Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz] T1CK[1:0] = 00 (fXIN) PWM0HR = 0CH T1PPR = FFH T1PDR = 80H
Duty PWM0HR1 PWM0HR0 0 0 T1PDR (8-bit) 80H
~ ~
Period
PWM0HR3 PWM0HR2 1 1
T1PPR (8-bit) FFH
Figure 12-11 Example of PWM at 8MHz
T 1 C K [1:0 ] = 10 (1 uS ) P W M 0 H R = 0 0H T1PPR = 0EH T 1 P D R = 0 5H Source clock T1 PWM POL=1 Duty Cycle [05H x 1uS = 5uS] Period Cycle [0EH x 1uS = 14uS, 71KHz] Duty Cycle [05H x 1uS = 5uS] Duty Cycle [05H x 1uS = 5uS]
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 04 05
Write T1PPR to 0AH
~ ~
Period changed Period Cycle [0AH x 1uS = 10uS, 100KHz]
Figure 12-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz)
~ ~
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13. BUZZER OUTPUT FUNCTION
The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz at fXIN = 4 MHz) by user programmable counter. Pin RB1 is assigned for output port of Buzzer driver by setting the bit BUZO of RBFUNC to "1". The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increased from 00H until it matches 6-bit register BUR. Also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%. The bit 0 to 5 of BUR determines output frequency for buzzer driving. Frequency calculation is following as shown below.
Oscillator Frequency f BUZ ( Hz ) = ----------------------------------------------------------------------------2 x Prescaler Ratio x ( BUR + 1 )
The bits BUCK1, BUCK0 of BUR selects the source clock from prescaler output.
BUR
BUCK1
BUCK0
BUR5
BUR4
BUR3
BUR2
BUR1
BUR0
ADDRESS : DEH RESET VALUE : 11111111 Bit Manipulation Not Available
Input clock selection 00 : fXIN / 8 01 : fXIN / 16
Buzzer Period Data
10 : fXIN / 32 11 : fXIN / 64
fXIN
/8 / 16 / 32 / 64
MUX
COUNTER (6-bit)
F/F BUCK[1:0] BUR (6-bit) COMPARATOR RB1/BUZ PIN BUZO [RBFUNC.1]
Figure 13-1 Buzzer Driver
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14. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is selected to VDD or AVREF by setting of the bit AVREFS in RBFUNC register. If external analog reference AVREF is selected, the bit ANSEL0 should not be set to "1", because this pin is used to an analog reference of A/D converter. The A/D module has two registers which are the control register ADCM and A/D result register ADCR. The ADCM register, shown in Figure 14-2, controls the operation of the A/D converter module. The port pins can be configure as analog inputs or digital I/O.
ADS[2:0]
To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in RAFUNC register. And selected the corresponding channel to be converted by setting ADS[2:0]. The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 14-1. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 10 uS (at fXIN=8 MHz).
111 RA7/AN7 ANSEL7 110 RA6/AN6 A/D Result Register ANSEL6 101 RA5/AN5 ANSEL5 100 RA4/AN4 ANSEL4 011 RA3/AN3 ANSEL3 010 RA2/AN2 ANSEL2 001 RA1/AN1 ANSEL1 RB0/AN0/AVREF ANSEL0 (RAFUNC.0) 000 Resistor Ladder Circuit Sample & Hold S/H Successive Approximation Circuit ADCR(8-bit) ADDRESS : EBH RESET VALUE : Undefined
A D IF
A/D Interrupt
1 VDD Pin 0 ADEN AVREFS (RBFUNC.0)
Figure 14-1 A/D Converter Block Diagram
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A/D Control Register ADCM Reserved Analog Channel Select 000 : Channel 0 (RB0/AN0) 001 : Channel 1 (RA1/AN1) 010 : Channel 2 (RA2/AN2) 011 : Channel 3 (RA3/AN3) 100 : Channel 4 (RA4/AN4) 101 : Channel 5 (RA5/AN5) 110 : Channel 6 (RA6/AN6) 111 : Channel 7 (RA7/AN7) A/D Enable bit 1 : A/D Conversion is enable 0 : A/D Converter module shut off and consumes no operation current A/D Result Data Register ADCR ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 ADDRESS : EBH RESET VALUE : Undefined A/D Status bit 0 : A/D Conversion is in process 1 : A/D Conversion is completed A/D Start bit 1 : A/D Conversion is started After 1 cycle, cleared to "0" 0 : Bit force to zero ADEN ADS2 ADS1 ADS0 ADST ADSF ADDRESS : EAH RESET VALUE : --000001
Figure 14-2 A/D Converter Registers
A/D Converter Cautions
ENABLE A/D CONVERTER
(1) Input range of AN0 to AN7 The input voltage of AN0 to AN7 should be within the specification range. In particular, if a voltage above VDD
A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT
(or AVREF) or below VSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected.
(2) Noise countermeasures
A/D START (ADST = 1)
In order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF (or VDD) and AN0 to AN7. Since the effect
increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be conNOP
nected externally as shown in Figure 14-4 in order to reduce noise.
ADSF = 1 NO YES
Analog Input 100~1000pF
AN0~AN7
READ ADCR
Figure 14-3 A/D Converter Operation Flow
Figure 14-4 Analog Input Pin Connecting Capacitor
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(3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7 The analog input pins AN0 to AN7 also function as input/ output port (PORT RA and RB0) pins. When A/D conversion is performed with any of pins AN0 to AN7 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling
noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
(4) AVREF pin input impedance A series resistor string of approximately 10K is connected between the AVREF pin and the VSS pin.
Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the
series resistor string between the AVREF pin and the VSS pin, and there will be a large reference voltage error.
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15. INTERRUPTS
The HMS87C1X0XA interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Interrupt Edge Selection Register (IEDS), priority circuit and Master enable flag("I" flag of PSW). The configuration of interrupt circuit is shown in Figure 15-1and Interrupt priority is shown in Table 15-1. The External Interrupts INT0 and INT1 can each be transition-activated (1-to-0, 0-to-1 and both transition). The flags that actually generate these interrupts are bit INT0IF and INT1IF in Register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 and Timer 1 Interrupts are generated by T0IF and T1IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The Watch dog timer Interrupt is generated by WDTIF which set by a match in Watch dog timer register (when the bit WDTON is set to "0"). The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflowing of the Basic Interval Timer Register(BITR).
Internal bus line
I-flag is in PSW, it is cleared by "DI", set by "EI" instruction.When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware. Interrupt Enable Register (Higher byte)
IRQH External Int. 0
IEDS INT0IF INT1IF
IENH 7 6
Release STOP
External Int. 1 Timer 0 Timer 1
To CPU Priority Control I Flag Interrupt Master Enable Flag Interrupt Vector Address Generator
T0IF T1IF
5 4
A/D Converter WDT BIT
ADIF WDTIF BITIF
7 6 5
IRQL
IENL
Interrupt Enable Register (Lower byte)
Internal bus line
Figure 15-1 Block Diagram of Interrupt Function
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The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 15-2. These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
Reset/Interrupt Hardware Reset External Interrupt 0 External Interrupt 1 Timer 0 Timer 1 A/D Converter Watch Dog Timer Basic Interval Timer
Symbol RESET INT0 INT1 Timer 0 Timer 1 A/D C WDT BIT
Priority 1 2 3 4 5 6 7
Vector Addr. FFFEH FFFAH FFF8H FFF6H FFF4H FFEAH FFE8H FFE6H
Table 15-1 Interrupt Priority
Interrupt Enable Register High IENH INT0E INT1E T0E T1E ADDRESS : E2H RESET VALUE : 0000----
Interrupt Enable Register Low IENL ADE WDTE BITE ADDRESS : E3H RESET VALUE : 000-----
Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled. 0 : Disable 1 : Enable Interrupt Request Register High IRQH INT0IF INT1IF T0IF T1IF ADDRESS : E4H RESET VALUE : 0000----
Interrupt Request Register Low IRQL ADIF WDTIF BITIF ADDRESS : E5H RESET VALUE : 000-----
Shows the interrupt occurrence 0 : Not occurred 1 : Interrupt request is occurred
Figure 15-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and disable any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by software before re-enabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and written.
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15.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 fOSC (2 s at fXIN=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed.
System clock
Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 15-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer Vector Table Address
Entry Address
When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers.
0FFE6H 0FFE7H
012H 0F3H
0F312H 0F313H
0EH 2FH
Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program.
A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced.
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The following method is used to save/restore the generalpurpose registers. Example: Register save using push and pop instructions
INTxx: PUSH PUSH PUSH A X Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.
Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
interrupt processing
POP POP POP RETI
Y X A
;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN
General purpose register save/restore using push and pop instructions;
main task acceptance of interrupt interrupt service task saving registers
Main Program service
TIMER 1 service INT0 service
enable INT0 disable other EI
Occur TIMER1 interrupt restoring registers interrupt return
Occur INT0
enable INT0 enable other
BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 15-4.
In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
Figure 15-5 Execution of Multi Interrupt
Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend.
TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI A X Y IENH,#80H IENL,#0
B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE RETI
=0
;Enable INT0 only ;Disable other ;Enable Interrupt
TCALL0 ROUTINE
RET
Figure 15-4 Execution of BRK/TCALL0
IENH,#0F0H ;Enable all interrupts IENL,#0E0H Y X A
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15.2 External Interrupt
The external interrupt on INT0 and INT1 pins are edge triggered depending on the edge selection register IEDS (address 0E6H) as shown in Figure 15-6. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge.
Ext. Interrupt Edge Selection Register W WW W IEDS ADDRESS : 0E6H RESET VALUE : ----0000 W W W W
INT0 pin
INT0IF
INT0 INTERRUPT
INT1 edge select 00 : Int. disable 01 : falling 10 : rising 11 : both
INT0 edge select 00 : Int. disable 01 : falling 10 : rising 11 : both
edge selection
INT1 pin
INT1IF
INT1 INTERRUPT
LDM RBIO,#1111_1011B ; ;**** Set port as an interrupt port LDM RBFUNC,#04H ; ;**** Set Falling-edge Detection LDM IEDS,#0000_0001B :
IEDS [0E6H]
Response Time The INT0 and INT1 edge are latched into INT0IF and INT1IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 15-7 shows interrupt response timings.
Figure 15-6 External Interrupt Block Diagram
Example: To use as an INT0 and INT1
: : ;**** Set port as an input port RB2
max. 12 fOSC
8 fOSC
Interrupt Interrupt goes latched active
Interrupt processing
Interrupt routine
Figure 15-7 Interrupt Response Timing Diagram
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16. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or other causes and return the operation to the normal condition. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external oscillator of the Xin pin. But the internal RC oscillated clock source should be activated by execution of STOP instruction. It means that the watchdog timer can not run even if the clock on the Xin pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. The source clock of WDT is overflow of Basic Interval Timer. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or CPU reset signal in accordance with the bit WDTON .
Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer and setting the Watchdog Timer Register, maximum error of timer is depend on prescaler ratio of Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT of CKCTLR and executing the STOP instruction as shown below.
: LDM LDM STOP NOP NOP : CKCTLR,#3FH WDTR,#0FFH ; enable the RC-osc WDT ; set the WDT period ; enter the STOP mode ; RC-osc WDT running
The RC oscillation period is variable according to the temperature, VDD and process variations from part to part (approximately, 120~180uS at 5V). The following equation shows the RC oscillated watchdog timer time-out. T R C W D T = C LK R C x28x[W D T R .6~ 0 ]+ (C L K R C x28)/2 w h ere, C L K R C = 1 20~ 1 80u S In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. TWDT = [WDTR.6~0] x Interval of BIT
Clock Control Register CKCTLR WAKEUP RCWDT 0 X WDTON 1 BTCL X BTS2 X BTS1 X BTS0 X ADDRESS : EDH RESET VALUE : 01111111 Bit Manipulation Not Available ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available
Watchdog Timer Register WDTR WAKEUP RCWDT STOP BTS[2:0] WDTCL
7-bit Watchdog Counter Register
fXIN
/8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024
WDTR (8-bit) 3
BTCL Clear
WDTCL
WDTON
8 MUX
0 BITR (8-bit) 1 7-bit Counter OFD
1
CPU RESET
0 Overflow Detection Watchdog Timer Interrupt Request
Internal RC OSC
BITIF
Basic Interval Timer Interrupt
Figure 16-1 Block Diagram of Watchdog Timer
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17. POWER SAVING MODE
For applications where power consumption is a critical factor, device provides three kinds of power saving functions, STOP mode, Wake-up Timer mode and internal RCoscillated watchdog timer mode. The power saving function is activated by execution of STOP instruction after setting the corresponding bit (WAKEUP, RCWDT) of CKCTLR. Table 17-1 shows the status of each Power Saving Mode
Peripheral RAM Control Registers I/O Ports CPU Timer0 Oscillation Prescaler Internal RC oscillator Entering Condition CKCTLR[6,5] Power Saving Release Source STOP Retain Retain Retain Stop Stop Stop Stop Stop 00 RESET, INT0, INT1 Wake-up Timer Retain Retain Retain Stop Operation Oscillation / 2048 only Stop 1X RESET, INT0, INT1, Timer0 Internal RC-WDT Retain Retain Retain Stop Stop Stop Stop Oscillation 01 RESET, INT0, INT1, RC-WDT
Note: Before executing STOP instruction, clear all interrupt request flag. Because if the interrupt request flag is set before STOP instruction, the MCU runs as if it doesn't perform STOP instruction, even though the STOP instruction is completed. So insert two lines to clear all interrupt request flags (IRQH, IRQL) before STOP instruction as shown each example.
Table 17-1 Power Saving Mode
17.1 Stop Mode
In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up. * The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held. * The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode. The Stop mode is activated by execution of STOP instruction after setting the bit WAKEUP and RCWDT of CKCTLR to "00". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize.
Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM CKCTLR,#0000_1110B LDM IRQH,#0 LDM IRQL,#0 STOP NOP NOP
In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current
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flows when the input level is stable at the power voltage level (VDD/VSS), however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. Release the STOP mode The exit from STOP mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. After releasing STOP mode, instruction execution is divided into two ways by I-flag(bit2 of PSW). If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. (refer to Figure 17-1) When exit from Stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. Figure 17-2 shows the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 17-3. Minimizing Current Consumption in Stop Mode The Stop mode is designed to reduce power consumption. To minimize the current consumption during Stop mode,
the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Weak pull-ups on port pins should be turned off, if possible. All inputs should be either as VSS or at VDD (or as close to rail as possible). An intermediate voltage on an input pin causes the input buffer to draw a significant amount of current.
STOP INSTRUCTION STOP Mode
Interrupt Request =0
Corresponding Interrupt Enable Bit (IENH, IENL)
IEXX =1
STOP Mode Release
Master Interrupt Enable Bit PSW[2]
I-FLAG =1
=0
Interrupt Service Routine
Next INSTRUCTION
Figure 17-1 STOP Releasing Flow by Interrupts
~ ~
Oscillator (XIN pin) Internal Clock External Interrupt
~ ~
STOP Instruction Execution
~~ ~~ ~ ~
Clear Basic Interval Timer
~ ~ ~ ~ ~ ~
BIT Counter
N-2
N-1
N
N+1
N+2
00
01
FE
FF
00
01
~ ~
Normal Operation
STOP Mode
Stabilization Time tST > 20mS
Normal Operation
Figure 17-2 Timing of STOP Mode Release by External Interrupt
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STOP Mode
~ ~
Oscillator (XIN pin) Internal Clock RESET Internal RESET
~ ~
STOP Instruction Execution Time can not be controlled by software
Figure 17-3 Timing of STOP Mode Release by RESET
~~ ~~ ~ ~ ~ ~
Stabilization Time tST = 64mS @4MHz
~~ ~~ ~ ~
17.2 Wake-up Timer Mode
In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler (only 2048 divided ratio) and Timer0, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to "1". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation)
Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM TDR0,#0FFH LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B LDM IRQH,#0 LDM IRQL,#0 STOP NOP NOP
In addition, the clock source of timer0 should be selected to 2048 divided ratio. Otherwise, the wake-up function can not work. And the timer0 can be operated as 16-bit timer with timer1 (refer to timer function). The period of wake-up function is varied by setting the timer data register 0, TDR0. Release the Wake-up Timer mode The exit from Wake-up Timer mode is hardware reset, Timer0 overflow or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts and Timer0 overflow allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine (refer to Figure 17-1). When exit from Wake-up Timer mode by external interrupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 17-4.
~ ~
Oscillator (XIN pin) CPU Clock Interrupt Request
STOP Instruction Execution
~~ ~~ ~ ~
Normal Operation
Wake-up Timer Mode (stop the CPU clock)
Normal Operation Do not need Stabilization Time
Figure 17-4 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt
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17.3 Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP and RCWDT of CKCTLR to "01". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation)
Note: After STOP instruction, at least two or more NOP instruction should be written
Ex) LDM LDM LDM LDM STOP NOP NOP WDTR,#1111_1111B CKCTLR,#0010_1110B IRQH,#0 IRQL,#0
chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine.(Figure 17-5) However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal RESET signal and execute the reset processing. (Figure 17-6) If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine (refer to Figure 17-1). When exit from Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required for normal operation. Figure 17-5 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 17-6.
Release the Internal RC-Oscillated Watchdog Timer mode The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-
~ ~
Oscillator (XIN pin) Internal RC Clock
~ ~
~ ~ ~ ~
Internal Clock External Interrupt (or WDT Interrupt)
~ ~
STOP Instruction Execution
~ ~
Clear Basic Interval Timer
~ ~ ~ ~
BIT Counter
N-2
N-1
N
N+1
N+2
00
01
FE
FF
00
00
~ ~
Normal Operation
RCWDT Mode
Stabilization Time tST > 20mS
Normal Operation
Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt
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RCWDT Mode
~ ~
Oscillator (XIN pin) Internal RC Clock
~ ~
~ ~ ~ ~
Internal Clock RESET RESET by WDT Internal RESET
~ ~
STOP Instruction Execution Time can not be controlled by software
Figure 17-6 Internal RCWDT Mode Releasing by RESET
~ ~ ~ ~
Stabilization Time tST = 64mS @4MHz
~ ~ ~ ~
17.4 Minimizing Current Consumption
The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical.
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means.
It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if uncertain voltage level (not VSS or VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low.
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VDD INPUT PIN internal pull-up OPEN INPUT PIN VDD VDD i=0
VDD
O
O
i GND VDD
i
Very weak current flows
X
Weak pull-up current flows
X
OPEN
i=0
GND
O
O
When port is configure as an input, input level should be closed to 0V or 5V to avoid power consumption.
Figure 17-7 Application Example of Unused Input Port
OUTPUT PIN ON OPEN ON OFF i GND VDD ON OFF OFF
OUTPUT PIN VDD L ON OFF i GND ON i=0 GND L VDD
O
OFF
X
X O
O
In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port.
In the left case, much current flows from port to GND.
Figure 17-8 Application Example of Unused Output Port
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18. RESET
The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 18-1. Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. Initial state of each register is shown as Table 8-1.
1
2
3
4
5
6
7
~ ~
Oscillator (XIN pin) RESET
~ ~ ~ ~
ADDRESS BUS DATA BUS
?
?
?
?
FFFE FFFF Start
~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilizing Time tST = 64mS at 4MHz
Figure 18-1 Timing Diagram after RESET
~ ~
MAIN PROGRAM RESET Process Step
* Power-On Reset (POR) The HMS87C130XA incorporates on-chip Power-On Reset (POR) circuitry which provides an internal chip reset for most power-up situations. To use this feature, the user merely ties the RESET pin to VDD and setting the POREN bit of CONFIG register ( refer to Figure 20-1). A Power-on Reset pulse is generated on-chip when VDD rise is detected approximately 1V. To take an advantage of the Power-on Reset, just tie the RESET pin directly ( or through the resistor ) to VDD.
VDD RESET
Basic Interval Timer Start
INTERNAL RESET
Figure 18-2 Time-out Sequence On Power-up (RESET Tied To VDD): Fast VDD Rise Time
A power-up example where RESET is not tied to VDD is shown in Figure 18-2. VDD is allowed to rise and stabilize before bringing RESET high. The chip will actually come out of reset and start the Basic Interval Timer after RESET goes high.
In Figure 18-3, the on-chip Power-On Reset feature is being used (RESET and VDD are tied together). The VDD is stable before the Basic interval timer times out and there is no problem in getting a proper reset. However, Figure 184 depicts a problem situation where VDD rises too slowly.
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The time between when the Basic interval timer senses a high on the RESET pin, and when the RESET pin (and VDD) actually reach their full value, is too long. In this situation, when the Basic interval timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external R circuits be used to achieve longer POR delay times ( Figure 18-5). The POR circuit
does not produce an internal reset when VDD declines
Note: When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met..
VDD RESET INTERNAL POR
Basic Interval Timer Start
INTERNAL RESET
Figure 18-3 Time-out Sequence On Power-up (RESET Tied To VDD): Fast VDD Rise Time
VDD RESET INTERNAL POR
INTERNAL RESET
Basic Interval Timer Start
Figure 18-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIED TO VDD): SLOW VDD RISE TIME
VDD VDD - External Power-On Reset circuit is required only if VDD power-up is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. R R1 RESET - R < 40 k is recommended to make sure that voltage drop across R does not violate the device electrical specification. - R1 = 100 to 1k will limit any current flowing into RESET from external capacitor C in the event of RESET pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
D
C
Figure 18-5 EXTERNAL POWERON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
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19. POWER FAIL PROCESSOR
The HMS87C1X0XA has an on-chip power fail detection circuitry to immunize against power noise. A Power Fail Detector Register, PFDR can enable (if clear/programmed) or disable (if set) the Power fail Detect circuitry. If VDD falls below 2.4~2.6V(or 1.6~1.8V) range for longer than 50 nS, the Power fail situation may reset MCU or halt the system clock according to PFS bit of PFDR. And power fail detect level is selectable by programming the bit PFDLEVEL of CONFIG register when program the OTP. As below PFDR register is not implemented on the in-circuit emulator, user can not experiment with it. Therefore, after final development of user program, this function may be experimented.
Note: Power fail detect level is decided by setting the bit PFDLEVEL of CONFIG register (refer to Figure 201.
PFDIS
PFDOPR
PFDM
Power Noise
Power Fail Detection Circuit PFS
to RESET circuit
System clock freeze
Power Fail Detector Register PFDR Reserved PFDOPR PFDIS PFDM PFS ADDRESS : EFH RESET VALUE : ----0100
Power Fail Status 0 : Normal Operate 1 : This bit force to "1" when Power fail was detected Operation Mode 0 : System Clock Freeze during power fail 1 : MCU will be reset during power fail Disable Flag 0 : Power fail detection enable 1 : Power fail detection disable PFD Operation Disable Flag 0 : Power fail detection enable 1 : Power fail detection disable But can read PFS
Figure 19-1 Power Fail Detector
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RESET VECTOR
PFS =1 NO RAM CLEAR INITIALIZE RAM DATA
YES
Skip the initial routine
INITIALIZE ALL PORTS INITIALIZE REGISTERS
FUNTION EXECUTION
Figure 19-2 Example S/W of RESET by Power fail
VDD 64mS
PFVDDMAX PFVDDMIN
Internal RESET VDD When PFDM = 1 Internal RESET VDD t < 64mS
64mS
PFVDDMAX PFVDDMIN
PFVDDMAX PFVDDMIN 64mS
Internal RESET
VDD
PFVDDMAX PFVDDMIN
System Clock When PFDM = 0 VDD PFVDDMAX PFVDDMIN
System Clock
Figure 19-3 Power Fail Processor Situations
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20. OTP PROGRAMMING
The HMS87C130XA is one-time PROM(OTP) microcontroller with 4K/2K bytes electrically programmable read only memory. To programming the OTP device, user must use the universal programmer which is support Hynix microcontrollers.
20.1 DEVICE CONFIGURATION AREA
The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as security bit, power on reset, RC-oscillation, PFD level select and open drain port selection . This area is not accessible during normal execution but is readable and writable during program / verify.
Configuration Register CONFIG POREN OPDR1 OPDR0 LOCK PFD LEVEL RC_OPT ADDRESS : 707FH
RC Otion 0 : Normal Oscillator 1 : External RC Oscillator PFD Level Select 0 : PFD Level High (2.4~2.6V) 1 : PFD Level Low (1.6~1.8V) SECURITY BIT 0 : Allow Code Read Out 1 : Prohibit Code Read Out Open Drain Port Selection 00 : Normal Port 01 : Open Drain RA0 10 : Open Drain RA0/RB2 11 : Open Drain RA0/RB2/RB3/RC0 Power on RESET 0 : Power on RESET Disable 1 : Power on RESET Enable
Figure 20-1 Device Configuration Area
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A_D4 A_D5 A_D6 A_D7 VDD CTL0 CTL1 CTL2
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13 NC
A_D3 A_D2 A_D1 A_D0
VSS VPP
EPROM Enable
Figure 20-2 Pin Assignment ( HMS1304/2A )
User Mode Pin No. Pin Name
1 2 3 4 5 6 7 8 9~14 15 16 17 18 19,20 21 22 23 24 RA4 (AN4) RA5 (AN5) RA6 (AN6) RA7 (AN7) VDD RD0 RD1 RBB0/AN0/AVref RB1~4, RD2~3 XIN XOUT RESET VSS RC0, 1 RA0 (EC0) RA1 (AN1) RA2 (AN2) RA3 (AN3)
EPROM MODE Pin Name
A_D4 A_D5 A_D6 A_D7 VDD CTL0 CTL1 CTL2 VDD EPROM Enable NC VPP VSS VDD A_D0 A_D1 A_D2 A_D3 Address Input Data Input/Output Connect to VDD (6.0V) High Active, Latch Address in falling edge No connection Programming Power (0V, 12.75V) Connect to VSS (0V) Connect to VDD (6.0V) A8 A9 A10 A11 A0 A1 A2 A3 D0 D1 D2 D3 Read/Write Control Address/Data Control Connect to VDD (6.0V) Address Input Data Input/Output
Description
A12 A13 A14 A15 A4 A5 A6 A7 D4 D5 D6 D7
Table 20-1 Pin Description in EPROM Mode ( HMS1304/2A )
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A_D4 A_D5 A_D6 A_D7 VDD CTL0 CTL1 CTL2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11 NC
A_D3 A_D2 A_D1 A_D0
VSS VPP
EPROM Enable
Figure 20-3 Pin Assignment ( HMS1204/2A ) User Mode Pin No. Pin Name
1 2 3 4 5 6 7 8 9,10 11 12 13 14 15,16 17 18 19 20 RA4 (AN4) RA5 (AN5) RA6 (AN6) RA7 (AN7) VDD RB0/AN0/AVref RB1/BUZ RB2/INT0 RB3~4 XIN XOUT RESET VSS RC0, 1 RA0 (EC0) RA1 (AN1) RA2 (AN2) RA3 (AN3)
EPROM MODE Pin Name
A_D4 A_D5 A_D6 A_D7 VDD CTL0 CTL1 CTL2 VDD EPROM Enable NC VPP VSS VDD A_D0 A_D1 A_D2 A_D3 Address Input Data Input/Output Connect to VDD (6.0V) High Active, Latch Address in falling edge No connection Programming Power (0V, 12.75V) Connect to VSS (0V) Connect to VDD (6.0V) A8 A9 A10 A11 A0 A1 A2 A3 D0 D1 D2 D3 Read/Write Control Address/Data Control Connect to VDD (6.0V) Address Input Data Input/Output
Description
A12 A13 A14 A15 A4 A5 A6 A7 D4 D5 D6 D7
Table 20-2 Pin Description in EPROM Mode ( HMS1204/2A )
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A_D4 A_D5 A_D6 A_D7 VDD CTL0 CTL1 CTL2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 NC
A_D3 A_D2 A_D1 A_D0 VSS VPP
EPROM Enable
Figure 20-4 Pin Assignment ( HMS1104/2A ) User Mode Pin No. Pin Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RA4 (AN4) RA5 (AN5) RA6 (AN6) RA7 (AN7) VDD RB0/AN0/AVref RB2/INT0 RB4/PWM/COMP XIN XOUT RESET VSS RA0 (EC0) RA1 (AN1) RA2 (AN2) RA3 (AN3)
EPROM MODE Pin Name
A_D4 A_D5 A_D6 A_D7 VDD CTL0 CTL1 CTL2 EPROM Enable NC VPP VSS A_D0 A_D1 A_D2 A_D3 Address Input Data Input/Output High Active, Latch Address in falling edge No connection Programming Power (0V, 12.75V) Connect to VSS (0V) A8 A9 A10 A11 A0 A1 A2 A3 D0 D1 D2 D3 Read/Write Control Address/Data Control Connect to VDD (6.0V) Address Input Data Input/Output
Description
A12 A13 A14 A15 A4 A5 A6 A7 D4 D5 D6 D7
Table 20-3 Pin Description in EPROM Mode ( HMS1104/2A )
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TSET1
THLD1
TDLY1
THLD2
TDLY2
~ ~
EPROM Enable
TVPPS VIHP TVPPR
~ ~ ~ ~
~ ~
VPP CTL0
TVDDS 0V
~~ ~~
~~ ~~
VDD1H TCD1
CTL1 CTL2 A_D7~ A_D0
0V
TCD1 VDD1H
~ ~
0V
TCD1
TCD1
~ ~
~ ~
~ ~
HA VDD1H
LA
DATA IN
DATA OUT
LA
DATA IN
DATA OUT
~ ~
~ ~
VDD
High 8bit Address Input Low 8bit Address Input Write Mode Verify Low 8bit Address Input Write Mode Verify
Figure 20-5 Timing Diagram in Program (Write & Verify) Mode
After input a high address, output data following low address input
TSET1 THLD1 TDLY1
Another high address step
EPROM Enable
TVPPS VIHP
VPP CTL0
TVDDS 0V
T VPPR
VDD2H
CTL1 CTL2 A_D7~ A_D0
0V
TCD2 VDD2H TCD1
TCD2
0V
TCD1
HA VDD2H
LA
DATA
LA
DATA
HA
LA
DATA
VDD
High 8bit Address Input Low 8bit Address Input DATA Output Low 8bit Address Input DATA Output High 8bit Address Input Low 8bit Address Input DATA Output
Figure 20-6 Timing Diagram in READ Mode
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Parameter Programming Supply Current Supply Current in EPROM Mode VPP Level during Programming VDD Level in Program Mode VDD Level in Read Mode CTL2~0 High Level in EPROM Mode CTL2~0 Low Level in EPROM Mode A_D7~A_D0 High Level in EPROM Mode A_D7~A_D0 Low Level in EPROM Mode VDD Saturation Time VPP Setup Time VPP Saturation Time EPROM Enable Setup Time after Data Input EPROM Enable Hold Time after TSET1 EPROM Enable Delay Time after THLD1 EPROM Enable Hold Time in Write Mode EPROM Enable Delay Time after THLD2 CTL2,1 Setup Time after Low Address input and Data input CTL1 Setup Time before Data output in Read and Verify Mode
Symbol IVPP IVDDP VIHP VDD1H VDD2H VIHC VILC VIHAD VILAD TVDDS TVPPR TVPPS TSET1 THLD1 TDLY1 THLD2 TDLY2 TCD1 TCD2
MIN 12.5 5.5 0.8VDD 0.9VDD 1 1
TYP 12.75 6 2.7 200 500 200 100 200 100 100
MAX 50 20 13 6.6 0.2VDD 0.1VDD 1 -
Unit mA mA V V V V V V V mS mS mS nS nS nS nS nS nS nS
Table 20-4 AC/DC Requirements for Program/Read Mode
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START
Set VDD=VDD1H Verify for all address Report Verify failure NO
Set VPP=VIHP
Report Programming failure NO
Verify OK YES
Verify blank YES First Address Location Next address location
Report Programming OK
N=1
Report Programming failure NO
VDD=Vpp=0v
END
EPROM Write 100uS program time
YES N > 25
Verify pass YES Apply 3N program cycle
NO
NO Last address YES
Figure 20-7 Programming Flow Chart
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START
Set VDD=VDD2H
Verify for all address
Set VPP=VIHP
First Address Location Next address location NO
Last address YES Report Read OK
VDD=0V VPP=0V
END
Figure 20-8 Reading Flow Chart
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APPENDIX
HMS871C130XA/120XA/110XA
APPENDIX
A. INSTRUCTION MAP
LOW 00000 HIGH 00
00001 01 SET1 dp.bit
00010 02
00011 03
00100 04 ADC #imm SBC #imm CMP #imm OR #imm AND #imm EOR #imm LDA #imm LDM dp,#imm
00101 05 ADC dp SBC dp CMP dp OR dp AND dp EOR dp LDA dp STA dp
00110 06 ADC dp+X SBC dp+X CMP dp+X OR dp+X AND dp+X EOR dp+X LDA dp+X STA dp+X
00111 07 ADC !abs SBC !abs CMP !abs OR !abs AND !abs EOR !abs LDA !abs STA !abs
01000 08 ASL A ROL A LSR A ROR A INC A DEC A TXA TAX
01001 09 ASL dp ROL dp LSR dp ROR dp INC dp DEC dp LDY dp STY dp
01010 0A
01011 0B
01100 0C BIT dp COM dp TST dp CMPX dp CMPY dp DBNE dp LDX dp STX dp
01101 0D POP A POP X POP Y POP PSW CBNE dp+X XMA dp+X LDX dp+Y STX dp+Y
01110 0E PUSH A PUSH X PUSH Y PUSH PSW TXSP TSPX XCN XAX
01111 0F BRK BRA rel PCALL Upage RET INC X DEC X DAS STOP
000 001 010 011 100 101 110 111
CLRC CLRG DI CLRV SETC SETG EI
BBS BBS A.bit,rel dp.bit,rel
TCALL SETA1 0 .bit TCALL CLRA1 2 .bit TCALL 4 TCALL 6 NOT1 M.bit OR1 OR1B
TCALL AND1 8 AND1B TCALL EOR1 10 EOR1B TCALL 12 TCALL 14 LDC LDCB STC M.bit
LOW 10000 HIGH 10
10001 11 CLR1
dp.bit
10010 12 BBC
A.bit,rel
10011 13 BBC
dp.bit,rel
10100 14 ADC {X} SBC {X} CMP {X} OR {X} AND {X} EOR {X} LDA {X} STA {X}
10101 15 ADC !abs+Y SBC !abs+Y CMP !abs+Y OR !abs+Y AND !abs+Y EOR !abs+Y LDA !abs+Y STA !abs+Y
10110 16 ADC [dp+X] SBC [dp+X] CMP [dp+X] OR [dp+X] AND [dp+X] EOR [dp+X] LDA [dp+X] STA [dp+X]
10111 17 ADC [dp]+Y SBC [dp]+Y CMP [dp]+Y OR [dp]+Y AND [dp]+Y EOR [dp]+Y LDA [dp]+Y STA [dp]+Y
11000 18 ASL !abs ROL !abs LSR !abs ROR !abs INC !abs DEC !abs LDY !abs STY !abs
11001 19 ASL dp+X ROL dp+X LSR dp+X ROR dp+X INC dp+X DEC dp+X LDY dp+X STY dp+X
11010 1A TCALL 1 TCALL 3 TCALL 5 TCALL 7 TCALL 9 TCALL 11 TCALL 13 TCALL 15
11011 1B JMP !abs CALL !abs MUL DBNE Y DIV XMA {X} LDA {X}+ STA {X}+
11100 1C BIT !abs TEST !abs
11101 1D ADDW dp SUBW dp
11110 1E LDX #imm LDY #imm CMPX #imm CMPY #imm INC Y DEC Y XAY XYX
11111 1F JMP [!abs] JMP [dp] CALL [dp] RETI TAY TYA DAA NOP
000 001 010 011 100 101 110 111
BPL rel BVC rel BCC rel BNE rel BMI rel BVS rel BCS rel BEQ rel
TCLR1 CMPW !abs dp CMPX !abs CMPY !abs XMA dp LDX !abs STX !abs LDYA dp INCW dp DECW dp STYA dp CBNE dp
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B. INSTRUCTION SET
1. ARITHMETIC/ LOGIC OPERATION
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MNEMONIC ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y ADC { X } AND #imm AND dp AND dp + X AND !abs AND !abs + Y AND [ dp + X ] AND [ dp ] + Y AND { X } ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [ dp + X ] CMP [ dp ] + Y CMP { X } CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y DIV OP BYTE CYCLE CODE NO NO 04 2 2 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF A8 A9 B9 B8 AF BE 9B 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1 1 2 2 3 1 1 1 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 2 4 5 5 2 2 12 Divide : YA / X Q: A, R: Y NV--H-Z1'S Complement : ( dp ) ~( dp ) Decimal adjust for addition Decimal adjust for subtraction Decrement M (M)-1 N-----ZN-----ZN-----ZC N-----ZC N-----ZCompare Y contents with memory contents (Y)-(M) N-----ZC Compare X contents with memory contents (X)-(M) N-----ZC N-----ZC Compare accumulator contents with memory contents (A) -(M) Arithmetic shift left
C 7 6 5 4 3 2 1 0 "0"
OPERATION Add with carry. A(A)+(M)+C
FLAG NVGBHIZC
NV--H-ZC
Logical AND A (A)(M) N-----Z-
N-----ZC
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HMS871C130XA/120XA/110XA
NO. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
MNEMONIC EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y EOR { X } INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [ dp + X ] OR [ dp ] + Y OR { X } ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } TST dp XCN
OP BYTE CYCLE OPERATION CODE NO NO A4 2 2 Exclusive OR A5 2 3 A (A)(M) A6 A7 B5 B6 B7 B4 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Test memory contents for negative or zero ( dp ) - 00H Exchange nibbles within the accumulator A7~A4 A3~A0 Subtract with carry A ( A ) - ( M ) - ~( C ) Rotate right through carry
7 6 5 4 3 2 1 0 C "0"
FLAG NVGBHIZC
N-----Z-
Increment M (M)+1
N-----ZN-----Z-
Logical shift right
7 6 5 4 3 2 1 0 C
N-----ZC
Multiply : YA Y x A Logical OR A (A)(M)
N-----Z-
N-----Z-
Rotate left through carry
C 7 6 5 4 3 2 1 0
N-----ZC
N-----ZC
NV--HZC
N-----ZN-----Z-
Apr. 2001 Ver 1.0
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HMS87C130XA/120XA/110XA
2. REGISTER / MEMORY OPERATION
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MNEMONIC LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [ dp + X ] LDA [ dp ] + Y LDA { X } LDA { X }+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + X LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [ dp + X ] STA [ dp ] + Y STA { X } STA { X }+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp+X XMA {X} XYX OP BYTE CYCLE CODE NO NO C4 2 2 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 4 5 5 6 7 7 4 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Exchange X-register contents with Y-register : X Y -------Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X sp Transfer X-register contents to accumulator: A X Transfer X-register contents to stack-pointer: sp X Transfer Y-register contents to accumulator: A Y N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZStore Y-register contents in memory (M) Y -------X- register auto-increment : ( M ) A, X X + 1 Store X-register contents in memory (M) X --------------Store accumulator contents in memory (M)A Load Y-register Y(M) N-----ZX- register auto-increment : A ( M ) , X X + 1 Load memory with immediate data : ( M ) imm Load X-register X (M) N-----Z-------N-----ZOPERATION Load accumulator A(M) FLAG NVGBHIZC
Exchange X-register contents with accumulator :X A -------Exchange Y-register contents with accumulator :Y A -------Exchange memory contents with accumulator (M)A N-----Z-
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Apr. 2001 Ver 1.0
HMS871C130XA/120XA/110XA
3. 16-BIT OPERATION
NO. 1 2 3 4 5 6 7 MNEMONIC ADDW dp CMPW dp DECW dp INCW dp LDYA dp STYA dp SUBW dp OP BYTE CYCLE CODE NO NO 1D 5D BD 9D 7D DD 3D 2 2 2 2 2 2 2 5 4 6 6 5 5 5 OPERATION 16-Bits add without carry YA ( YA ) + ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : (YA) - (dp+1)(dp) Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 Load YA YA ( dp +1 ) ( dp ) Store YA ( dp +1 ) ( dp ) YA 16-Bits substact without carry YA ( YA ) - ( dp +1) ( dp) FLAG NVGBHIZC NV--H-ZC N-----ZC N-----ZN-----ZN-----Z-------NV--H-ZC
4. BIT MANIPULATION
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNEMONIC AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLRA1 A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs OP BYTE CYCLE OPERATION CODE NO NO 8B 3 4 Bit AND C-flag : C ( C ) ( M .bit ) 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6 Bit AND C-flag and NOT : C ( C ) ~( M .bit ) Bit test A with memory : Z ( A ) ( M ) , N ( M7 ) , V ( M6 ) Clear bit : ( M.bit ) "0" Clear A bit : ( A.bit ) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C ( C ) ( M .bit ) ---------------------0 --0-----0--0--FLAG NVGBHIZC -------C -------C MM----Z-
-------C Bit exclusive-OR C-flag and NOT : C ( C ) ~(M .bit) -------C Load C-flag : C ( M .bit ) -------C Load C-flag with NOT : C ~( M .bit ) Bit complement : ( M .bit ) ~( M .bit ) Bit OR C-flag : C ( C ) ( M .bit ) Bit OR C-flag and NOT : C ( C ) ~( M .bit ) Set bit : ( M.bit ) "1" Set A bit : ( A.bit ) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : ( M .bit ) C Test and clear bits with A : A - ( M ) , ( M ) ( M ) ~( A ) Test and set bits with A : A-(M), (M) (M)(A) -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z-
Apr. 2001 Ver 1.0
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HMS87C130XA/120XA/110XA
5. BRANCH / JUMP OPERATION
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNEMONIC BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp+X,rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL upage OP BYTE CYCLE OPERATION CODE NO NO y2 2 4/6 Branch if bit clear : y3 3 5/7 if ( bit ) = 0 , then pc ( pc ) + rel x2 x3 50 D0 F0 90 70 10 2F 30 B0 3B 5F FD 8D AC 7B 1B 1F 3F 4F 2 3 2 2 2 2 2 2 2 2 2 3 2 3 3 3 2 3 3 2 2 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 8 8 5/7 6/8 5/7 4/6 3 5 4 6 U-page call M(sp) ( pcH ), sp sp - 1, M(sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH "0FFH" . Table call : (sp) ( pcH ), sp sp - 1, M(sp) ( pcL ),sp sp - 1, pcL (Table vector L), pcH (Table vector H) -------Branch if bit set : if ( bit ) = 1 , then pc ( pc ) + rel Branch if carry bit clear if ( C ) = 0 , then pc ( pc ) + rel Branch if carry bit set if ( C ) = 1 , then pc ( pc ) + rel Branch if equal if ( Z ) = 1 , then pc ( pc ) + rel Branch if minus if ( N ) = 1 , then pc ( pc ) + rel Branch if not equal if ( Z ) = 0 , then pc ( pc ) + rel Branch if minus if ( N ) = 0 , then pc ( pc ) + rel Branch always pc ( pc ) + rel Branch if overflow bit clear if (V) = 0 , then pc ( pc) + rel Branch if overflow bit set if (V) = 1 , then pc ( pc ) + rel Subroutine call M( sp)( pcH ), spsp - 1, M(sp) (pcL), sp sp - 1, -------if !abs, pc abs ; if [dp], pc L ( dp ), pcH ( dp+1 ) . Compare and branch if not equal : if ( A ) ( M ) , then pc ( pc ) + rel. Decrement and branch if not equal : if ( M ) 0 , then pc ( pc ) + rel. Unconditional jump pc jump address ------------------------------------------------------------------------------------FLAG NVGBHIZC ---------------
24
TCALL n
nA
1
8
--------
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Apr. 2001 Ver 1.0
HMS871C130XA/120XA/110XA
6. CONTROL OPERATION & etc.
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 MNEMONIC BRK DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET OP BYTE CYCLE CODE NO NO 0F 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F 1 1 1 1 1 1 1 1 1 1 1 1 1 8 3 3 2 4 4 4 4 4 4 4 4 5 OPERATION FLAG NVGBHIZC
Software interrupt : B "1", M(sp) (pcH), sp sp-1, M(s) (pcL), sp sp - 1, M(sp) (PSW), sp sp -1, ---1-0-pcL ( 0FFDEH ) , pcH ( 0FFDFH) . Disable interrupts : I "0" Enable interrupts : I "1" No operation sp sp + 1, A M( sp ) sp sp + 1, X M( sp ) sp sp + 1, Y M( sp ) sp sp + 1, PSW M( sp ) M( sp ) A , sp sp - 1 M( sp ) X , sp sp - 1 M( sp ) Y , sp sp - 1 M( sp ) PSW , sp sp - 1 Return from subroutine -------sp sp +1, pcL M( sp ), sp sp +1, pcH M( sp ) Return from interrupt sp sp +1, PSW M( sp ), sp sp + 1, pcL M( sp ), sp sp + 1, pcH M( sp ) Stop mode ( halt CPU, stop oscillator ) restored --------------restored ------------0------1---------
14 15
RETI STOP
7F EF
1 1
6 3
Apr. 2001 Ver 1.0
vii

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