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| (R) IRF740S N - CHANNEL 400V - 0.48 - 10 A - D2PAK PowerMESHTM MOSFET TYPE IRF740S s s s s s s V DSS 400 V R DS(on) < 0.55 ID 10 A TYPICAL RDS(on) = 0.48 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED FOR THROUGH-HOLE VERSION CONTACT SALES OFFICE 3 1 D2PAK TO-263 (Suffix "T4") DESCRIPTION This power MOSFET is designed using the company's consolidated strip layout-based MESH OVERLAYTM process. This technology matches and improves the performances compared with standard parts from various sources. APPLICATIONS s HIGH CURRENT SWITCHING s UNINTERRUPTIBLE POWER SUPPLY (UPS) s DC/DC COVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT. INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR V GS ID ID IDM (*) P t ot dv/dt(1) T stg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) Gate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) Total Dissipation at Tc = 25 C Derating F actor Peak Diode Recovery voltage slope Storage T emperature Max. O perating Junction Temperature o o o Value 400 400 20 10 6.3 40 125 1.0 4.0 -65 to 150 150 (1) ISD 10 A, di/dt 120 /s, VDD V(BR)DSS, Tj TJMAX Uni t V V V A A A W W/ C V/ ns o o o C C (*) Pulse width limited by safe operating area August 1998 1/8 IRF740S THERMAL DATA R t hj-ca se Rthj -amb R thc- si nk Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose 1.0 62.5 0.5 300 C/W oC/W o C/W o C o AVALANCHE CHARACTERISTICS Symb ol I AR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 o C, I D = IAR , VDD = 50 V) Max Valu e 10 520 Unit A mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 250 A V GS = 0 Min. 400 1 50 100 Typ . Max. Un it V A A nA V DS = Max Rating Zero G ate Voltage Drain Current (VGS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) V GS = 20 V T c = 125 C o ON () Symb ol V GS(th) R DS( on) ID(o n) Parameter Gate Threshold Voltage V DS = VGS Test Cond ition s ID = 250 A ID = 5.3 A 10 Min. 2 Typ . 3 0.48 Max. 4 0.55 Un it V A Static Drain-source On V GS = 10V Resistance On State Drain Current V DS > I D(on) x R DS(on) max V GS = 10 V DYNAMIC Symb ol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse T ransfer Capacitance Test Cond ition s V DS > I D(on) x R DS(on) max V DS = 25 V f = 1 MHz ID = 6 A VGS = 0 Min. 5.8 1400 220 27 Typ . Max. Un it S pF pF pF 2/8 IRF740S ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symb ol t d(on) tr Qg Q gs Q gd Parameter Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Cond ition s V DD = 200 V I D = 5 A VGS = 10 V R G = 4.7 (see test circuit, figure 1) V DD = 320 V I D = 10.7 A VGS = 10V Min. Typ . 17 10 35 11 12 43 Max. Un it ns ns nC nC nC SWITCHING OFF Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Cond ition s V DD = 320 V I D = 10 A R G = 4.7 V GS = 10 V (see test circuit, figure 3) Min. Typ . 10 10 17 Max. Un it ns ns ns SOURCE DRAIN DIODE Symb ol I SD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 10 A V GS = 0 370 3.2 17 Test Cond ition s Min. Typ . Max. 10 40 1.6 Un it A A V ns C A I SD =10 A di/dt = 100 A/s o T j = 150 C V DD = 100 V (see test circuit, figure 3) () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 IRF740S Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 IRF740S Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 IRF740S Fig. 1: Unclamped Inductive Load Test Circuit Fig. 1: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 IRF740S TO-263 (D2PAK) MECHANICAL DATA mm MIN. A A1 B B2 C C2 D E G L L2 L3 4.3 2.49 0.7 1.25 0.45 1.21 8.95 10 4.88 15 1.27 1.4 TYP. MAX. 4.6 2.69 0.93 1.4 0.6 1.36 9.35 10.28 5.28 15.85 1.4 1.75 MIN. 0.169 0.098 0.027 0.049 0.017 0.047 0.352 0.393 0.192 0.590 0.050 0.055 inch TYP. MAX. 0.181 0.106 0.036 0.055 0.023 0.053 0.368 0.404 0.208 0.624 0.055 0.068 DIM. E C2 L2 A D L L3 B2 B G A1 C P011P6/C 7/8 IRF740S Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. . 8/8 |
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