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MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
September 1983 Revised February 1999
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
General Description
The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positivegoing transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. The 74HC logic family is functionally and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 20 ns s Wide power supply range: 2-6V s Low quiescent current: 40 A maximum (74HC Series) s Low input current: 1 A maximum s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number MM74HC74AM MM74HC74ASJ MM74HC74AMTC MM74HC74AN Package Number M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Inputs PR L H L H H H CLR H L L H H H CLK X X X L D X X X H L X Q H L H (Note 1) H L Q0 Outputs Q L H H (Note 1) L H Q0
Note: Q0 = the level of Q before the indicated input conditions were established. Note 1: This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) level.
(c) 1999 Fairchild Semiconductor Corporation
DS005106.prf
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MM74HC74A
Logic Diagram
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MM74HC74A
Absolute Maximum Ratings(Note 2)
(Note 3) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 4) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C (Note 5)
VCC 2.0V 4.5V 6.0V VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VI N =VCC or GND IOUT = 0 A 6.0V VIN = VCC or GND 4.5V 6.0V 6.0V 4.5V 6.0V 2.0V 4.5V 6.0V
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, OUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V -40 +85 1000 500 400 C ns ns ns 2 0 Max 6 VCC Units V V
-0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C 600 mW 500 mW
Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Note 4: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage Conditions
TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.3 5.2 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 4.0
TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 40 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 80
Units V V V V V V V V V V V V V V V V A A
Note 5: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC74A
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPHL, tPLH tREM ts tH tW Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q or Q Maximum Propagation Delay Preset or Clear to Q or Q Minimum Removal Time, Preset or Clear to Clock Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Minimum Pulse Width Clock, Preset or Clear 8 16 ns 0 0 ns 10 20 ns 6 5 ns 17 40 ns Conditions Typ 72 10 Guaranteed Limit 30 30 Units MHz ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay Clock to Q or Q tPHL, tPLH Maximum Propagation Delay Preset or Clear To Q or Q tREM Minimum Removal Time Preset or Clear To Clock ts Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum, Pulse Width Clock, Preset or Clear tTLH, tTHL Maximum Output Rise and Fall Time tr , tf Maximum Input Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 6) Maximum Input Capacitance
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
Conditions
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V
TA = 25C Typ 22 72 94 34 12 10 66 20 16 20 6 5 35 10 8 6 30 35 110 22 19 150 30 26 50 10 9 80 16 14 0 0 0 30 9 8 25 7 6 80 16 14 75 15 13 1000 500 400 80 5 10
TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 5 24 28 140 28 24 190 38 33 65 13 11 100 20 17 0 0 0 101 20 17 95 19 16 1000 500 400 4 20 24 165 33 28 225 45 38 75 15 13 120 24 20 0 0 0 119 24 20 110 22 19 1000 500 400
Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
(per flip-flop)
10
10
pF
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MM74HC74A
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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MM74HC74A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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