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MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Preliminary
This document is a preliminary Target Spec. and some of the contents are subject to change without notice.
PINCONFIGURATION (TOP VIEW) Vcc DQCl DQCu CC1# CC0# WE# CS# CMd# CMs# K DQ0 Vss DQ1 DQ2 VddQ DQ3 Vss DQ4 VccQ DQ5 DQ6 Vss DQ7 MCL As0 As1 As2 RAS# CAS# DTD# Ad0 Ad1 Ad2 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58
DESCRIPTION
1. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit. The block data transfer between the DRAM and the data transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a fundamental advantage over a conventional DRAM/SRAM cache. The RAM is fabricated with a high performance CMOS process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low cost are essential. The use of quadruple-layer polysilicon process combined with silicide and double layer aluminum wiring technology, a single-transistor dynamic storage stacked capacitor cell, and a six-transistor static storage cache cell provide high circuit density at reduced costs.
2.
400 mil 70Pin TSOP Type II 0.65mm Lead Pitch
57 56 55 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
Vss Ad9 Ad8 Ad7 Ad11 Ad10 As9 As8 As7 As6 DQ15 Vss DQ14 DQ13 VccQ DQ12 Vcc DQ11 VccQ DQ10 DQ9 Vss DQ8 MCH G# As5 As4 As3 Ad6 Ad5 Ad4 Ad3 ADF# Vss
FEATURES
Type name
M5M4V16169TP/RT-7 M5M4V16169TP/RT-8 M5M4V16169TP/RT-10 M5M4V16169TP/RT-15 SRAM Access/cycle 5.6ns/7ns 6.4ns/8ns 8.0ns/10ns 8.0ns/15ns DRAM Access/cycle 49ns/70ns 56ns/80ns 60ns/90ns 75ns/120ns Power Dissipation (Typ) DRAM: 530 SRAM: 860 DRAM: 500 SRAM: 800 DRAM: 430 SRAM: 660 DRAM: 330 SRAM: 420
Package code:70P3S-L Vss Ad9 Ad8 Ad7 Ad11 Ad10 As9 As8 As7 As6 DQ15 Vss DQ14 DQ13 VccQ DQ12 Vcc
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 3 4 5 6 7 8 9 10 11 12 13
# 70-pin,400-mil TSOP (type II ) with 0.65mm lead pitch and 23.49mm package length. # Multiplexed DRAM address inputs for reduced pin count and higher system densities. # Selectable output operation (transparent / latched / registered) using set command register cycle. # Single 3.3V +/- 0.3V Power Supply. (3.3V +/- 0.15V for -7 part) # 2048 refresh cycles every 64ms (Ad0->Ad10). # Programmable burst length (1,2,4,8) and burst sequence (sequential,interleave) with no latency. # Synchronous design for precise control with an external clock (K). # Output retention by advanced mask clock (CMs#). # All inputs/outputs low capacitance and LVTTL compatible. # Separate DRAM and SRAM address inputs for fast SRAM access. # Page Mode capability. # Auto Refresh capability. # Self Refresh capability.
: Master Clock K : Chip Select CS# : DRAM Clock Mask CMd# : Row Addr. Strobe RAS# : Column Addr. Strobe CAS# : Data Transfer Direction DTD# : DRAM Address Ad : SRAM Clock Mask CMs# CC0#,CC1# : Control Clocks : Write Enable WE# : I/O Byte Control DQC(u/l) : SRAM Address As DQ11 : Output Enable G# VccQ : Data I/O DQ DQ10 : Power Supply Vcc DQ9 : DQ Power Supply VccQ Vss : Ground Vss DQ8 :Address Fetch clock ADF# MCH This pin can be None-Connect. G# :Must Connect Low MCL As5 :Must Connect High MCH As4 As3 Ad6 Ad5 Ad4 Ad3 ADF# Vss
400 mil 70Pin TSOP Type II 0.65mm Lead Pitch
14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Vcc DQCl DQCu CC1# CC0# WE# CS# CMd# CMs# K DQ0 Vss DQ1 DQ2 VccQ DQ3 Vss DQ4 VccQ DQ5 DQ6 Vss DQ7 MCL As0 As1 As2 RAS# CAS# DTD# Ad0 Ad1 Ad2 Vcc
Package code:70P3S-M
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
BLOCK DIAGRAM 1
Ad11 66 Ad10 65 Col.3-7 Ad9 Ad8
DRAM Address Input
Vcc
1 54 35
Vss
12 23 48 59 70 17 36
VccQ
15 20 51 56 29 RAS#
(Row Address strobe)
69 68 67 41 40 Row 0-11
Column Block Decoder
30 CAS#
(Column Address strobe)
31 DTD#
(Data Transfer Direction)
Ad7 Ad6 Ad5 Ad4 Ad3 Ad2 Ad1 Ad0
1M bit DRAM Array
Mask
01 7
8 CMd#
(Clock Mask for DRAM)
1M x 16= 16M DRAM KBuffer
39 38 34 33 32 Command (0-6)
RB1 RB2
7 CS# 10 K
Timing control
(Chip Select) (Master ClocK)
Sense Amplifier and I/O control Mask 0 1 Read Buffer1 2 7
9 CMs#
(Clock Mask for SRAM)
6 WE#
(Write Enable) (Control Clock 0)
5 CC0# 4 CC1#
(Control Clock 1)
WB2 Mask WB1 Mask As9 64 As8 63 As7 62
SRAM Address input
WB2M
WB2
Read Buffer2 Write Buffer 2 Write Buffer 1
WB1M WB1
37 ADF#
(Address Fetch)
3 DQCu(Enable upper) 2 DQCl(Enable lower) 01 2 As3-9
S/A and I/O
7
16
As6 61 As5 44 As4 43 As3 42 As2 28 As1 27 As0 26 As0-2
Col.Decoder
Din Buffer
1KBit SRAM Array
1Kx16=16K SRAM
Main Amp.
11 13 14 16 19 21 22 24 47 49 50 52 55 57 58 60 45
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 G# (Output Enable) 2
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MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
BLOCK DIAGRAM 2 DRAM 1MX16
Ad3-7 1 of 32 Decode 8X16 Block
DRAM Row Decoder 8X16
8X16
Ad0-11 1 of 4096 Decode
RB1 WB2
Lower Byte Upper Byte Lower Byte Upper Byte
DQ0-7
DQ8-15
As0-2 1of8 Decode
As0-2 1of8Decode
RB2
Lower Byte Upper Byte
8X16
16 bits DQs 16 bits 16 bits
WB1
Lower Byte Upper Byte
8X16 8X16 Block
8X16 16 bits
SRAM 1KX16
As0-2 1of8Decode
SRAM Row Decoder
As3 - 9 1 of 128 Decode
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
FUNCTION TRUTH TABLE
Mnemonic
SRAM CS# H X L L L L L L L L L L X L L L L L L L L L L L L L L L
DQC CMs# CC0# CC1# (u/l) WE#
Previous
As
(SRAM address) Previous
DRAM
CMd# RAS# CAS# DTD#
Ad
(DRAM address)
Ad2 Ad1 Ad0
CODE NOP SPD LBM DES SR SW BRT BWT BRTR BWTW BR BW DPD DNOP DRT DWT1 DWT1R DWT2 DWT2R DWT3 DWT3R DWT4 DWT4R ACT PCG ARF SRF SCR
As0-9 X X X X As0-9 As0-9 As3-9 As3-9
(2) (2)
Ad0-11 X X X X X X X X X X X X X X
Ad3-7 (2) (Col.Block) Ad3-7 (2) (Col.Block) Ad3-7 (2) (Col.Block) Ad3-7 (2) (Col.Block) Ad3-7 (2) (Col.Block) Ad3-7 (2) (Col.Block) Ad3-7 (2) (Col.Block) Ad3-7 (2) (Col.Block) Ad3-7 (2) (Col.Block) Ad0-11 (Row Add.)
H L H H H H H H H H H H X X X X X X X X X X X X X X X X
X X H H H H L L L L L L X X X X X X X X X X X X X X X X
X X H H L L H H H H L L X X X X X X X X X X X X X X X X
X X H X H H L L H H H H X X X X X X X X X X X X X X X X
X X L X H L H L H L H L X X X X X X X X X X X X X X X X
H X X X X X X X X X X X L H H H H H H H H H H H H H H H
(7) (8)
X X X X X X X X X X X X X H H H H H H H H H H L L L L L
(1)
X X X X X X X X X X X X X (1) H L L L L L L L L L H H L L L
X X X X X X X X X X X X X (1) X H L L L L L L L L H L H H L
As0-9 As0-9 As0-2 As0-2 X X X X X X X X X X X X X X X X
(2) (2)
0 0 0 0 0 1 1 1 1
0 0 0 1 1 0 0 1 1
0 0 1 0 1 0 1 0 1
X X X Command
NOTES 1) For the DPD function, the RAS#, CAS# and DTD# inputs are DON'T CARE except for the L,L,H combination. (Respectively). 2) The unused addresses must be set to Low. 3) Use New: If BW or BWT or BWTW is initiated the same cycle as DWT1 or DWT1R, new data is loaded into the buffer and transferred to DRAM. 4) Clear 1 or 2 Transfer Mask Bits (as addressed by As0-2 and DQCU/L).
5) Actual number of bits transfer depends on the state of the DTBW Mask and the DQCU/DQCL inputs. Note: If DQC(U/L) is Low, the corresponding DQ(s) is(are) disabled (Input and Output Buffer). SR,SW,BR and BW cycles with DQCU and DQCL Low result in a Deselect SRAM operation. 6) Following a DWT1 or DWT1R cycle, the entire WB1 Transfer Mask is Set . (i.e. , data can no longer be transferred from WB1 to DRAM.) Succeeding Buffer-Writes or Buffer Write Transfers will Clear Mask bits. 7) CMd# during current cycle must be High (see timing diagram for Auto-Refresh). 8) CMd# during current cycle must be Low (see timing diagram for Self-Refresh).
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
FUNCTION TRUTH TABLE
Data Transfer Buffers
Write Buffers WB1 Load Load Load Use Use Use Use WB2 Load/ Use Load/ Use Use Use Load/ Use Load/ Use Use Use Xfer Masks WB1 WB2 Mask Mask Clear Mask Clear Mask Clear 1 (4) or 2 bits
Read Buffer RB1,2 -
DQ pin Din
-
Dout Hi-Z
Suspend
Function
No Operation SRAM Power Down& Data retention DRAM Power Down Deselect SRAM SRAM Read SRAM Write Buffer Read Xfer Buffer Write Xfer Buffer Read Xfer & Read Buffer Read Xfer & Read Buffer Read Buffer Write DRAM Power Down DRAM No OPeration DRAM Read Xfer DRAM Write Xfer1
DRAM Write Xfer1& Read
No operation No operation No operation SRAM->DO DIN->SRAM RB2->SRAM SRAM->WB1 RB2->SRAM->DO DIN->SRAM->WB1 RB2->DO DIN->WB1 No operation No operation DRAM->RB1->RB2 (3) WB1->WB2->DRAM WB1->WB2 (3) ->DRAM->RB1->RB2 WB2->DRAM WB2->DRAM ->RB1->RB2 WB1->WB2->DRAM WB1->WB2 (3) ->DRAM->RB1->RB2 WB2->DRAM WB2->DRAM->RB
(6)
Byte mask -
Hi-Z Hi-Z Valid Hi-Z Hi-Z Hi-Z Valid Hi-Z Valid Hi-Z
-
Valid
-
Use
-
Use
-
Valid
-
Use
-
Valid
-
Use
(6)
Load
-
Load/ Use Load/ Use Use Use
Use -
Load
-
DRAM Write Xfer2
DRAM Write Xfer2& Read
Load
-
Load
DRAM Write Xfer3
DRAM Write Xfer3& Read
Load Load
-
DRAM Write Xfer4
DRAM Write Xfer4& Read
Load
-
DRAM Activate DRAM Precharge Auto Refresh Self Refresh Entry Set Command Register
Function WB2 --> RB DRAM --> RB RB --> Dout RB --> SRAM
Page Call
Function Din --> SRAM Din --> WB1 SRAM --> WB1 WB1 --> WB2 WB2 --> DRAM
Data Transferred (max) (5) 8/16 bits (5) 8/16bits 128 bits (8X16bit-block) 128 bits (8X16bit-block) 128 bits (8X16bit-block)
Data Transferred (max) 128 bits (8X16bit-block) 128 bits (8X16bit-block) (5) 8/16 bits 128 bits (8X16bit-block)
DO: Data Out DIN: Data In WB1: Write Buffer 1 WB2: Write Buffer 2 RB: Read Buffer
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
PIN DESCRIPTIONS(1)
K Input Master Clock Provides the fundamental timing and the internal clock frequency for the CDRAM. All external timing parameters (with the exception of G# in read cycle and CMd# in Self refresh cycle) are specified with respect to the rising edge of K. DRAM Clock Mask controls the operation of the internal DRAM master clock (K). When CMd# is Low at the rising edge of K, the internal DRAM master clock (K) for the following cycle is ceased and input stages are powered-off, resulting in a DRAM Power Down. Row Address Strobe is used in conjunction with Master clock K (depending on the states of CMd#, CAS#, and DTD#) to activate the DRAM (latching the Row Address lines and accessing 1 of 4096 rows), initiate a DRAM precharge cycle, perform a DRAM Read or Write Transfer, DRAM Write Transfer & Read, set the command registers, start an Auto-Refresh cycle, enter a Self-Refresh cycle,create a DRAM NOP cycle, or power down the DRAM. Column Address Strobe is used in conjunction with the Master Clock K to latch the Column addresses. When preceded by RAS# in a DRAM access cycle, CAS# initiates a DRAM Write Transfer (WB1/2 -> DRAM, if DTD#=L), DRAM Write Transfer & Read (WB1/2 -> DRAM -> RB, if DTD#=L) or DRAM Read Transfer (DRAM -> RB, if DTD#=H), depending on the state of DTD# (see DTD# pin description). Data Transfer Direction controls DRAM-to-RB(read) / WB-to-DRAM (write) direction. If preceded by a RAS# low cycle, both CAS# and DTD# low (on the rising edge of K) initiate a DRAM Write Transfer cycle. If DTD# stays High with the above conditions, a DRAM Read Transfer cycle results. DTD# can also initiate DRAM Activate, DRAM Precharge, Auto-Refresh, Set-Command Register, and Self Refresh cycles. DRAM Address Lines are Multiplexed to reduce pin count. Ad0-Ad11 (@ RAS=low,CAS=high,DTD=high, K=Rising edge) specify the Row Address of the DRAM to activate and refresh the selected page and Ad3-Ad7 (@ RAS=high,CAS=low,K=Rising edge) specify the Block Address of the DRAM. In addition, Ad0-Ad2 (@ RAS=high,CAS=low, K=Rising edge) specify the transfer operation of the DRAM . Also Ad0-Ad9 (@RAS=low,CAS=low, DTD=low, K=Rising Edge) are used as the command in set command register cycle. The Chip Select controls the operation of the CDRAM. When CS#=H at the rising edge of K and the previous CMd# or CMs# is high, the chip is in No Operation mode. SRAM Clock Mask controls the operation of the internal SRAM master clock (Ks). When CMs# is asserted at a rising edge of K, the internal SRAM master clock for the following cycle is suspended, resulting in the power down of the SRAM portion of the circuit, including the Sense Amps. CMs# can also be used to retain output data during SRAM power-down.
CMd#
Input
RAS#
Input
CAS#
Input
DTD#
Input
Ad0-Ad11
Input
CS#
Input
CMs#
Input
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
PIN DESCRIPTIONS(2)
DQCl,DQCu Input DQCu/l are I/OByte control signals. If G#=Low, DQCu/l have a control of output impedence: DQCu controls upper DQs (DQ8-15) & DQCl controls lower DQs (DQ0-7). DQCu/l also control both input data during SRAM Writes or Buffer Writes and transfer mask during Buffer Writes. (WB1 transfer Masks for each byte are written (bits are cleared) during Buffer Writes depending on DQCu/l inputs.) Write Enable controls SRAM and Buffer read and write operations. A high on the WE# pin causes either a Buffer Read, SRAM Read, Buffer Read Transfer and/or a Buffer Read Transfer & Read to occur (depending on the state of the CC0# and CC1# bits). A low on the WE# pin causes either a Buffer Write, SRAM Write, Buffer Write Transfer and/or a Buffer Write Transfer & Write to occur (depending on the state of the CC0# and CC1# inputs) The Control Clock Inputs control SRAM and Buffer operations. CC0# is Low for all Buffer Writes, Reads, and Transfers, and High for all other SRAM operations. CC1# is high for all Buffer Read Transfers and Buffer Write Transfers , and Deselect SRAM. SRAM Addresses are non-multiplexed, and access 1024 - 16-bit words ( configured as 128 Rows X 8 Columns X 16 Bits, where the Block Size is 8 X 16) in the SRAM array. As0-As3 select word address within a block, and As3-As9 select the SRAM row(block). The Output Enable is an asynchronous input. G#=high forces the outputs to high impedence. Output operation is either transparent, latched, or registered depending on the state of the command register. The Data Lines for the CDRAM are asynchronously controlled by G#. VccQ is the DQ power supply and allows the device to operate in a mixed voltage system (e.g., 5V data bus). As specified in the Table: Recommended Operating Conditions, VccQ must be greater-than or equal-to the highest voltage experienced by the data bus. For 3.3V system operation, VccQ may be tied to Vcc.
WE#
Input
CC0#,CC1#
Inputs
As0-As9
Inputs
G#
Input
DQ0-DQ15
Inputs / Outputs
VccQ
Supply
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (1)
NOP No Operation. Outputs are high-impedance. All input buffers remain active. If CMs#=Low at the rising edge of K, the SRAM enters SRAM Power Down at the next rising edge of K. During this mode, the internal SRAM K clock becomes inactive. The Output Buffers remain enabled and are controlled by G#. All input buffers of SRAM clocks and SRAM addresses are inactive. All transfer functions and input/output operations to and from the SRAM and Buffer are disabled. This cycle is useful for output impedance control (Hi-Z,Low-Z) without G#. Output buffers are active during this cycle for registered output mode control. Data is read from the SRAM to the I/O pins. Addresses As0-As9 are used to select the data to be read. As3-As9 decode the SRAM Row (=Block), and As0-As2 decode (1 of 8) the 16bit word. DQCu and DQCl control the impedence (High-Z/Low-Z) of the upper and lower bytes, respectively. Data is written from the I/O pins to the SRAM. Addresses As0-As9 are used to select the location to be written. As3-As9 decode the SRAM Row (=Block), and As0-As2 decode (1of8) the 16-bit word to be written. DQCUu and DQCl control Upper and Lower byte writes, respectively.
DRAM 1MX16
8X16
DRAM RowDecoder
SRAM Power-Down
Deselect SRAM
SRAM Read
8X16Block
Ad3-7 1of32 Decode
8X16
Ad0-9 1of4096Decode
SRAM Write
DQ0-7
Lower Byte Upper Byte
WB2
DQ8-15
RB1
Lower Byte Upper Byte
8X16
As0-2 1of8Decode
RB2
Lower Byte Upper Byte
16bits
WB1
Lower Byte Upper Byte
As0-2 1of8 Decode
DQs
16bits 8X16
X
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (2)
Data is transferred from the Read Buffer (RB2) to the SRAM. Addresses As3-9 select the SRAM row to which the 8X16 bit block is to be written. Addresses As0-As2 must be set low.
DRAM 1M X 16
8X16
DRAM RowDecoder
8X16Block
Ad3-7 1of32 Decode
Ad0-11 1of4096Decode 8X16
Buffer Read Transfer
DQ0-7
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte Upper Byte
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
As0-2 1of8Decode
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data is transferred from the SRAM to the Write-Buffer1 (WB1). Addresses As3-As9 decode the SRAM Row (=8X16 bit block) to be transferred. Addresses As0-As2 must be set low. The Buffer Write Transfer cycle "clears" all transfer mask bits in the WB1 Mask (allowing all data to be transferred in a successive DRAM Write Transfer cycle).
DRAM 1M X 16
DRAM RowDecoder 8X16 8X16 Ad0-11 1of4096Decode 8X16Block
Ad3-7 1of32 Decode
Buffer Write Transfer
DQ0-7
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte
Upper Byte
8X16 As0-2 1of8 Decode
As0-2 1of8Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
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16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (3)
Data is transferred from the Read Buffer (RB2) to the SRAM, and simultaneously, data (16 bit word) is read from the RB2 to the I/O pins. Addresses As3-9 select the SRAM Row to which the 8X16 bit block is to be written. Addresses As0-As2 decode the 16-bit word to be read.
DRAM 1M X 16
DRAM RowDecoder
8X16Block
Ad3-7 1of32 Decode
8X16 8X16
Ad0-11 1of4096Decode
Buffer Read Transfer & SRAM Read
DQ0-7
Lower Byte Upper Byte
WB2
DQ8-15
Lower Byte
RB1 Byte Upper
Upper Byte
As0-2 1of8Decode
8X16
RB2
Lower Byte
16bits
As0-2 1of8Decode
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data is first written from the I/O pins to SRAM as decoded by As0-As9. Then, the SRAM Row (=Block) decoded by As3-As9 is transferred to the Write-Buffer1 (WB1). The Buffer Write Transfer cycle "clears" all transfer mask bits in the WB1 Mask (allowing all data to be transferred in a successive DRAM Write Transfer cycle). DQCu and DQCl control Upper and Lower byte writes respectively, however all transfer mask bits in the WB1 are cleared.
DRAM 1M X 16
DRAM RowDecoder 8X16 8X16
DQ0-7
8X16Block
Ad3-7 1of32 Decode
Buffer Write Transfer & SRAM Write
Ad0-11 1of4096Decode
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
RB2
Lower Byte Upper Byte
16bits
8X16
WB1
Lower Byte Upper Byte
As0-2 1of8 Decode
DQs
16bits 8X16
X
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (4)
Data is read from the Read Buffer (RB2) to the I/O pins. Addresses As0-As2 are used to select (1 of 8) the 16-bit word to be read. Addresses As3-As9 must be set low for this operation.
Ad3-7 1of32 Decode 8X16 8X16
DRAM 1M X 16
DRAM RowDecoder
8X16Block
Ad0-11 1of4096Decode
Buffer Read
DQ0-7
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits
WB1
Lower Byte Upper Byte
X
8X16
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data is written from the I/O pins to the Write-Buffer1. Addresses As0-A2 are used to select (1of8) the 16-bit word to be written. Addresses As3-As9 must be set low for this operation. The transfer mask bits associated with the Upper and Lower bytes are cleared in the WB1 Mask. DQCu and DQCl control Upper and Lower byte writes (and associated tranfer mask bits), respectively.
DRAM 1M X 16
DRAM RowDecoder
8X16Block
Ad3-7 1of32 Decode
8X16 8X16
Ad0-11 1of4096Decode
Buffer Write
DQ0-7
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
11
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (5)
DRAM Power-Down If CMd#=Low at the rising edge of K, the DRAM enters DRAM Power Down at the next rising edge of K. During this mode, the internal DRAM K clock becomes inactive. Also all input buffers of DRAM clocks and DRAM addresses are inactive. Note that the latency of DRAM Read Transfer cycle is not counted up in this cycle. The DNOP cycle is used when no other DRAM operations are desired, holding the DRAM in its present (precharge/activate) state. A Block (8x16) is transferred from the DRAM to the Read Buffer1 and 2 (RB1,RB2) as specified by Addresses Ad3-Ad7. Addresses Ad8-Ad11 and Ad0-Ad2 must be set to Low. After the Latency Period (specified in the Access Latency Table) new data will be present in the Read Buffer2. Prior to the Latency timeout, old data will be present in the RB2. (Notes 1,2,4)
DRAM 1M X 16
DRAM RowDecoder
DRAM NOP
8X16Block
Ad3-7 1of32 Decode
8X16
Ad0-11 1of4096Decode 8X16
DRAM Read Transfer
DQ0-7
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
12
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (6)
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by Addresses Ad3-Ad7. Addresses Ad8-Ad11 must be set to Low. The Mask present in WB1 is also transferred to WB2 and controls the data written to the DRAM. After data has been transferred from WB1 to WB2 in the present cycle, the entire WB1 Mask is Set. (Notes 3,4)
Ad3-7 1of32 Decode 8X16
DRAM 1M X 16
DRAM RowDecoder
8X16Block
DRAM Write Transfer1
DQ0-7
8X16
Ad0-11 1of4096Decode
WB2
Lower Byte Upper Byte
RB1
DQ8-15 Lower Byte Upper Byte
8X16 As0-2 1of8 Decode
As0-2 1of8Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by Addresses Ad3-Ad7. Addresses Ad8-A11 must be set to Low. The transfer mask present in WB1 is also transferred to WB2 and controls the data written to the DRAM. The block to which the data is written in DRAM is simultaneously transferred to the Read Buffer.(Notes 2,3,4)
Ad3-7 1of32 Decode
DRAM 1M X 16
DRAM RowDecoder
8X16Block
DRAM Write Transfer1 & Read
8X16 8X16
Ad0-11 1of4096Decode
DQ0-7
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
13
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (7)
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3Ad7. Addresses Ad8-Ad11 must be set to Low. The WB2 Mask controls the data written to the DRAM. With the DWT2 function, the WB2 data and WB2 transfer mask remain unchanged. (Note 4)
DRAM 1M X 16
DRAM RowDecoder 8X16 Ad0-11 1of4096Decode 8X16Block
Ad3-7 1of32 Decode
DRAM Write Transfer2
8X16
DQ0-7
WB2
Lower Byte Upper Byte
RB1
DQ8-15 Lower Byte Upper Byte
8X16 As0-2 1of8 Decode
As0-2 1of8Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3Ad7. Addresses Ad8-Ad11 must be set to Low. The WB2 transfer mask controls the data written to the DRAM. With the DWT2 function, the WB2 data and WB2 transfer mask remain unchanged. The block to which the data is written in DRAM is simultaneously transferred to the Read Buffer1 and 2. (Notes 1,2,4)
Ad3-7 1of32 Decode 8X16
DRAM 1MX16
8X16Block
DRAM RowDecoder Ad0-11 1of4096Decode
DRAM Write Transfer2 & Read
8X16
DQ0-7
WB2
Lower Byte Upper Byte
RB1
DQ8-15 Lower Byte Upper Byte
8X16 As0-2 1of8 Decode
As0-2 1of8Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
14
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (8)
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by Addresses Ad3-Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister controls the data written to the DRAM. The Byte Mask Register is set at Load Byte Mask cycle,where corresponding byte masks are set depending on DQ data in the cycle. (Note 4,5) The data of WB1 and the mask data of WBM1 are tranferred to WB2 and WBM2, however WBM1/2 is not used in this cycle.
Ad3-7 1of32 Decode 8X16
DRAM 256KX16
DRAM RowDecoder
8X16Block
DRAM Write Transfer3
DQ0-7 Lower Byte Upper Byte
Ad0-11 1of4096Decode 8X16
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder As3-9 1of128Decode
As0-2 1of8Decode
Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by Addresses Ad3-Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister controls the data written to the DRAM. The block to which the data is written in DRAM is simultaneously transferred to the Read Buffer.(Notes 1,2,4,5)
Ad3-7 1of32 Decode 8X16
DRAM 256KX16
DRAM RowDecoder
8X16Block
DRAM Write Transfer3 & Read
Ad0-11 1of4096Decode 8X16
DQ0-7
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder As3-9 1of128Decode
As0-2 1of8Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
15
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (9)
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister controls the data written to the DRAM. With the DWT4 function, the WB2 data and WB2 Mask remain unchanged. (Note 4,5)
DRAM 256KX16
DRAM RowDecoder 8X16 8X16Block
Ad3-7 1of32 Decode
DRAM Write Transfer4
DQ0-7 Lower Byte Upper Byte
Ad0-11 1of4096Decode 8X16
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder As3-9 1of128Decode
As0-2 1of8Decode
Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister controls the data written to the DRAM. With the DWT4R function, the WB2 data and WB2 transfer mask remain unchanged. The block to which the data is written in DRAM is simultaneously transferred to the Read Buffer. (Notes 1,2,4,5)
Ad3-7 1of32 Decode
DRAM 256KX16
DRAM RowDecoder
8X16Block
DRAM Write Transfer4 & Read
8X16 8X16
DQ0-7
Ad0-11 1of4096Decode
Lower Byte Upper Byte
WB2
RB1
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
RB2
Lower Byte Upper Byte
16bits
DQs
16bits 8X16
WB1
Lower Byte Upper Byte
X
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder As3-9 1of128Decode
As0-2 1of8Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
16
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (10)
DRAM Activate DRAM Precharge Addresses are latched from the Ad0-Ad11 inputs by the rising edge of K. Internally, a DRAM row is selected (Page Call) in preparation for a DRAM Read or Write Transfer cycle. A DRAM Precharge cycle must separate all DRAM Activate cycles. Internally, the active DRAM Row is deselected (completing the refresh process) and page-mode is disabled. The DRAM is precharged prior to another DRAM Activate cycle. Internally, a DRAM row is selected and refreshed (as addressed by an internal, self-incrementing counter), followed by an internally generated Precharge cycle. The Auto refresh cycle can be implemented only if the DRAM is in Precharge state (i.e., a Precharge or Auto-Refresh cycle occurred more recently than an Acitvate cycle). DRAM Auto-Refresh is similar to a CAS-BeforeRAS (CBR) mode in standard DRAMs. All clock buffers are suspended, and CMd# asynchronously controls Self Refresh (CMd# rising edge initiates exit from Self Refresh). During Self Refresh, device enters a low power mode, with 2048 automatic refresh cycles. When SCR is initiated,the addresses present on the Ad0-Ad11 DRAM Address pins determine the DRAM Read Transfer Latency, the Output Mode (transparent / latched / registered), and WB1 transfer mask mode (set-all/ no change). No DRAM operation is executed in this cycle. Refer to the SCR Truth Table for legal Address values. During SCR cycle and the following 3 clock cycles(totally 4 clock cycles), only NOP,DNOP orDPD are allowed in DRAM portion and only NOP,DES or SPD are done in SRAM portion. The set commands are valid at least after the above 4 clocks later and the previous function is not guaranteed to work if it has not been completed.(i.e. DRT ,DWT1&R,DWT2&R and SR,BR and BRTR with registered output mode.)
DRAM Auto-Refresh
DRAM Self Refresh
Set Command Register
Notes:
1) This function is performed in a Latency period specified in the Access Latency Table. 2) After the Latency Period (specified in the Access Latency Table) new data will be present in the Read Buffer2. Prior to the Latency timeout, old data will be present in the RB2. 3) After data has been transferred from WB1, the entire WB1 Mask is Set. 4) Valid Ad0-Ad2 addresses are shown in the FUNCTION TRUTH TABLE.
Power-On sequence
Before starting normal operation, the following power on sequence is necessary. 1) Apply power and maintain stable power (pause) for 500us. 2) Perform a precharge (PCG) operation. 3) After tRP, perform 8 auto refresh commands (ARF) with adequate interval (tRC). 4) Issue set command register (SCR) to initilize the mode register. After this sequence, the RAM is in idle state and ready for normal operation. Note that DNOP / DPD and DES / SPD or NOP command will be the stand-by command for the above power sequence. Vcc must be powered-on at the same time or before VccQ is on. And Vcc must be powered-off at the same time or after VccQ is off.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Output Operations Output appears from the rising edge of K clock. Transparent
DES SR SR DES SR SR
K DQC G#
tKHQX tKHA tKHQZ
K DQC
tKHA
G#
tGLA
DQ0-15
Q
DQ0-15
tGLQ
Q
tGHQ
Latched
DES SR
Output appears from the falling edge of K clock. SR DES SR SR
K DQC
tKHA
K
G#
tKLQX
tKLA
This outputmode was deleted.
DQC G#
tKHA tKLA tKLQZ tGLA tGHQ
DQ0-15
Q
DQ0-15
tGLQ
Q
Registered
DES SR
Output appears from the rising edge of K clock. SR SR DES SR SR SR
K DQC
tK tKHAR
K DQC G#
tKHQX tKHQZ tK tKHAR
G# DQ0-15 Q
tGLA
tKHQZ
tGHQ
DQ0-15
tGLQ
Q
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
tK tKH
K,K#
tKL tS tH tCMDH tCSH tRH tCH tDTH tCMSH tC0H tC1H tWH tDQCH tHADF tAH tDH
CMd#
tCMDS tCSS tRS tCS tDTS tCMSS tC0S tC1S tWS tDQCS tSADF tAS tDS
CS# RAS#
CAS# DTD# CMs# CC0#
CC1# WE# DQC(u / l) ADF#
Ad0-11 As0-9
DQ0-15 (Input)
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Load Byte Mask
Byte mask allocation during DWT3 and DWT4 Byte Mask Register Lower DQs
DQ0 DQ1
Upper DQs
DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Lower Upper
Block address
0
1
2
3
4
5
6
7
Column Block (16 byte)
0 : mask, no write 1 : unmask, write enable
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DWT3 / DWT4 Write data / Mask data
0 DRAM column 128 set
0 1 2 3 4 5 6 7 0 1 0 1 1 1 0 0
0 ---
DRAM row 1023
byte mask
written
Lower 8bit Upper8 bit
SRAM
WB1/WB2
Byte mask 255
lower byte Byte mask bit
upper byte
01011100 11111000 DQ0-> ->DQ15
Write / Mask logic
DWT2 DWT1
As0-2
addition DWT3/DWT4
DQCl DQCu
WM1
WM2
DQ0-15 Load Byte Mask (LBM)
SRAM
WB1
WB2
DRAM
DWT1/DWT3 DWT2/DWT4
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
21
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DWT3-DWT4 for Window clear(Block Write)
shadow clear / window clear
Window Boundary
Page boundary
ACT DNOP DWT3 DNOP DWT4 DNOP DWT4 DNOP DWT4 DNOP DWT4 PCG BWT DES LBM DES LBM DES DES DES DES DES LBM DES
Color data is transferred from WB2 to DRAM column block with new byte mask. Color data is transferred from WB2 to DRAM column block with byte mask. Color data is transferred from WB1 through WB2 to DRAM column block with byte mask, which is loaded by Load Byte Mask cycle(LBM). The byte mask data is valid from the LBM cycle immediately and lasts until the next LBM cycle is initiated. Color data is loaded from SRAM cache to WB1.(BWT) Page call.(ACT) (REV 1.0) Jul. 1998 22
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Burst Mode (1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs#
ADF#
CC0#
CC1# WE# DQC(u / l) As0-2
C1 C2 C3
Accept interrupt for inputting new address w/o gap.
As3-11 G# DQ0-15
C1
C2
C3
L
Q1 Q1+1 Q1+2 Q1+3
Q2 Q2+1
Q3 Q3+1 Q3+2 Q3+3
Q3
DES SR
SR
SR
SR
DES SR
SR
SR
SR
SR
SR
SR
SRAM address and DRAM address can be multiplexed using this duration for DRAM control
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
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16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Burst Mode (2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs#
ADF#
CC0#
CC1# WE# DQC(u / l) As0-2
C1 C2 C3 C4 C5 C6
As3-11 G# DQ0-15
C1
C2
C3
C4
C5
C6
L
Q1 Q1+1 D1+2
D2
Q3
Q4
Q5
Q6
DES SR
DES SR
SPD SPD DES SW SW
SR
SR
SR
SR
Burst address is not incremented by DES, SPD.
"Insert wait" is possible.
ADF#=Low is equal to non-burst mode.
M5M4V16169D keeps compatibility setting ADF# low or setting Burst length=1 by SCR cycle. (Ad7, Ad8 and Ad9=0) MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998 24
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
**-15 spec is the same as M5M4V16169TP/RT-15
ABSOLUTE MAXIMUM RATINGS (Ta=0~70C , Vdd=3.30.3V for -8,and -10, Vdd=3.30.15V for -7 Vss=0V, unless otherwise noted)
Symbol Vcc VI VO IO Pd Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Conditions With respect to Vss Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 1000 0 ~ 70 -65 ~ 150 Unit V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70C , Vdd=3.30.3V for -8,and -10, Vdd=3.30.15V for -7 Vss=0V, unless otherwise noted)
Symbol Vcc Vss VccQ VIH VIH VIH VIL
(LVTTL) (LVTTL) (LVTTL) (LVTTL)
Parameter Supply Voltage Supply Voltage Supply Voltage for Output High-level Input Voltage clock and add. High-level Input Voltage master clock (K) High-level Input Voltage data pin Low-level Input Voltage all inputs
Limits Min. 3.0 0 3.0 2.0 2.2 2.0 -0.3 Typ. 3.3 0 3.3 Max 3.6 0 3.6 Vdd+0.3 Vdd+0.3 VddQ+0.3 0.8 Unit V V V V V V V
CAPACITANCE (Ta=0~70C , Vdd=3.30.3V for -8,and -10, Vdd=3.30.15V for -7 Vss=0V, unless otherwise noted)
Symbol CI(A) CI(C) CI/O Parameter Input Capacitance, Address pin Input Capacitance, Clock pin Input Capacitance, I/O pin Test Condition V I=Vss f=1MHz V I =25mVrms Limits (MAX) 5 5 7 Unit pF pF pF
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(REV 1.0) Jul. 1998
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
**-15 spec is the same as M5M4V16169TP/RT-15
AVERAGE SUPPLY CURRENT from Vcc (Ta=0~70C , Vdd=3.30.3V for -8,and -10, Vdd=3.30.15V for -7 Vss=0V, unless otherwise noted)
Symbol IccS IccD IccD(PG) Condition
Average supply current of SRAM operating, tK=min. DRAM=DPD output open data input=H or L
Limits (MAX) -7 260 160 140 60 50 5 1 -8 240 150 130 60 50 5 1 -10 200 130 110 50 40 5 1 -15 140 100 80 30 25 5 1
Unit mA mA mA mA mA mA mA
Average supply current of DRAM operating, tRC=min. SRAM=SPD
Average supply current of DRAM page-mode tPC=min. SRAM=SPD LVTTL standby, tK=min, DRAM=DNOP&SRAM=DES, output open data input=H or L CMOS standby, tK=min, DRAM=DNOP&SRAM+DES, output open data input=H or L
Icc(STN1) or NOP all input=stable. Icc(STN2) or NOP all input=stable. Icc(PD) Icc(SRF)
CMOS Power Down current, CMd#=CMs#=L,tK=min. CMOS Self Refresh current, CMd#=CMs#=L,tK=
AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0~70C , Vdd=3.30.3V for -8,and -10, Vdd=3.30.15V for -7 Vss=0V, unless otherwise noted)
Symbol
VOH(DC)*(LVTTL) VOL(DC)*(LVTTL)
Parameter High-level Output Voltage (DC) Low-level Output Voltage (DC) Off-state Output Current Input Current
Test Condition IOH= -2mA IOL= 2mA
Q floating V O =0 ~VddQ
Limits Min. 2.4 -10 -10 Max 0.4 10 10
Unit V V uA uA
IOZ II
VIH =0 ~ VddQ+0.3V
* VOH(AC) and VOL(AC) are the reference levels for AC measurements. VOH(DC) and VOL(DC) are the final levels the outputs reach.
VTT 50ohm
VOUT 30pF
AC Condition
(Access Time)
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(REV 1.0) Jul. 1998
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16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
**-15 spec is the same as M5M4V16169TP/RT-15
TIMING REQUIREMENTS (CLK pulse, input signals setup / hold time to CLK edge) (Ta=0~70C , Vdd=3.30.3V for -8,and -10, Vdd=3.30.15V for -7 Vss=0V, unless otherwise noted) Input Pulse Levels: Input Timing Measurement Reference Level: VIH=3.0V,VIL=0.0V (LVTTL) 1.5V (LVTTL)
Limits Symbol tK tKH tKL tS tH Parameter Min. Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Setup Time for Inputs Hold Time for Inputs -7 Max Min. -8 Max -10 Min. Max -15 Min. Max Unit
7 3 3 3 1
8 3 3 3 1
10 3.5 4 3 1
15 5 5 4 1
ns ns ns ns ns
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(REV 1.0) Jul. 1998
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16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
**-15 spec is the same as M5M4V16169TP/RT-15
TIMING REQUIREMENTS (Read, Write, Refresh) (Ta=0~70C , Vdd=3.30.3V for -8,and -10, Vdd=3.30.15V for -7 Vss=0V, unless otherwise noted) Input Pulse Levels: Input Timing Measurement Reference Level: VIH=3.0V,VIL=0.0V (LVTTL) 1.5V (LVTTL)
Limits Symbol tREF tRP tRCD tRC* tWC* tPC tRAS tRASP tRWL tRSH Parameter Min. Refresh Cycle Time Precharge Time Delay Time, Add Strb. Row to Col. DRAM Activate-Read Cycle Time DRAM Activate-Write Cycle Time Page Cycle Time Activate Time Page mode Activate Time Write to Precharge Lead Time Read to Precharge Hold Time -7 Max Min. -8 Max -10 Min. Max -15 Min. Max Unit ms ns ns ns ns
12,000 100,000
64 21 21 70 70 14 49 49 14 14 24 24 80 80 16 56 56 16 16
64 30 30 90 90 20 60 60 20 20
64 40 30 120 120 30 70 70 20 20
64
10,000 100,000
10,000 100,000
10,000 100,000
ns ns ns ns ns
*Note: When tRP and tRAS = Min. values, tRC and tWC = tRP + tRAS.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
28
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
**-15 spec is the same as M5M4V16169TP/RT-15
SWITCHING CHARACTERISTICS (Ta=0~70C , Vdd=3.30.3V for -8,and -10, Vdd=3.30.15V for -7 Vss=0V, unless otherwise noted)
Limits Symbol Parameter Buffer-Fill from DRAM Read Transfer Access Time from K-High Edge Output Active Time from K-High Edge Output Disable Time from K-High Edge Access Time from K-High Edge Output Active Time from K-High Edge Output Disable Time from K-High Edge Access Time from G#-Low Edge Output Active Time from G#-Low Edge Output Disable Time from G#-High Edge
-7 Min. Max
-8 Min. Max
-10 Min. Max
-15 Min. Max
Unit
tCBF tKHA tKHQX tKHQZ tKHAR tKHQXR tKHQZR tGLA tGLQ tGHQ
20
20 2 2
20 10 10 7 10 7 8 3 3 12 3 3
20 15 5
ns ns ns ns ns ns ns ns ns ns
5.6 2 2 0 2 7 5.6 5.6 2 2 0 2
6.4 8 6.4 6.4 2 2 0 2
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
29
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
non-G# controlled Write & Read (DES control) ( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down )
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs#
CS# CC0#
CC1# WE# DQC(u / l) As0-2
C1 C2 C3 C4 C5 C6
As3-9 G# DQ0-15
C1
C2
C3
C4
C5
C6
L
D1
Q2
D3
Q4
D5
Q6
DES SW
SR
DES SW
SR
DES SW
SR
SPD SPD SPD DES
Note : Output is transparent. MITSUBISHI ELECTRIC
DRAM operation can be freely performed.
(REV 1.0) Jul. 1998 30
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
G# controlled Write & Read ( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down )
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs# CS# CC0#
H
L
CC1# WE# DQC(u / l)
C1 C2 C3 C4 C5 C6 C7
As0-2 As3-9 G#
C1
C2
C3
C4
C5
C6
C7
DQ0-15
D1
Q2 Q3
D4
Q5
Q6
Q7
DES
SW
SR
SPD
SPD SPD
DES
SR
SW
SR
SR
SR
DES
Note : Output is transparent. MITSUBISHI ELECTRIC
DRAM operation can be freely performed.
(REV 1.0) Jul. 1998 31
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DQC controlled Write & Read ( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down )
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs#
CS# CC0#
CC1# WE# DQCu DQCl As0-2
C1
C2
C3
C4
C5
C6
As3-9 G# DQ8-15
L
C1
C2
C3
C4
C5
C6
D1
Q2
D5
Q6
DQ0-7
D1
Q2
D3
Q4
DES SW
(u/l)
SR
(u/l)
DES SW
(l)
SR
(l)
DES SW
(u)
SR
(u)
SPD SPD SPD DES
H or L
Note : Output is transparent. MITSUBISHI ELECTRIC
DRAM operation can be freely performed.
(REV 1.0) Jul. 1998 32
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Registered Output control ( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down )
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs#
CS# CC0#
CC1# WE# DQC(u / l) As0-2
C1
C2
C3
C4
C5
C6
C7
C8
As3-9 G# DQ0-15
L
C1
C2
C3
C4
C5
C6
C7
C8
D1
D3
Q2
D5
Q4
D7
Q6
Q8
DES SW
SR
SW
SR
SW
SR
SW
SR DES SPD SPD DES
Note : Output is registered. MITSUBISHI ELECTRIC
DRAM operation can be freely performed.
(REV 1.0) Jul. 1998 33
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Buffer Read Transfer (RB2 -> SRAM) Buffer Read Transfer & SRAM Read (RB2 -> SRAM -> Output)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs# CS# CC0#
H
L
CC1# WE# DQC(u / l)
As0-2 As3-9 G#
C1
C2
C3
C4
C5
C6
C7
C8
(C1)
(C1)
(C1)
(C1)
(C1)
(C5)
(C5)
(C5)
(C5)
L
DQ0-15
DES BRT SR
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SR
SR
SR
BRTR SR
SR
SR
DES
DES DES
DES
Note : Output is transparent. MITSUBISHI ELECTRIC
DRAM operation can be freely performed.
(REV 1.0) Jul. 1998 34
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Buffer Write Transfer (SRAM -> WB1) Buffer Write Transfer & SRAM Write (Input -> SRAM -> WB1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs# CS# CC0#
H
L
CC1# WE# DQC(u / l)
C2
As0-2 As3-9 G#
C1
C2
C3
L
WB1(0-7)
old
D1
D2
D3
DQ0-15
DES DES BWT DES
D2
DES BWTW DES
DES
BWT
DES DES
DES DES
DES
Note : Output is transparent. MITSUBISHI ELECTRIC
DRAM operation can be freely performed.
(REV 1.0) Jul. 1998 35
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Buffer Write (Input -> WB1) Buffer Read (RB2 -> Output)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs# CS# CC0#
H
L
CC1# WE# DQC(u / l)
As0-2 As3-9 G# WB1(0-7) WB1 Mask(0-7)
C1
C2
C3
C4
C5
C6
C7
C8
L
D1
D2
D3
D4
D1
D2
D3
D4
DQ0-15
D1 BW
D2 BW
D3 BW
D4 BW DES DES DES DES BR
Q5 BR
Q6 BR
Q7 BR
Q8 DES DES
Note : Output is transparent. MITSUBISHI ELECTRIC
DRAM operation can be freely performed.
(REV 1.0) Jul. 1998 36
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
NO - Operation of SRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMs# CS#
H
CC0# CC1#
WE# DQC(U / l)
AS0-9
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NO-Operation Mode
CMd# RAS# CAS# DTD# Ad0-11 DRAM operation can be freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
37
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
NO - Operation of DRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
H
CS#
CMd#
RAS#
CAS#
DTD#
Ad0-11
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
NO-Operation Mode
CMs# CC0# CC1# WE# DQC(u/l) G# As0-9 DQ0-15 SRAM operation can be freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
38
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Power Down / DRAM Activate / DRAM Precharge
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd#
CS#
RAS# CAS#
DTD# Ad0-11
Row
DPD DPD DPD ACT
DNOP DNOP DNOP DNOP
PCG DPD DPD DPD DPD
CMs# CC0# CC1# WE# DQC(u/l) G# As0-9 DQ0-15 SRAM operation can be freely performed.
DPD is recommended during no operation to save power. MITSUBISHI ELECTRIC
39
(REV 1.0) Jul. 1998
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
RAS only Refresh cycle DRAM Power Down / DRAM Activate / DRAM Precharge
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K CMd#
CS#
tRC tRP tRAS
RAS# CAS#
DTD#
Ad0-11
Row
DPD PCG DPD DPD ACT
DNOP DNOP DNOP DNOP
PCG DPD DPD DPD
CMs# CC0# CC1# WE# DQC(u/l) G# As0-9 DQ0-15 SRAM operation can be freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
40
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Auto Refresh
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
H tRC H
CMd#
H
H
CS# RAS#
CAS# DTD#
Ad0-11
DPD DPD ARF DNOP DPD DPD DPD DPD DPD DPD ARF DNOP DNOP DNOP
CMs# CC0# CC1# WE# DQC(u/l) G# As0-9 DQ0-15
Note: DRAM must be in Precharge state prior to Auto-Refresh cycle. DRAM new commands except for NOP,DNOP and DPD can be set after tRC later from ARF command input.
SRAM operation can be freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
41
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Self Refresh
1 2 3 4 1 2 3 4 5 6
K
Inhibit falling edge.
CMd#
H
L
H
CS# RAS#
L
L
CAS# DTD#
L
H
Row
DNOP DNOP SRF Halt
Ad0-11
Halt
Halt DNOP DNOP DNOP DNOP ACT DNOP
tRC for Recovery
Self Refresh Mode SRAM Power Down Mode Self Refresh Entry
Self Refresh SRAM Power Down Exit
Self Refresh Entry: (Note: DRAM must be in Precharge state prior to Self-Refresh Entry) Previous CMd#=H, Present CMd#=L, CS#=RAS#=CAS#=L, DTD#=H (CMd# must remain low to maintain Self Refresh). Self Refresh Exit (in order): a) resume K clock b) CMd#=H c) Wait tRC for recovery d) Resume normal operation
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
42
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
tRC
CMd# CS#
tRP tRAS
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2
Row
Ad0-Ad2=Low
Ad3-11
Row
**Col
tCBF
RB1 RB2
DRAM SRAM
Old Data Latency x tK Old Data DPD DPD PCG DPD DPD DPD ACT BR Old BR BR Old BR BR Old BR BR Old
DNOP
New Data
New Data DRT BR Old
DNOP
PCG DPD DPD DPD BR BR BR BR
BR
BR
DQ0-15
Old
Old
Old
Old
New New New New New
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 43
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
tRC
CMd# CS#
tRP tRAS
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2 Ad3-9
Row
Ad0-Ad2=Low
Row
**Col
tCBF
RB1
Old Data Latency x tK
New Data
RB2
DRAM SRAM
Old Data DPD DPD PCG DPD DPD DPD ACT BR BR BR BR BR BR BR
DNOP
New Data DRT BR
DNOP
PCG DPD DPD DPD BR BR BR BR
BR
BR
DQ0-15
Old
Old
Old
Old
Old
Old
Old
Old
Old
Old New New New New
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 44
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
tRC
CMd# CS#
tRP tRAS
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2
Row
Ad0-Ad2=Low
Ad3-11
Row
**Col
tCBF
RB1
Old Data Latency x tK
New Data
RB2
DRAM SRAM
Old Data
New Data
DPD DPD PCG DPD DPD DPD ACT BR BR BR BR BR BR BR
DNOP
DRT BR
DNOP
PCG DPD DPD DPD BR BR BR BR
BR
BR
DQ0-15
Old
Old
Old
Old
Old
Old
Old
Old
Old
Old
Old New New New
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 45
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
tRC
CMd# CS#
tRP tRAS
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2
Row
Ad0-Ad2=Low
Ad3-11
Row
**Col
tCBF
RB1 RB2
Old Data Latency x tK Old Data
New Data
New Data
DRAM SRAM
DPD DPD PCG DPD DPD DPD ACT BR Old BR BR Old BR BR Old BR BR
DNOP
DRT BR Old
DNOP
PCG BR Old
DNOP
DPD DPD BR BR
BR
BR
BR
DQ0-15
Old
Old
Old
Old
Old
Old
Old New New
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 46
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer (Pipe-lined Page-Mode) Latency set=1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd# CS#
tRASP
RAS#
tPC tRCD tPC tPC tPC tPC tRSH
CAS#
DTD#
Ad0-2
Row
Ad0-Ad2=Low
Ad3-11
Row
**C1
**C2
**C3
**C4
**C5
**C6
tCBF
tCBF C1 C2
tCBF tCBF tCBF tCBF C3 C4 C5 C6
RB1
Old Data
Latency x tK Latency x tK
Latency Latency Latency Latency x tK x tK x tK x tK
RB2
DRAM SRAM
Old Data
C1
C2
C3
C4
C5
C6
DPD ACT BR BR
DNOP
DRT BR
DNOP
DRT BR
DNOP
DRT DRT DRT DRT BR BR BR BR
DNOP
PCG BR BR
BR
BR
BR
BR
DQ0-15
Old
Old
Old
Old
Q1
Q1
Q2
Q2
Q3
Q4
Q5
Q6
Q6
Q6
Pipe-lined Page mode
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 47
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd# CS#
tRASP
RAS#
tPC tRCD tPC tRSH
CAS#
DTD#
Ad0-2
Row
Ad0-Ad2=Low
Ad3-11
Row
**C1
**C2
**C3
**C4
**C5
**C6
tCBF
tCBF C1 C2 tCBF C1
tCBF tCBF tCBF tCBF C3 C4 C5 C6 tCBF C2 C6
DNOP
RB1
Old Data
tCBF
RB
DRAM SRAM
Old Data DPD ACT BR BR
DNOP
DRT BR
DNOP
DRT BR
DNOP
DRT DRT DRT DRT BR BR BR BR
PCG BR BR
BR
BR
BR
BR
DQ0-15
Old
Old
Old
Old
Old
Q1
Q1
Q2
Q2
Q2
Q2
Q2
Q6
Q6
If next DRT happens within the latency, new data does not transferred to RB. However this operation is not guaranteed. SRAM operation can be freely performed. ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 48
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd# CS#
tRASP
RAS#
tRCD tPC tPC tRSH
CAS#
DTD#
Ad0-2 Ad3-11
Row
Ad0-Ad2=Low
Row
**C1
**C2
**C3
**C4
tCBF
tCBF C1 C2 Latency x tK C1
tCBF tCBF C3 C4 Latency x tK C2
DNOP DNOP
RB1 RB2
DRAM SRAM
Old Data
Latency x tK Old Data DPD ACT BR BR
DNOP
C4
DNOP
DRT BR
DNOP DNOP
DRT BR
DRT DRT BR BR
PCG BR BR
BR
BR
BR
BR
BR
BR
DQ0-15
Old
Old
Old
Old
Old
Old
Q1
Q1
Q1
Q2
Q2
Q2
Q2
Q4
If next DRT happens within the latency, new data does not transferred to RB. However this operation is not guaranteed.
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 49
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd# CS#
tRASP
RAS#
tRCD tPC tRSH
CAS#
DTD#
Ad0-2 Ad3-11
Row
Ad0-Ad2=Low
Row
**C1
**C2
**C3
tCBF
tCBF C1 Latency x tK C2
tCBF C3 Latency x tK
RB RB
DRAM SRAM
Old Data
Old Data DPD ACT BR BR
DNOP
C1 DRT BR
DNOP DNOP DNOP
C3
DNOP
DRT BR
DRT BR
DNOP DNOP
PCG BR BR
BR
BR
BR
BR
BR
BR
BR
DQ0-15
Old
Old
Old
Old
Old
Old
Old
Q1
Q1
Q1
Q1
Q1
Q1
Q3
If next DRT happens within the latency, new data does not transferred to RB. However this operation is not guaranteed.
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 50
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write (DIN->WB1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
tRC
CMd# CS#
tRP tRAS
RAS#
tRCD tRWL
CAS#
DTD#
Ad0-2 Ad3-11
Row
Ad0-Ad2=Low
Row
**Col
WB2
Old Data
New Data[WB1(0-7)]
WB1
C0
C1
C2
C3
C4
C5
C6
C7
C0
C1
C2
C3
C4
DRAM SRAM
DPD DPD PCG DPD DPD DPD ACT DES BW BW BW BW BW BW
DNOP
DWT1 DNOP PCG DPD DPD DPD BW BW BW BW BW BW
BW
DQ0-15
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
Please refer to next page in detail.
SRAM operation can be freely performed. ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 51
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write (DIN->WB1)
detail
6 tRC 7 8 9 10 11 12 13 14
1
2
3
4
5
K CMd# CS#
tRP tRAS tRCD tRWL
RAS# CAS# DTD# Ad0-2 Ad3-11 WB2 [0-7] WB1[0] WB1 mask[0] WB1[1] WB1 mask[1] WB1[2] WB1 mask[2] WB1[3] WB1 masl[3] WB1[4] WB1 mask[4] WB1[5] WB1 mask[5] WB1[6] WB1 mask[6] WB1[7] WB1 mask[7]
DRAM SRAM 0 Row
Ad0-Ad2=Low
Row Old Data
**Col
New Data[from WB1(0-7)] 0
1
1
2
2
3
3
4
4
5
6
7
DPD DPD PCG DPD DPD DPD ACT DNOP DWT1 DNOP PCG DPD DPD DPD DES BW BW BW BW BW BW BW BW BW BW BW BW BW D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5
DQ0-15
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
52
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write Transfer (SRAM->WB1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
tRC
CMd#
CS#
tRP tRAS
RAS#
tRCD tRWL
CAS#
DTD#
Ad0-2
Row
Ad0-Ad2=Low
Ad3-11
Row
**Col
WB2
Old Data
New Data[WB1(0-7)]
WB1
Old Data
New Data
Next New Data
DRAM SRAM
DPD DPD PCG DPD DPD DPD ACT SW SW SW SW SW SW SW
DNOP
DWT1 DNOP PCG DPD DPD DPD BWT BWT SW SW SW SW
SW
DQ0-15
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
Please refer to next page in detail.
SRAM operation can be freely performed. ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 53
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write Transfer (SRAM->WB1)
detail
6 tRC 7 8 9 10 11 12 13 14
1
2
3
4
5
K CMd# CS#
tRP tRAS tRCD tRWL
RAS# CAS# DTD# Ad0-2 Ad3-11 WB2 [0-7] WB1[0] WB1 mask[0] WB1[1] WB1 mask[1] WB1[2] WB1 mask[2] WB1[3] WB1 masl[3] WB1[4] WB1 mask[4] WB1[5] WB1 mask[5] WB1[6] WB1 mask[6] WB1[7] WB1 mask[7]
DRAM SRAM Row
Ad0-Ad2=Low
Row Old Data
**Col
New Data[from WB1(0-7)] 0 0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
DPD DPD PCG DPD DPD DPD ACT DNOP DWT1 DNOP PCG DPD DPD DPD SW SW SW SW SW SW SW SW BWT BWT SW SW SW SW D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3
DQ0-15
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
54
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write (DIN->WB1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd# CS#
tRP tRASP tPC tRCD tRWL
RAS#
CAS#
DTD#
Ad0-2
Row
Ad0-Ad2=Low Ad0-Ad2=Low
Ad3-11
Row
**Col
**Col
WB2
C2
Old Data
New Data[WB1(0-7)]
Next Data[WB1(0-1)]
WB1
C0
C1
C3
C4
C5
C6
C7
C0
C1
C2
C3
C4
DRAM SRAM
DPD DPD PCG DPD DPD DPD ACT DES BW BW BW BW BW BW
DNOP
DWT1 DNOP DWT1 BW BW BW
DNOP PCG
DPD BW
BW
BW
BW
DQ0-15
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
Please refer to next page in detail.
SRAM operation can be freely performed. ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 55
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Page-Mode DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write (DIN->WB1)
detail
8 9 10 11 12 13 14
1
2
3
4
5
6
7
K CMd# CS#
tRP tRASP tRCD tPC tRWL
RAS# CAS# DTD# Ad0-2 Ad3-11 WB2 [0-7] WB1[0] WB1 mask[0] WB1[1] WB1 mask[1] WB1[2] WB1 mask[2] WB1[3] WB1 masl[3] WB1[4] WB1 mask[4] WB1[5] WB1 mask[5] WB1[6] WB1 mask[6] WB1[7] WB1 mask[7]
DRAM SRAM DPD DPD PCG DPD DPD DPD ACT DES BW BW BW BW BW BW 0 1 2 3 4 5 6
DNOP
Row
Ad0-Ad2=Low Ad0-Ad2=Low
Row Old Data 0
**Col
**Col
New Data [from WB1(0-7)]
Next Data[WB1(0-1)]
0
1
1
2
2
3
3
4
4
5
6
7
DWT1 DNOP DWT1 DNOP PCG DPD BW BW BW BW BW BW BW 7 0 1 2 3 4 5
DQ0-15
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
56
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 1&Read (WB1->WB2->DRAM->RB) Latency set=1 Buffer Write (DIN->WB1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
tRC
CMd# CS#
tRP tRAS
RAS#
tRCD tRWL
CAS#
DTD#
Ad0=High
Ad0-2 Ad3-11
Row
Ad1-Ad2=Low
Row
**Col
WB2
Old Data
New Data[WB1(0-7)]
WB1
0
1
2
3 tCBF
4
5
6
7 tCBF
0
1
2
3
4
RB1 RB2
DRAM SRAM
Old Data tCBF Old Data DPD DPD PCG DPD DPD DPD ACT DES BW BW BW BW BW BW 0 1 2 3 4 5 6 Latency x tK
New Data[WB1(0-7)]
New Data[WB1(0-7)]
DNOP DWT1R DNOP
BW 7
BW 0
BW 1
PCG DPD DPD DPD BW BW BW BW 2 3 4 5
DQ0-15
New Data on RB appears as to latency set count. See DRT timing chart. SRAM operation can be freely performed. ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 57
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer 2 (WB2->DRAM)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd# CS#
tRP tRASP tPC tRCD tRWL
RAS#
CAS#
DTD#
Ad1=High
Ad0-2 Ad3-11
Row
Ad0-Ad2=Low Ad0,Ad2=Low
Row
**Col
**Col
NoChange
WB2
Old Data
New Data[WB1(0-7)]
WB1
0
1
2
3
4
5
6
7
0
1
2
3
4
DRAM SRAM
DPD DPD PCG DPD DPD DPD ACT DES BW BW BW BW BW BW
DNOP DWT1 DNOP DWT2 DNOP PCG
DPD BW
BW
BW
BW
BW
BW
BW
DQ0-15
0
1
2
3
4
5
6
7
0
1
2
3
4
5
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 58
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
DRAM Write Transfer2 & Read (WB2->DRAM->RB1-> RB2) Latency set=1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd# CS#
tRP tRASP tPC tRCD tRWL
RAS#
CAS#
DTD#
Ad0,Ad1=High
Ad0-2
Row
Ad0-Ad2=Low Ad2=Low
Ad3-11
Row
**Col
**Col
NoChange
WB2
Old Data
New Data[WB1(0-7)]
WB1
0
1
2
3
4
5
6
7
0
1 tCBF
2
3
4
RB1 RB1
DRAM SRAM
Old Data
New Data[WB1(0-7)] Latency x tK
Old Data DPD DPD PCG DPD DPD DPD ACT DES BW 0 1 BW 2 BW 3 BW 4 BW 5 BW 6
New Data[WB1(0-7)]
DNOP DWT1 DNOP DWT2 DNOP
PCG DPD BW BW 4 5
BW 7
BW 0
BW 1
BW 2
BW 3
DQ0-15
New Data on RB appears as to latency set count. See DRT timing chart. SRAM operation can be freely performed. ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 59
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
This page is left blank, so that the Set Command Register Timing Diagram on the next spread can be seen conveniently.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
60
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Set Command Register (1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
CMd#
CS# RAS#
CAS# DTD#
Ad0-11
CMD DPD DPD DPD DPD DPD DPD
Row
SCR DPD DPD DPD ACT DNOP DNOP DNOP
*Set Command Reg.
Inhibit new command except for DNOP,DPD DES,SPD and NOP.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
61
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Set Command Register(2)
Address Input
Ad11 Ad10 Ad9
L
L L L L L L L L L L L L L L L L L L
Command Ad3 Ad2 Ad1 Ad0
L
L L L L H L H L L L L L L L L L L L L L L L L L
Ad8 Ad7 Ad6 Ad5 Ad4
L L L L L L L L L L L L L H H L H L H L L L L L L L L L L H H L H L H
L
L L L L L L L L L L L L L L L L L L L H
L
H
No operation Set All WB1 Xfer Masks Default Output ModeTransparent Output Mode Latched Output Mode Registered
Latency 1 Latency 2 Latency 3 Latency 4 Default BL=1 BL=2 BL=4 BL=8 Sequential Interleave
Default Default
K CMd#
CS# RAS#
CAS# DTD# Ad0~11
Command
* Latency is the number of clock cycles required to transfer new data from the DRAM to the Read Buffer . Therefore, it can be adjusted to the clock frequency of the system. (Latency) x (tK) should meet tCBF min. timing requirement.
SCR
Inhibit new read or write function during these 4 clocks. MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998 62
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Burst Mode Address
Initial Address BL As2 As1 As0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 1 2 1 0 1 0 Y0 0 1 2 3 4 5 6 7 0 1 2 3 0 Y1 1 2 3 4 5 6 7 0 1 2 3 0 1 Y2 2 3 4 5 6 7 0 1 2 3 0 1 Y3 3 4 5 6 7 0 1 2 3 0 1 2 Y4 4 5 6 7 0 1 2 3 Y5 5 6 7 0 1 2 3 4 Y6 6 7 0 1 2 3 4 5 Y7 7 0 1 2 3 4 5 6 Y0 0 1 2 3 4 5 6 7 0 1 2 3 0 Y1 1 0 3 2 5 4 7 6 1 0 3 2 1 Y2 2 3 0 1 6 7 4 5 2 3 0 1 Y3 3 2 1 0 7 6 5 4 3 2 1 0 Y4 4 5 6 7 0 1 2 3 Y5 5 4 7 6 1 0 3 2 Y6 6 7 4 5 2 3 0 1 Y7 7 6 5 4 3 2 1 0 Sequential Interleaved
Note: When SRAM command is executed more than burst length, the Address repeats with the same sequence.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
63
MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
70P3S Package Dimension
70 36
A
70P3S-L
1 1
35 35
0.125 +0.05 -0.02
+0.02 (0.005 -0.0008 )
70P3S-M
0.5+-0.1 (0.02+-0.004) Detail A 70 0.65+-0.1 (0.026+-0.004)
*2 23.49+-0.1 UNIT : mm (INCH)
*3
0.3
+0.1 -0.05 +0.004 -0.05
36 )
(0.012
(0.925+-0.004)
0.1 (0.004)
Note)
Dimension *1, *2 do not include mold flash. Dimension *3 does not include tie - bar cut remain.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
64

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