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HD66137T
High-Voltage Durable 240-Channel Common Driver for Dot-Matrix STN LCD
ADE-207-291(Z) Rev. 2 Aug. 03, 1999 Description
The HD 66137T is a 240-channel common driver which drives a dot matrix STN LCD panel. By changing the mode, this can be applied to 240- and 200- and 160- channel output. Through the use of a 43-V highvoltage CMOS process technology, a high-voltage drive of +21.5 V and -21.5 V, centering on VM is possible. -21.5V generated from +21.5 V with built-in switching circuit and external capacity. Low logicdrive voltage (3 V) is used. This device is used together with the segment driver HD66130, HD66134ST or HD66136.
Features
* * * * * * * * Display duty: Up to 1/240 LCD drive voltage: 43 V max Built-in switching circuit (to generate -21.5 V) Number of LCD drive circuit: 240 Operating voltage: 2.5 to 5.5 V Intermediate voltage I/F Built-in alternating signal generation circuit Pin programmable Output mode change: 240-output mode 200-output mode 160-output mode * Built-in display-off function * Flex TCP
1
2 1 2 3 4 5 X1 X2 X3 X4 X5 Top view Note: The shape above does not indicate the actual outline. 236 237 238 239 240 X236 X237 X238 X239 X240 VLCDL VHL VML VLL VEEL VEO C1 C2 DIO2 M RESET MWS4 MWS3 MWS2 MWS1 MWS0 VCC MODE1 MODE0 DOC DISPOFF AMP SHL GND CL CCL M/S DIO1 VEER VLR VMR VHR VLCDR 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241
HD66137T
Pin Arrangement
HD66137T
Block Diagram
X1--X240 *2, *3 VHL VLL VML *1, *3 VLCDL,R VEEL,R VCC GND
Shift register D Q SR SR 1 20 Q D Shift register D Q SR SR 21 40 Q D
LCD drive circuit Level shifter
VHR VLR VMR
Level shifter
Logic
Logic
Logic
Logic
Logic
Shift register D Q SR SR 41 200 Q D
Shift register D Q SR SR 201 220 Q D
Shift register D Q SR SR 221 240 Q D
DISPOFF
Logic
M/S
Switch circuit
Logic
Alternating signal generating circuit
DIO1 DIO2 SHL MODE0 MODE1
CL
VEO CCL AMP C2 C1
M
*1 VLCDL and VLCDR, and VEEL and VEER are internally connected. *2 VHL and VHR, VLL and VLR, and VML and VMR are internally connected.
DOC
MWS 0 to MWS 4
RESET
Logic
3
HD66137T
Internal Block Diagram
1. LCD drive Circuit This circuit selects and outputs the three level signals for the LCD drive. By a combination of the data in the shift register and M, either VH, VL, or VM is selected and transmitted to the output circuit. 2. Level shifter This boosts a 5-V signal to a high-voltage signal for LCD drive. 3. Shift register This is a 240-bit bidirectional shift register circuit. The first line marker signal output from the DIO1 pin and DIO2 pin is sequentially shifted by shift clock CL. The shift direction is determined by the SHL pin. 4. Alternating signal generating circuit This circuit generates an alternating signal (M signal) for LCD display. To suppress cross-talk, the signal is alternated in a unit from several lines to several tens of lines. By connecting MWS0 to MWS4 pins to VCC or GND, the desired number of signals can be alternated. When alternating signals are externally input, all pins (MWS0 to MWS4) are connected to GND.
HIFAS Family timing Comparison HD66130/131S/134S/135/136 CL1 M HD66132/133
Input signal
Output signal
Segment Common
4
HD66137T
Pin Function
Classification Power supply Symbol VLCDL, R VEEL, R VCC, GND VHL, R VLL, R VML, R Connected Pin No. to 273, 241 Power 269, 245 supply 257 250 272, 242 Power 270, 244 supply 271, 243 I/O -- Functions VLCDL, R-VEEL, R : Power supply for LCD drive VLCDL, R : Power supply for switch circuit VCC-GND : Power supply for logic circuit Power supply for LCD drive level VHL, R : Selected level (Set to the same voltage as VLCDL, R.) VLL, R : Selected level (Set to the same voltage as VEEL, R.) VML, R : Non-selected level and Power supply for switch circuit output When use built -in switching circuit and generate VEE, VEO pin connect to VEEL, R pins. VM voltage is point of reference and reversed and output the voltage input to the voltage between VLCD and VM. If built-in switching circuit is not used, don't connect any lines to this pin. External capacitance should be connected here when using the switch circuit for generate VEE. If built-in switching circuit is not used, don't connect any lines to this pin. Shift clock input. Data is shifted at the falling edge of shift clock CL of the shift register. Inputs or outputs the alternating current for LCD drive output. This pin specifies the cycle of the alternating signal (M signal) in the unit of the number of lines. The number of lines, which is an integer from 2 to 31, is specified as follows. Usually, specify the number of lines within a range from 10 to 31. When the HD66131T is driven by an external alternating signal, specify the number of lines as zero.
Number MWS4 MWS3 MWS2 MWS1 MWS0 of lines 0 0 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 * * * * * * * * * * * * 1 31 1 1 1 1 Line alternating M-pin status waveform ---- Input Prohibited Output 2 lines alternated 3 lines alternated * * 31 lines alternated
Input
VEO
268
VEEL, R
C1, C2
267, 266 Capacitance --
Control signal
CL M
249 264
MPU Extension driver or MPU --
Input I/O
MWS0 MWS1 MWS2 MWS3 MWS4
258 259 260 261 262
Input
5
HD66137T
Pin Functions (cont)
Classification Control signal Symbol MODE0 MODE1 Connected Pin No. to 256 256 -- I/O Input Function Switch terminals for the number of LCD drive output pins.
MODE0 MODE1 Shift direction "H" "H" 240 - output (X1, X2, X3......X238, X239, X240) "H" "L" 200 - output (X21, X22, X23......X218, X219, X220) "L" "H" 160 - output (X41, X42, X43......X198, X199, X200) "L" "L" Prohibited
DIO1 DIO2
246 265
Extension driver or MPU MPU
I/O
Serial data input output pin
SHL "H" level "L" level DIO1 serial output pin seiral input pin DIO2 serial input pin seiral output pin
CCL
248
Input
Built-in switching circuit clock input. When use built-in switching circuit and generate VEE, this pin connect CL pin. If built-in switching circuit is not used, CCL must be fixed to GND Built-in swiching circuit on-off control. When use built-in switching circuit, this pin must be fixed to VCC. If built-in switching circuit is not used, this pin must be fixed to GND Setting this pin to GND sets initializes the alternating signal (M signal) circuit. A VCC level RESET is normally used. Setting this pin to GND sets LCD drive output X1 to X240 to the VM level. Controls the display-off function, and displayoff signal output from DOC pin.
"H" level When DISPOFF is Low level, X1-240 set VM level "L" level Until serial data input 16 times X1-X240 set VM level
AMP
252
--
Input
RESET
263
MPU or VCC
Input
DISPOFF 253 M/S 247
MPU --
Input Input
DOC
254
--
Output
"H" level When DISPOFF is Low level, output low level When DISPOFF is High level, output High level "L" level Until serial data input 16 times output low level from DOC pin
DISPOFF DIO1,2 DOC 12345 141516
When using M/S is low level, DOC pin should be connect to SEG LSI Dispoff control pin.
6
HD66137T
Pin Functions (cont)
Classification Control signal Symbol SHL Connected Pin No. to 251 -- I/O Input Function This pin switches shift directions.
SHL "H" level MODE0 MODE1 "H" "H" "L" "H" "H" "L" "H" "L" "H" "H" "L" "H" Shift direction Right shift DIO2SR1********SR240DIO1 DIO2SR21********SR220DIO1 DIO2SR41********SR200DIO1 Left shift DIO1SR240********SR1DIO2 DIO1SR220********SR21DIO2 DIO1SR200********SR41DIO2
"L" level
SR1, SR2***SR240 correspond to X1, X2***X240. Note: The 40 or 80 pins invalidated at the 200-output or 160-output mode output the non-selected level synchronized every time; release these pins. LCD drive output X1 to X240 1 to 240 LCD Output LCD drive output By a combination of the display data and the M signal, when DISPOFF is set to VCC, either VH, VL, or VM is selected and transmitted to the output circuit.
M D Output level 1 VL 1 0 VM 1 VH 0 0 VM
Note: Configuring the LCD panel using the HD66137 when using the select SEGMENT driver.
The Select SEGMENT driver
SEGMENT driver HD66130 (320 OUT) HD66132 (240 OUT) HD66134S (240 OUT) HD66136 (400 OUT) Select q x q q
7
HD66137T
Application Example
Application Example (1) Figure 1 shows an application example 640 x 3 (collar) x 240 dot Half VGA Size STN color panel. This panel configured HD66137 x 1 piece and HD66136 x 5 pieces. HD66137 generates M signal and DOC signal. M signal pin is connected M signal pin of HD66136 and DOC signal pin is connected DISP signal pin of HD66136. HD66137 is able to generates - voltage by external capacitor. VEO pin is connected VEE pin and VL pin.
CA
VLCD V0 V0S VCC VM V1S V1 GND
seg1 seg2 seg3
-
Y384~Y1
SHL EIO2 MODE GND VCC SHL
Y384~Y1 HD66136 (No.2)
SHL EIO1 EIO2 MODE GND Vcc
Y384~Y1 HD66136 (No.5)
HD66136 (No.1)
EIO1
EIO2 MODE GND VCC
Controller
Notes : 1. When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about 0.1F for each IC (between Vcc and GND, V0 and GND, VLCD and GND, and VEE and GND). 2. In addition, for the power supply circuit, connect a capacitor of several F or several tens of F between the liquid-crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid-crystal drive power supply and level power supply in the period between when the liquid-crystal drive power supply is turned on and when it is turned off. 3. When using external capacitor to generate VEE, you must connect a capaciter of several F or several tens of F between the VEE and GND.
Figure 1 Application Example (1)
8
seg1918 seg1919 seg1920
C0 +
CL CCL RESET DISPOFF AMP M/S DOC M NWS0~4 VHL, R VML, R VLL, R C1 C2
com1 com2 com3
SHL DIO1 VLCDL,R GND VEEL,R VEO VCC
LCD panel 640 x 3 (collar) x 240 1/240duty
com238 com239 com240
HD66137
DIO2 CC1~4 revised signal VM generate circuit
X1~X240
Power supply circuit
EIO1
CC1~4 M CL1 CL2 D0~11 BS DISP VML, R V1SL,R V1L, R V0SL,R V0L, R
CC1~4 M CL1 CL2 D0~11 BS DISP VML, R V1SL,R V1L, R V0SL,R V0L, R
CC1~4 M CL1 CL2 D0~11 BS DISP VML, R V1SL,R V1L, R V0SL,R V0L, R
MWS0~4
DISP FLM
CL2 D0~11
CL1
HD66137T
Application Example (2) Figure 2 shows an application example 320 x 3 (collar) x 240 dot Quarter VGA Size STN color panel. This panel configured HD66137 x 1 piece and HD66130 x 3 pieces. HD66137 generates M signal and DOC signal. M signal pin is connected M signal pin of HD66130 and DOC signal pin is connected DISP signal pin of HD66136. HD66137 is able to generates - voltage by external capacitor. VEO pin is connected VEE pin and VL pin.
CA
VLCD V0 VCC VM V1 GND
Y320~Y1
SHL EIO2 MODE GND VCC SHL
Y320~Y1 HD66130 (No.2)
V1L, R
SHL EIO1 EIO2 MODE GND
Y320~Y1 HD66130 (No.3)
V1L, R
HD66130 (No.1)
V1L, R
EIO1
EIO2 MODE GND VCC
VCC
Controller
Notes : 1. When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about 0.1F for each IC (between Vcc and GND, V0 and GND, VLCD and GND, and VEE and GND). 2. In addition, for the power supply circuit, connect a capacitor of several F or several tens of F between the liquid-crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid-crystal drive power supply and level power supply in the period between when the liquid-crystal drive power supply is turned on and when it is turned off. 3. When useing external capacitor to generate VEE, you must connect a capacitor of several F or several tens of F between the VEE and GND.
Figure 2 Application Example (2)
seg958 seg959 seg960
EIO1
seg1 seg2 seg3
C0 + -
CL CCL RESET DISPOFF AMP M/S DOC M NWS0~4 VHL, R VML, R VLL, R C1 C2
com1 com2 com3
SHL DIO1 VLCDL,R GND VEEL,R VEO VCC
LCD panel 320 x 3 (collar) x 240 1/240duty
com238 com239 com240
HD66137
DIO2
X1~X240
Power supply circuit
M CL1 CL2 D0~7 BS DISP VML, R
M CL1 CL2 D0~7 BS DISP VML, R
M CL1 CL2 D0~7 BS DISP VML, R
V0L, R
V0L, R
V0L, R
CL1 CL2 D0~7 DISP FLM NWS0~4
9
HD66137T
Power Supply Circuit Example
Figure 3 shows a power supply circuit example.
+21.0V
VLCD VH
DC-DC CONVERTER +3.0~5.0V +2.7~5.5V
- +
VCC V0 VM SEG Driver COM Driver
HD66137
GND
V1 GND
+
-
External Capacitor (2.2~4.7 F)
VEO VL VEE C1 C2
+ -
C0 External Capacitor (2.2~4.7 F)
Figure 3 Power Supply Circuit Example
10
HD66137T
Absolute Maximum Rating
Item Power supply Logic circuit voltage LCD drive circuit Symbol VCC VLCD VEE Input voltage (1) Input voltage (2) Input voltage (3) Input voltage (4) Operating temperature Storage temperature VT1 VH VL VM Topr Tstg Ratings -0.3 to +7.0 -0.3 to +25.0 -20.0 to +0.3 -0.3 to VCC + 0.3 -0.3 to VLCD +0.3 to VEE -0.3 to + 5.0 -30 to +75 -55 to +110 Unit V V V V V V V C C Notes 1, 8 1, 3, 8 1, 4, 8 1, 2 1, 5, 8 1, 6, 8 1, 7, 8
Notes: 1. Voltage from GND. 2. Applicable to DIO1, DISPOFF, SHL, M, NWS0, NWS1, NWS2, NWS3, NWS4, RESET, MODE0, MODE1, CL, M/S, AMP, CCL, DIO2. 3. Applicable to VLCDL, R pins. 4. Applicable to VEEL, R pins. 5. Applicable to VHL, R pins. 6. Applicable to VLL , R pins. 7. Applicable to VML, R pins. (Caution) Operating the LSI in excess of the absolute maximum rating will result in permanent damage. Use the LSI observing electrical characteristic conditions in normal operation. Exceeding the conditions will cause malfunctions or will affect LSI reliability. 8. Observe the sequence of activation and inactivation for the following power supplies and signals. And this sequence apply to use built - in switching circuit. If the sequence is not observed, it may cause LSI malfunction, permanent damage, or adverse effects.
11
HD66137T
VCC
2.5V 0ms 2.5V
VLCD, VH
0ms 0ms
VM
VEE,VL
0ms 0ms
0ms
DISPOFF
0ms
Input signal, clock, or data Undefined Initialization (Longer than one frame)
8.1 Power on (1) Turn on the power supply in the order of GND- V CC, GND-VLCD (VH), and VM. VM-VEE is generated automatically. In this case, input GND to the DISPOFF pin. (2) The LCD level forcibely outputs the VM level by the DISPOFF function. (3) The DISPOFF function has a priority even if input signal distortion occurs immediately after V CC input. (4) Then input the predetermined signals to initialize the driver registers. In this case, assure a period for more than one frame. (5) Preparation for normal display is thus completed. Cancel the DISPOFF function by setting the DISPOFF pin to VCC. At this point, the levels of VEE (VL), VLCD (VH) and VM must have reached the predetermined respective voltage. 8.2 Shut down As a rule, shut down in order opposite to that used for power on. (1) Set the DISPOFF pin to GND. (2) At first shut off the LCD power supply GND-VLCD (VH), at same time GND-VEE (VL) get to VM. Next shut off the VM. (3) Set VCC and the input signal to GND. At this point, VEE (VL), VLCD (VH) and VM pin input must completely drop to 0 V. Since the DISPOFF function is inactivated when the VCC level drops to GND, the LCD output may output a level other than VM. Therefore, an incorrect display may appear at shut down or power on.
12
HD66137T
Electrical Characteristics
DC Characteristics (VCC = 2.5 to 5.5 V, GND = 0 V, VLCD-VEE = 15 to 43 V, Ta = -30 to +75 C)
Item Symbol Applicable Pins
DIO1, DISPOFF, SHL, M, M/S, MWS0~4, RESET, CL, MODE0, MODE1, DOC, AMP, CCL, DIO2
Min.
0.7 x VCC
Typ. Max. --
VCC
Unit V
Measurement Conditions
Notes
Input high-level VIH voltage Input low-level voltage Output highlevel voltage Output lowlevel voltage ON resistance between Vi-Yj Input leak current (1) VIL
0
--
0.3 x VCC
V
VOH VOL RON I IL1
M, DOC, DIO1, DIO2 M, DOC, DIO1, DIO2
X1 to X240, V pin DIO1, DISPOFF, SHL, M, M/S, MWS0~4, RESET, CL, MODE0, MODE1, DOC, AMP, CCL, DIO2
VCC - 0.4
-- -- 0.7 --
-- 0.4 2.0 5
V V k A
I OH = -0.4 mA I OL = 0.4 mA I ON = 150 A VIN = VCC to GND 1
-- -- -5
Input leak current (2)
Current consumption (1)
I IL2 I CC1
VH, VL, VM, C1, C2 VCC
-25
-- 10
25 40
A A VCC = 3.3 V, VLCD-VEE = 40 V, f CL = 19.2 kHz, f M = 1.5 kHz VCC = 5.0 V, VLCD-VEE = 40 V, f CL = 19.2 kHz, f M = 1.5 kHz VCC = 3.3 V, VLCD-VEE = 40 V, f CL = 19.2 kHz, f M = 1.5 kHz 2
--
Current consumption (2)
I CC2
VCC
--
20
50
A
Current consumption (3)
I LCD
VLCD
--
25
50
A
Notes: 1. This is a resistance value between the X and V pins (either of VH, VL, or VM) when a load current is applied to one of x1 to x240 pins. These values are regulated under the conditions of VLCD = VH = 21.75 V, VEE = VL = -18.5 V, VM = 1.75 V, GND = 0 V, Use VH, VL, and VM in the range of VLCD - VMVH - VM = 21.5 to 7.5 V, VEE - VMVL - VM = -21.5 to -7.5 V, with the relation of VH > VM > VL. 2. The current applied between the input and output is excluded. When an input to a CMOS gate is at an intermediate level, through current flows between the power supplies, and the power supply current increases. Therefore, use VIH = VCC and VIL = GND. 3. The voltage relationship of each signal is as follows :
13
HD66137T
Segment voltage Segment waveform Common waveform Common voltage VH (23.0 V)
V0
(5.0V) VCC (3.3 V) VM (3.0 V)
VCC (3.3V) VM (3.0V) V1 (1.0V) GND (0.0V)
GND (0.0 V)
VL (-17.0 V) Normal display period Off-display period Normal display period Off-display period
AC Characteristics (1) (V CC = 2.5 to 5.5 V, GND = 0 V, VLCD-VEE = 15 to 43 V, Ta = -30 to +75 C)
Item Clock cycle time CL high-level width CL low-level width CL rising time CL falling time Data set-up time Data hold time Data output delay time M output delay time M set-up time M Hold time DOC delay time 1 DOC delay time 2 Symbol t CYC t CWH t CWL tr tf t DS t DH t DD t MD t MS t MH t DOC1 t DOC2 Pin Name
CL
min.
400
max. -- -- -- 30 30 -- -- 200 200 -- -- 300 300
Dimensions ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
CL CL CL CL DIO1, DIO2, CL DIO1, DIO2, CL DIO1, DIO2, CL M, CL M, CL M, CL DISPOFF, DOC DIO1, DIO2, DOC
25 370 -- -- 100 10 -- -- 20 20 -- --
1 1
2 2
14
HD66137T
AC Characteristics (2) (V CC = 2.5 to 4.5 V, GND = 0 V, VLCD-VEE = 43 V, Ta = -30 to +75 C)
Item Output delay time1 Symbol t pd1 Pin Name
X(n), M
min.
--
max. 1.2
Dimensions s
Note 2
AC Characteristics (3) (V CC = 4.5 to 5.5 V, GND = 0 V, VLCD-VEE = 43 V, Ta = -30 to +75 C)
Item Output delay time1 Symbol t pd1 Pin Name
X(n), M
min.
--
max. 0.7
Dimensions s
Note 2
*1, *2. The following timing is regulated with the circuit at the right connected.
test point *1: 30pF *2: 100pF
15
HD66137T
tf
0.7 x VCC
tCWL
tr
tCWH
tCYC
CL
0.3 x VCC
tDS
tDH
DIO1 DIO2
tDD
0.7 x VCC 0.3 x VCC
DIO1 DIO2
tMD
VOH VOL
M (During output)
VOH VOL
tpd1
0.7 x VH
X (n)
0.3 x VH 0.3 x VL 0.7 x VL
0.7 x VCC
CL
tMS
0.7 x VCC 0.3 x VCC
0.3 x VCC
tMH
0.7 x VCC 0.3 x VCC
M (During input)
DISPOFF
0.3 x VCC
DIO1 DIO2 (During input)
tDOC1
0.3 x VCC
tDOC2
0.7 x VCC 0.3 x VCC
DOC
16
HD66137T
Terminal Configuration
Terminal Configuration (1)
VCC VLCD
I
Input Data
I
VM Level
GND Input Terminal 1 Applicable terminals : CL, CCL, SHL, MODE0,1, AMP DISPOFF, RESET, MWS0~4, M/S VLCD
VEE Input Terminal 2 Applicable terminals : VMR, L
* VMR terminal connect with VML terminal in LSI.
VLCD
I
VH Level
I
VL Level
VEE Input Terminal 3 Applicable terminals : VHR, L
* VHR terminal connect with VHL terminal in LSI.
VEE Input Terminal 4 Applicable terminals : VLR, L
* VLR terminal connect with VLL terminal in SLI.
O
Output Terminal 1 Applicable terminals : DOC
17
HD66137T
Terminal Configuration (2)
VCC
Input Data VCC GND Data
Output enable GND I/O Terminal 1 Applicable terminals : DIO1, DIO2, M, VLCD VLCD VLCD VM VEE VLCD VLCD VM
I/O
I/O
VEE
VEE VLCD I/O Terminal 2 Applicable terminals : C1 VH VM
VEE
VEE VEE I/O Terminal 3 Applicable terminals : C2 VM
VLCD
VM VLCD
O
VEE
VEE VL VM
LCD drive Output Terminal Applicable terminals : X1 to X240
18
HD66137T
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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