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1 CHIP CODEC
S5T8554B/7B
INTRODUCTION
16-CERDIP The S5T8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM) system. These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used at the analog termination of a PCM line or trunk. These devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information.
16-DIP-300A
8-DIP-300
FEATURES
* * * * * * * Complete CODEC and filtering system Meets or exceeds AT&T D3/D4 and CCITT specifications -Law: S5T8554B, A-Law: S5T8557B On-chip auto zero, sample and hold, and precision voltage references Low power dissipation: 60mW (operating), 3mW (standby) 5V operation TTL or CMOS compatible Automatic power down
ORDERING INFORMATION
Device S5T8554B02-L0B0 S5T8557B02-L0B0 S5T8554B01-D0B0 S5T8557B01-D0B0 S5T8554B01-S0B0 S5T8557B01-S0B0 Package 16-CERDIP 16-DIP-300A 16-SOP-BD300 Operating Temperature -25C to 125C -25C to +70C -25C to +70C
1
S5T8554B/7B
1 CHIP CODEC
PIN CONFIGURATION
V BB GNDA VFRO V CC FSR DR BCLKR/CLKSEL MCLKR/PDN
1 2 3 4 5 6 7 8
16 VFXI+ 15 VFXI14 GSX 13 TSX 12 FSXS 11 DX 10 BCLKX 9 MCLK X
S5T8554B/7B
KT8554/7
PIN DISCRIPTION
Pin No 1 2 3 4 5 6 7 Symbol VBB GNDA VFRO VCC FSR DR BLCKR/ CLKSEL MCLKR/ PDN MCLKX BLCKX DX FSX TSX GSX VFXI
-
Description VBB = -5V 5% Analog ground. Analog output of the receive power Amp. VCC = +5 V 5% Receive frame sync pulse. 8kHz pulse train PCM data input. Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in normal operation and BCLKX is used for both TX and RX directions. Alternately direct clock input available, vary from 60kHz to 2.048MHz. When MCLK R is connected continuously high, the device is powered down. Normally connected continuously low, MCLKX is selected for all DAC timing. Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available. Must be 1.536MHz/1.544MHz or 2.048MHz. May be vary from 64kHz to 2.048MHz but BCLKX is externally tied with MCLKX in normal operation. PCM data output. TX frame sync pulse. 8kHz pulse train. Changed from high to low during the encoder timeslot. Open drain output. Analog output of the TX input amplifier. Used to set gain through external resistor. Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal.
8
9 10 11 12 13 14 15 16
VFXI+
2
1 CHIP CODEC
S5T8554B/7B
ABSOLUTE MAXIMUM RATING
Characteristic Positive Supply Voltage Negative Supply Voltage Voltage at Any Analog Input or Output Voltage at Any Digital Input or Output Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 secs) Symbol VCC VBB VI (A) VI (D) Ta TSTG TLEAD Value 7 -7 VCC + 0.3 ~ VBB - 0.3 VCC + 0.3 ~ GNDA - 0.3 -25 ~ +125 -65 ~ +150 300 Unit V V V V C C C
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0V 5%, VBB = -5.0V 5%, GNDA = 0V, Ta = 0C to 70C; typical characteristics specified at VCC = 5.0V, VBB = -5.0V, Ta=25C; all signals referenced to GNDA) Characteristic POWER DISSIPATION Power-Down Current Power-Down Current Active Current Active Current DIGITAL INTERFACE Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage VIL VIH IIL IIH VOL - - GNDA VIN VIL, all digital input VIH VIN VCC DX, IL = 3.2mA SIGR, IL = 1.0mA TSX, IL = 3.2mA, open drain DX, IH = -3.2mA SIGR, IH = -1.0mA DX, GNDA VO VCC - 2.2 -10 -10 - - - - - - 0.6 - 10 10 0.4 0.4 0.4 - 10 V V A A V V V V V A ICC (DOWN) No Load IBB (DOWN) No Load ICC (A) IBB (A) No Load No Load - - - - 0.5 0.05 6.0 6.0 1.5 0.3 9.0 9.0 mA mA mA mA Symbol Test Conditions Min. Typ. Max. Unit
Output High Voltage Output Current in High Impedance State (Tri -state)
IO (HZ) IO (HZ)
2.4 2.4 -10
- -
ANALOG INTERFACE WITH RECEIVE FILTER Output Resistance RO Pin VFRO - 1 3
3
S5T8554B/7B
1 CHIP CODEC
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0V 5%, VBB = -5.0V 5%, GNDA = 0V, Ta = 0C to 70C; typical characteristics specified at VCC = 5.0V, VBB = -5.0V, Ta=25C; all signals referenced to GNDA) Characteristic Load Resistance Load Capacitance Output DC Offset Voltage Symbol RL CL VOO (RX) Test Conditions VFRO = 2.5V - - Min. 600 - -200 -200 10 - 10 - 2.8 5,000 - - CMRRXA > 60dB DC Test DC Test 1 -20 -2.5 60 60 Typ. - - - - - 1 - - - - 2 - - - - Max. - 500 200 Unit pF mV
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain Bandwidth Offset Voltage Common-Mode Voltage Common-Mode Rejection Ratio Power Supply Rejection Ratio ILKG RI RO RL CL VOD (TX) GV BW VIO (TX) VCM (TX) CMRR PSRR -2.5VV+2.5V, VFXI+ or VFXI-2.5VV+2.5V, VFXI+ or VFXIClosed loop, unity gain GSX GSX GSX, RL10KW VFXI+ to GSX 200 - 3 - 50 - - - 20 2.5 - - nA M k pF V V/N MHz mV V dB dB
4
1 CHIP CODEC
S5T8554B/7B
TIMING CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0V 5%, VBB = -5.0V 5%, GNDA = 0V, Ta = 0C to 70C; typical characteristics specified at VCC = 5.0V, VBB = -5.0V, Ta=25C; all signals referenced to GNDA) Characteristic Frequency of Master Clock Symbol fMCK Test Conditions Depends on the device used and the BCLKR/CLKSEL Pin. MCLKX and MCLKR tPB = 488ns tPB = 488ns Long frame only Short frame only Long frame only Load = 150pF plse 2 LSTTL loads Load = 150pF plse 2 LSTTL loads - CL = 0pF to 150pF Min. - Typ. 1.536 1.544 2.048 - - - - - - - - - Max. - Unit nS
Rise Time of Bit Clock Fall Time of Bit Clock Holding Time from Bit Clock Low to Frame Sync Holding Time from Bit Clock High to Frame Sync Set-Up Time from Frame Sync to Bit Clock Low Delay Time from BCLKX High to Data Valid Delay Time to TSX Low Delay Time from BCLKX Low to Data Output Disabled Delay Time to Valid Data from FSX or BCLKX, Whichever Comes Later Set-Up Time from DR Valid to BCLKR/X Low Hold Time from FSR/X Low to DR Invalid Set-Up Time from FSR/X to BCLKR/X Low Width of Master Clock High Width of Master Clock Low Rise Time of Master Clock Fall Time of Master Clock Set-Up Time from BCLKX High (and FSX In Long Frame Sync Mode) to MCLKX Falling Edge
tR (BCK) tF (BCK) tH (LFS) tH (RFS) tSU (FBCL) tD (HDV) tD (TSXL) tD (LDD) tD (VD)
- - 0 0 80 0 - 50 20
50 50 - - - 180 140 165 165
nS nS nS nS nS nS nS nS nS
tSU (DRBL) tH (BLDR) tSU (FBLS) tW (MCKH) tW (MCKL) tR (MCK) tF (MCK) tSU (BHMF)
- - Short frame sync pulse (1 or 2 bit clock periods long) (Note 1) MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLKR First bit clock after the leading edge FSX
50 50 50 160 160 - - -
- - - - - - - -
- - - - - 50 50 -
nS nS nS nS nS nS nS -
5
S5T8554B/7B
1 CHIP CODEC
TIMING CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0V 5%, VBB = -5.0V 5%, GNDA = 0V, Ta = 0C to 70C; typical characteristics specified at VCC = 5.0V, VBB = -5.0V, Ta=25C; all signals referenced to GNDA) Characteristic Period of Bit Clock Width of Bit Clock High Width of Bit Clock Low Hold Time from BCLKX/R Low to FSX/R Low Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSX or FSR) Minimum Width of the Frame Sync Pulse (Low Level) Symbol tCK tW (BCKH) tW (BCKL) tH (BLFL) tH (3rd) VIH = 2.2 VIL = 0.6V Short frame sync pulse (1 or 2 bit clock periods long) (Note 1) Long frame sync pulse (From 3 to 8 bit clock periods long) 64K bit/s operating mode Test Conditions - Min. 485 160 160 - 100 Typ. 488 - - - - Max. 15,725 - - - - Unit nS nS nS nS nS
tWFL
-
-
-
nS
NOTE: For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high.
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1 CHIP CODEC
S5T8554B/7B
TIMING DIAGRAM
tD(TSXL) TSx tR(MCK) MCLKR MCLKX tW(MCKH) BCLKX FSX DX tH(HFS) tSU(FBLS)
1
tF(MCK) tW(MCK) t CK
tSU(BHMF)
2 3 4 5 6 7 8
tH(BLFL) tD(HDV)
1 2 3 4 5 6
tD(LDD)
7 8
BCLKR tH(HFS) FSR DR tSU(FBLS)
1
2
3
4
5
6
7
8
tH(BLFL) tH(BLDR) tH(BLDR)
6 7 8
tSU(DRBL)
1 2 3 4 5
Figure 1. Short Frame Sync Timing
7
S5T8554B/7B
1 CHIP CODEC
TIMING DIAGRAM (Continued)
tW(MCKL) tR(MCK) MCLKR MCLKX tSU(BHML) tW(MCKH) tSBFM
1 2 tW(BCKH) tF(BCK) 3 tW(BCKL) 4 tCK 5 6 7 8 9
tF(MCK) tCK
BCLKX
tH(HFS) t SU(FBCK) FSX tD(VD) DX
tRB
tH(3rd) tD(HDV)
3 4 5 6 7
tD(VD)
1 2
tD(LDD)
8
tD(VD) BCLKR tH(HFS) tSU(FBLK) FSR tSU(DRBL) DR
1 2 3 4 1 3 4 5 6 7 8 9
tH(3rd)
tH(BLDL) tH(BLDL)
5 6 7 8
Figure 2. Long Frame Sync Timing
8
1 CHIP CODEC
S5T8554B/7B
TRANSMISSION CHARACTERISTICS
(Unless otherwise specified: Ta = 0C to 70C, VCC = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic AMPLITUDE RESPONSE Receive Gain, Absolute GV (ARX) Ta=25C, VCC=5V, VBB=-5V Input = Digital code sequence for 0dBm signal at 1020Hz f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz Ta = 0C to 70C VCC=5V 5%, VBB=-5V 5% Sinusoidal test method, reference input PCM code corresponds to an ideally encoded -10dB0 signal PCM level = -40dBm0 to +3dBm0 PCM level = -50dBm0 to -10dBm0 PCM level = -55dBm0 to -50dBm0 RL = 600 Norminal 0dBm0 level is 4dBm (600) 0dBm0 Max overload level (3.17dBm0): S5T8554B Max overload level (3.14dBm0): S5T8557B Ta = 25C, VCC = 5V, VBB = -5V Input at GSX = 0dBm0 at 1020Hz f = 16Hz f = 50Hz f = 60Hz f = 200Hz f = 300Hz - 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz f = 4600Hz and up, measure response from 0Hz to 4000Hz -0.15 - 0.15 dB Symbol Test Conditions Min. Typ. Max. Unit
Receive Gain, Relative to GV (ARX)
GV (RRX)
-0.15 -0.35 -0.7 - -
-
0.15 0.05 0 -14 0.1 0.05
dB dB dB dB dB dB
Absolute Receive Gain Variation with Temperature
GV (ARX) /T
- - -
Absolute Receive gain GV (ARX) Variation with Supply Voltage /V Receive Gain Variations with Level GV (RXL)
-0.2 -0.4 -1.2 -2.5 - - - 1.2276 2.501
0.2 0.4 1.2 2.5 - -
dB dB dB V Vrms VPK
Receive Output Drive Level Absolute Level Max Overload Level
VO (RX) VAL VOL (AMX)
Transmit Gain, Absolute Transmit Gain, Relative to GV (ARX)
GV (ATX) GV (RTX)
-0.15
- -
0.15 -40 -30 -26 -0.1 0.15 0.05 0 - -14 -32
dB dB dB dB dB dB dB dB dB dB dB
-1.8 -0.15 -0.35 -0.7
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S5T8554B/7B
1 CHIP CODEC
TRANSMISSION CHARACTERISTICS
(Unless otherwise specified: Ta = 0C to 70C, VCC = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Absolute Transmit Gain Variation with Temperature Symbol Test Conditions Min. - - Typ. - - - -0.2 -0.4 -1.2 - -40 -30 0.2 0.4 1.2 dB dB dB s s s s s s s s s s s s s s Max. 0.1 0.05 Unit dB dB
GV(ATX) Ta = 0C to 70C /T VCC = 5V 5%, VBB = -5V 5% Sinusoldal test method Reference level = - 10dBm0 VFXI + = - 40dBm0 to +3dBm0 VFX + = - 50dBm0 to - 40dBm0 VFXI + = - 55dBm0 to - 50dBm0
Absolute Transmit Gain GV Variation with Supply Voltage (ATX) /V Transmit Gain Variations with Level -
ENVELOPE DELAY DISTORTION WITH FREQUENCY Receive Delay, Absolute Receive Delay, Relative to tD (ARX) tD (ARX) tD (RRX) f = 1600Hz f = 500Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz f = 1600Hz f = 500Hz - 600Hz f = 600Hz - 800Hz f = 800Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz 180 -25 -120 70 100 145 290 195 120 50 20 55 80 130 200
90 125 175 315 220 145 75 40 75 105 155
Transmit Delay, Absolute Transmit Delay, Relative to tD (ATX)
tD (ATX) tD (RTX)
- -
NOISE Receive Noise, CMessage Weighted Receive Noise, PMessage Weighted Transmit Noise, CMessage Weighted Transmit Noise, PMessage Weighted Noise, Single Frequency Positive Power Supply Rejection, Transmit NRXC PCM code equals alternating positive and negative zero, S5T8554B PCM code equals, positive zero, S5T8557B S5T8554B S5T8557B f = 0kHz to 100kHz, loop around measurement, VFXI + = 0Vrms VFXI + = 0Vrms, VCC = 5.0VDC + 100mVrms f = 0kHz - 50kHz - 8 11 dBrnc0
NRXP NTXC NTXP NSF PSRR
(PTX)
- - - - 40
-82 12 74 - -
-79 15 -67 -53 -
dBm0p dBrnc0 dBm0p dBm0 dBC
10
1 CHIP CODEC
S5T8554B/7B
TRANSMISSION CHARACTERISTICS
(Unless otherwise specified: Ta = 0C to 70C, VCC = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Negative Power Supply Rejection, Transmit Positive Power Supply Rejection, Receive Symbol PSRR
(NTX)
Test Conditions VFXI + = 0Vrms, VBB = -5.0VDC + 100mVrms f = 0kHz - 50kHz PCM code equals positive zero VCC = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4kHz - 25kHz f = 25kHz - 50kHz PCM code equals positive zero VBB = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4kHz - 25kHz f = 25kHz - 50kHz Loop around measurement, 0dBm0, 300Hz - 3400Hz input PCM applied to DR, Measure individual image signals at VFRO 4600Hz - 760Hz 7600Hz - 8400Hz 8400Hz - 100,000Hz
Min. 40
Typ. - -
Max. - -
Unit dBC
PSRR
(PRX)
40 40 36 - 40 40 36 - - -
dBC dB dB
Negative Power Supply Rejection, Receive
PSRR
(NRX)
dBC dB dB
Spurious Out-of-Band Signals at the Channel Output
SOS
-32 -40 -32 - 33 26 29 30 14 15 - - - - - - -46 -46 -41 -
dB dB dB
DISTORTION Signal to Total Distortion Transmit or Receive HalfChannel THDTX THDRX Sinusoidal test method Level = 3.0dBm0 = 0dBm0 to 30dBm0 = -40dBm0 XMT RCV = -55dBm0 XMT RCV - - Loop around measurement, VFXI + = -4dBm0 to -21dBm0, two frequencies in the range 300Hz - 3400Hz dBC dBC dBC dBC dBC dBC dB dB dB
Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion
THDSF
(TDO)
THDSF
(RX)
THDIMD
CROSSTALK Transmit to Receive Crosstalk, 0dB0 Transmit Level CT (TX-RX) f = 300Hz - 3400Hz DR = Steady PCM code - -90 -75 dB
11
S5T8554B/7B
1 CHIP CODEC
TRANSMISSION CHARACTERISTICS
(Unless otherwise specified: Ta = 0C to 70C, VCC = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02kHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Receive to Transmit Crosstalk, 0dBm0 Receive Level Symbol CT (RX-TX) Test Conditions - Min. - Typ. -90 Max. -70 (Note1) Unit dB
NOTE: CT (RX-TX) is measured with a - 40dBm0 activating signal applied at VFXI +
Encoding Format At DX Output -Law KT8554 VIN (at GSX) = + Full Scale VIN (at GSX) = 0V VIN (at GSX) = -Full Scale 10000000 11111111 01111111 0000000 A-Law KT8557 10101010 11010101 01010101 00101010
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1 CHIP CODEC
S5T8554B/7B
APPLICATION CIRCUIT
+5V -5V
0.1F
0.1F
4 VCC R2 14 GS X
2 GND
1 V BB DX 11 DR 6 9 10 7 R6 FSXS 12 FS
X/R
DX DR CLOCK
S5T8554B/7B
FROM SLIC R4 TO SLIC R3 3 VFRO R1 15 VFXI-
KT8554/7
MCLKX BCLK X BCLKR/CLKSEL
16 PDN 8
VFXI+
u-low only
MCLK R/PDN
FSR
5
NOTES: 1. Supposing Desired Line Termination Impedance RL = 600ohm It is 0dBm = 0.77459Vrms 2. TX Gain 20 log (R2/R1), R1 + R2 < 100Kohm, or The Correspondence of 1-CHIP CODEC 0dBm 0 = 4dBm.
SELECTION OF MASTER CLOCK FREQUENCY BCLKR/CLKSEL Clocked 0 1 (or open) S5T8554B 1.536 / 1.544MHz 2.048MHz 1.536 / 1.544MHz 2.048MHz 1.536 / 1.544MHz 2.048MHz S5T8557B
13
S5T8554B/7B
1 CHIP CODEC
NOTES
14

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