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Preliminary W741C20X 4-BIT MICROCONTROLLER
Table of Contents-GENERAL DESCRIPTION ..............................................................................................................................2 FEATURES......................................................................................................................................................2 PIN CONFIGURATION ....................................................................................................................................3 PIN DESCRIPTION..........................................................................................................................................4 BLOCK DIAGRAM ...........................................................................................................................................5 FUNCTIONAL DESCRIPTION ........................................................................................................................6 ABSOLUTE MAXIMUM RATINGS ................................................................................................................27 DC CHARACTERISTICS...............................................................................................................................28 AC CHARACTERISTICS...............................................................................................................................29 PAD ASSIGNMENT & POSITIONS...............................................................................................................30 TYPICAL APPLICATION CIRCUIT................................................................................................................31 INSTRUCTION SET TABLE ..........................................................................................................................32 PACKAGE DIMENSIONS..............................................................................................................................79
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
GENERAL DESCRIPTION
The W741C20X is a high-performance 4-bit microcontroller (C) that operates on very low current. The device contains a 4-bit ALU, two 8-bit timers, a divider, a serial port, and five 4-bit I/O ports (including 3 output ports for LED driving). There are also seven interrupt sources and 8-level subroutine nesting for interrupt applications. The W741C20X has two power reduction modes, hold mode and stop mode, which help to minimize power dissipation. The W741C20X is suitable for remote controllers, toy controllers, keyboard controllers, speech synthesis LSI controllers, and other products.
FEATURES
* Operating voltage: 2.2V to 5.5V * Crystal or RC oscillation circuit can be selected by the code option
- Crystal/Ceramic oscillator: up to 4 MHz - RC oscillator: up to 4 MHz * Both in crystal or RC oscillator operation mode, high-frequency (400 KHz to 4 MHz) or lowfrequency (32.768 KHz) oscillation must be determined by the code option * Memory - 2048 x 16 bit program ROM (including 2K x 4 bit look-up table) - 128 x 4 bit data RAM (including 16 working registers)
* 21 input/output pins
- Input/output ports: 4 ports/16 pins - Serial input/output port: 1 port /4 pins (high sink current for LED driving) - MFP output pin: 1 pin (MFP) * Power-down mode - Hold function: no operation (except for oscillator) - Stop function: no operation (including oscillator)
* Seven types of interrupts
- Five internal interrupts (Divider 0, Timer 0, Timer 1, and Serial I/O) - Two external interrupts (Port RC and INT pin)
* MFP output pin
- Output is software selectable as modulating or nonmodulating frequency - Works as frequency output specified by Timer 1 * Built-in 14-bit clock frequency divider circuit * Two built-in 8-bit programmable countdown timers - Timer 0: One of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected - Timer 1: Offers auto-reload function, and one of two internal clock frequencies (FOSC or FOSC/64) can be selected, or falling edge of pin RC.0 can be selected (output through MFP pin) * Built-in 18/14-bit watchdog timer selectable for system reset -2-
Preliminary W741C20X
* Powerful instruction set: 118 instructions * 8-level subroutine (include interrupt) nesting * One serial transmission/receiver port specified by software * Up to 1 S instruction cycle (with 4 MHz operating frequency) * Packaged in 18-pin, 20-pin, 28-pin PDIP and 20-pin, 28-pin SOP
PIN CONFIGURATION W741C202/C205
RA2 RA3 INT RES RA1 RA0 XIN XOUT VDD RC3 RC2 RC1 RC0 VSS RE0 RE1 RE2 RE3 RB0 RB1 RB2 RB3 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RA1 RA0 XIN XOUT VDD RD3 RD2 RD1 RD0 RC3 RC2 RC1 RC0 MFP
W741C201
RA2 RA3 INT RES VSS RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
18-PDIP(300 mil)
28 SKINNY(300 mil), 28 SOP
W741C203
RA2 RA3 INT RES VSS VSS RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 XIN XOUT VDD VDD RC3 RC2 RC1 RC0 RA2 RA3 INT RES VSS VSS RB0 RB1 RB2 RB3
W741C204
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 XIN XOUT VDD VDD RC3 RC2 RC1 RC0
20-PDIP(300 mil)
20 SOP
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
PIN DESCRIPTION
SYMBOL XIN XOUT RA0-RA3 I/O I O I/O FUNCTION Input pin for oscillator. Connected to crystal or resistor to generate system clock by code option. Output pin for oscillator. Connected to crystal or resistor to generate system clock by code option. Input/Output port. Input/output mode specified by port mode 1 register (PM1). When used as output port, can provide high sink current for driving LED. Input/Output port. Input/output mode specified by port mode 2 register (PM2). When used as output port, can provide high sink current for driving LED. Input/Output port. Input/output mode specified by port mode 4 register (PM4). Each pin has an independent interrupt capability in input mode. Input/Output port. Input/output mode specified by port mode 5 register (PM5). Special input/output port. This port can be configured by software to act as the output of internal port RT or the serial I/O port. When used as output port, can provide high sink current for driving LED. Output pin only. This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1). External interrupt pin with pull-high resistor. System reset pin with pull-high resistor. Positive power supply (+). Negative power supply (-).
RB0-RB3
I/O
RC0-RC3 RD0-RD3 RE0/DOUT RE1/CLKO RE2/DIN RE3/CLKI MFP
I/O I/O I/O
O
INT RES
I I I I
VDD VSS
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Preliminary W741C20X
BLOCK DIAGRAM
RAM (128*4) RA0 to 3
PORT RA ROM (2048*16)
(look_up table 2K*4)
ACC PORT RB RB0 to 3
ALU
+1(+2)
PORT RC PC
RC0 to 3
Central Control Unit
IEF HEF EVF PEF SEF
PORT RD
RD0 to 3
STACK (8 Levels)
HCF
PSR0 PSR1 PSR2 PR MR0 PM0
PORT RT
SEL
.
.
.
RE0 to 3
(RE0/DOUT, RE1/CLKO, RE2/DIN, RE3/CLKI)
Serial I/O
MUX
Timer 0 (8-bit)
Timer 1 (8-bit)
Modulation Frequency Pulse
SEL
MUX
MFP
Watchdog Timer (4-bit)
Divider 0 (14-bit)
VDD VSS Timing Generator INT RES
XIN
XOUT
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
FUNCTIONAL DESCRIPTION
Program Counter (PC)
Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses of the 2048 x 16 on-chip ROM containing the program instruction words. When jump or subroutine call instructions or interrupt, or initial reset conditions are to be executed, the address corresponding to the instruction will be loaded into the program counter. The format used is shown below.
ITEM Initial Reset INT 0 (Divider) INT 1 (Timer 0) INT 2 (Port RC) INT 3 ( INT pin) INT 4 (Serial Port Input) INT 5 (Serial Port Output) INT 6 (Timer 1) JMP Instruction Subroutine Call
ADDRESS 000H 004H 008H 00CH 014H 018H 01CH 020H XXXH XXXH
INTERRUPT PRIORITY 1st 2nd 3rd 4th 5th 6th 7th -
Stack Register (STACK)
The stack register is organized as 11 bits x 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep.
Program Memory (ROM)
The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048 x 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements. Instruction MOVC R is used to read the look-up table and transfer table data to the RAM. The organization of the program memory is shown in Figure 1.
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Preliminary W741C20X
16 bits 000H
TABH TABL ACC -xxx xxxx xxyy 2048 address Offset 011x xxxx xxxx
ROM address = 600H + Offset/4 600H 3 2 1 0
This area can be used to store both instruction code and look-up table Each element (4 bits) of the look-up table
7FFH 2048 x 16-bit
Figure 1. Program Memory Organization
Data Memory (RAM)
1. Architecture The static data memory (RAM) used to store data is arranged as 128 x 4 bits. The data memory can be addressed directly or indirectly. The organization of the data memory is shown in Figure 2.
4 bits 00H : 0FH Working Register
128 address
7FH 128 x 4-bit Figure 2. Data Memory Organization
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers (WR). The other data memory is used as general memory and cannot operate directly with immediate data. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next section. 2. Page Register (PAGE) The page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 PAGE
Note: R/W means read/write available.
2 R/W
1 R/W
0 R/W
Bit 3 is reserved. Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits: 000 = Page 0 (00H - 0FH) 001 = Page 1 (10H - 1FH) 010 = Page 2 (20H - 2FH) 011 = Page 3 (30H - 3FH) 100 = Page 4 (40H - 4FH) 101 = Page 5 (50H - 5FH) 110 = Page 6 (60H - 6FH) 111 = Page 7 (70H - 7FH)
Accumulator (ACC)
The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.
Arithmetic and Logic Unit (ALU)
This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions: * Logic operations: ANL, XRL, ORL * Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3 * Shift operations: SHRC, RRC, SHLC, RLC * Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOVA R, CF.
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Preliminary W741C20X
Clock Generator
The W741C20X provides a crystal or RC oscillation circuit selected by option codes to generate the system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be connected to XIN and XOUT, and the capacitor must be connected if an accurate frequency is needed. When a crystal oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is used, a resistor in the range of 20 K to 1.6 M must be connected to XIN and XOUT, as shown in Figure 3. The system clock frequency range is from 32 KHz to 4 MHz. One machine cycle consists of a four-phase system clock sequence and can run up to 1 S with a 4 MHz system clock.
XIN Crystal 32 KHz or 400K to 4MHz XOUT
XIN
or
Resistor XOUT
Figure 3. Oscillator Configuration
Divider 0
Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as shown in Figure 4. When the system starts, the divider is incremented by each system clock (FOSC). When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. The last 4-stage of the Divider 0 can be reset by executing CLR DIVR0 instruction. If the oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1 periodically at each 500 mS interval.
Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset. The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Divider0
Fosc
Q1 Q2
HEF.0
S Q R
... Q9
Q10 Q11 Q12 Q13 Q14
R R R R
EVF.0
IEF.0
Hold mode release (HCF.0) Divider0 interrupt (INT0)
1. Reset 2. CLR EVF, #01H 3. CLR DIVR0 Fosc/16384 Fosc/1024 Enable /Disable Mask Option PMF.3
R
WDT
Qw1 Qw2 Qw3 Qw4
R R R
Overflow signal
System Reset
1. Reset 2. CLR WDT
Figure 4. Organization of Divider and Watchdog Timer
Parameter Flag (PMF)
The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:
3 PMF
Note: W means write only.
2
1
0
W
Bit 0, Bit 1 & Bit 2 are reserved. Bit 3 = 0 The fundamental frequency of the watch dog timer is FOSC/1024. = 1 The fundamental frequency of the watch dog timer is FOSC/16384. At initial reset, bit 3 of PMF is set to "0".
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Preliminary W741C20X
Timer/Counter
Timer 0 (TM0) Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instruction. When the MOV TM0L (TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting), the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 5. If the Timer 0 clock input is FOSC/4, then: Desired time 0 interval = (preset value +1) x 4 x 1/FOSC If the Timer 0 clock input is FOSC/1024, then: Desired time 0 interval = (preset value +1) x 1024 x 1/FOSC Preset value: Decimal number of Timer 0 preset value FOSC: Clock oscillation frequency
1. Reset 2. CLR EVF, #02H 3. Reset MR0.3 to 0 4. MOV TM0L, R or MOV TM0H, R MR0.0 Fosc/1024 Fosc/4 Enable 1. Set MR0.3 to 1 2. MOV TM0, #I MOV TM0H, R Disable 8-bit Binary Down Counter (Timer 0) 4 8 MOV TM0L, R 4 HEF.1 S R Hold mode release (HCF.1) Q EVF.1 IEF.1 Timer 0 interrupt (INT1)
1. Reset 2. CLR EVF, #02H 3. Set MR0.3 to 1 4. MOV TM0, #I
MOV TM0, #I
Figure 5. Organization of Timer 0
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Timer 1 (TM1) Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: Fosc/64, Fosc, or an external clock from the RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is Fosc. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L, R or MOV TM1H,R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into auto-reload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting. If the Timer 1 clock input is FT, then: Desired Timer 1 interval = (preset value +1) / FT Desired frequency for MFP output pin = FT / (preset value + 1) / 2 (Hz) Preset value: Decimal number of Timer 1 preset value, and FOSC: Clock oscillation frequency
MOV TM1, #I MOV TM1H, R 8 1. MR1.3 = 1 2. MOV TM1, #I 4 Auto-reload buffer External clock via RC.0 MR1.1 Enable FT Fosc/64 Fosc MR1.0 8 bits 8-bit Binary Down Counter (Timer 1) Disable Reset Set MR1.3 to 1 MOV TM1, #I 1. MR1.3 = 0
Figure 6. Organization of Timer 1
MOV TM1L, R Underflow signal 4
S R
Q
EVF.7
1. Reset 2. INT 7 accept 3. CLR EVF, #80H 4. Set MR1.3 to 1 5. MOV TM1, #I
2
circuit
Reset
MFP output pin MR1.2
MFP signal
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Preliminary W741C20X
For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below.
3rd octave Tone frequency C C# T D D# O E F N F# G E G# A A# B 130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.08 246.94 TM1 preset value & MFP frequency 7CH 75H 6FH 68H 62H 5DH 58H 53H 4EH 49H 45H 41H 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24 Tone frequency 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 4th octave TM1 preset value & MFP frequency 3EH 3AH 37H 34H 31H 2EH 2BH 29H 26H 24H 22H 20H 260.06 277.69 292.57 309.13 327.68 372.36 390.09 420.10 443.81 442.81 468.11 496.48 Tone frequency 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77 5th octave TM1 preset value & MFP frequency 1EH 1CH 1BH 19H 18H 16H 15H 14H 13H 12H 11H 10H 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76
Note: Central tone is A4 (440 Hz).
Mode Register 0 (MR0)
Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows: 3 MR0
Note: W means write only.
2
1
0 W
W
Bit 0 = 0 =1 Bit 3 = 0 =1
The fundamental frequency of Timer 0 is FOSC/4. The fundamental frequency of Timer 0 is FOSC/1024. Timer 0 stops down-counting. Timer 0 starts down-counting.
Bit 1 & Bit 2 are reserved
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Mode Register 1 (MR1)
Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows: 3 MR1
Note: W means write only.
2 W
1 W
0 W
W
Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC. = 1 The internal fundamental frequency of Timer 1 is FOSC/64. Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock. = 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin. Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin. = 1 The specified frequency of Timer 1 is delivered at the MFP output pin. Bit 3 = 0 Timer 1 stops down-counting. = 1 Timer 1 starts down-counting.
Input/Output Ports RA, RB
Port RA consists of pins RA.0 to RA.3 and Port RB consists of pins RB.0 to RB.3. At initial reset, input/output ports RA and RB are both in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or RB can be specified as input or output mode independently by the PM1 and PM2 registers. The MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV RB, R operate the output functions. For more details, refer to the instruction table and Figure 7.
Input/Output Pin of the RA(RB)
VDD
PM0.0 (or PM0.1)
Output Buffer DATA BUS
Enable
I/O PIN RA.n(RB.n)
PM1.n (or PM2.n)
MOV RA, R (or MOV RB, R) Instruction
Enable
MOVA R, RA (or MOVA R, RB) instruction
Figure 7. Architecture of RA & RB Input/Output Pins
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Preliminary W741C20X
Port Mode 0 Register (PM0)
The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows: 3 PM0
Note: W means write only.
2
1 w
0 w
Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 0 RB port is CMOS output type. Bit 0 = 1 RB port is NMOS open drain output type. Bit 2 & Bit 3 are reserved.
Port Mode 1 Register (PM1)
The port mode 1 register is organized as 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit descriptions are as follows: 3 PM1
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin At initial reset, port RA is input mode (PM1 = 1111B).
Port Mode 2 Register (PM2)
The port mode 2 register is organized as 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit descriptions are as follows: 3 PM2
Note: W means write only.
2 w
1 w
0 w
w
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin At initial reset, the port RB is input mode (PM2 = 1111B).
Port Mode 3 register (PM3)
Port Mode 3 Register is organized as a 4-bit binary register (PM3.0 to PM3.3). PM3 can be used to determine the operating mode of the output port RE and the clock rate of the serial I/O function. The PM3 control diagram is shown in Figure 8. The bit descriptions are as follows: 3 PM3
Note: W means write only.
2
1 W
0
W
Bit 0 is reserved. Bit 1 = 0 The output of the port RE is the output of the internal parallel port RT. = 1 The port RE works as the serial input/output port. Bit 2 is reserved. Bit 3 = 0 Serial Tx rate = FOSC/2 = 1 Serial Tx rate = FOSC/256
Internal parallel port RT Fosc/256 Fosc/2 PM3.3 PM3.1 MUX. Serial I/O port Port RE
Figure 8. PM3 Control Diagram
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Preliminary W741C20X
Port Mode 4 Register (PM4)
The port mode 4 register is organized as 4-bit binary register (PM4.0 to PM4.3). PM4 can be used to control the input/output mode of port RC. PM4 is controlled by the MOV PM4, #I instruction. The bit descriptions are as follows: 3 PM4
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 RC.0 works as output pin; Bit 0 = 1 RC.0 works as input pin Bit 1 = 0 RC.1 works as output pin; Bit 1 = 1 RC.1 works as input pin Bit 2 = 0 RC.2 works as output pin; Bit 2 = 1 RC.2 works as input pin Bit 3 = 0 RC.3 works as output pin; Bit 3 = 1 RC.3 works as input pin At initial reset, port RC is input mode (PM4 = 1111B).
Port Mode 5 Register (PM5)
The port mode 5 register is organized as 4-bit binary register (PM5.0 to PM5.3). PM5 can be used to control the input/output mode of port RD. PM5 is controlled by the MOV PM5, #I instruction. The bit descriptions are as follows: 3 PM5
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 RD.0 works as output pin; Bit 0 = 1 RD.0 works as input pin Bit 1 = 0 RD.1 works as output pin; Bit 1 = 1 RD.1 works as input pin Bit 2 = 0 RD.2 works as output pin; Bit 2 = 1 RD.2 works as input pin Bit 3 = 0 RD.3 works as output pin; Bit 3 = 1 RD.3 works as input pin
At initial reset, the port RB is input mode (PM2 = 1111B). Input/Output Ports RC, RD
Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. At initial reset, input/output ports RC and RD are both in input mode. When RC and RD are used as output ports, the CMOS type is the only ouput driving type. Each pin of port RC or RD can be specified as input or output mode independently by the PM4 and PM5 registers. The MOVA R, RC or MOVA R, RD instructions operate the input functions and the MOV RC, R or MOV RD, R operate the output functions. When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register 0 (PSR0) records the status of port RC, and that can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. Before the port mode of the RC port is changed from output mode to input mode in the hold mode release and interrupt application, the output value must be preset to the same as the system status to prevent the undesired signal change being accepted. Publication Release Date: March 1998 Revision A3
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Preliminary W741C20X
When the interrupt of RC port is accepted, the corresponding event flag (EVF.2) will be reset, but the content of PSR0 should not be changed except the CLR PSR0 or MOV PEF, #I instruction being executed or performing the reset function. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. The RD port is used as the I/O port only. Refer to Figure 9, Figure 10 and the instruction table for more details.
Input/Output Pin of the RC(RD)
Vdd
Output Buffer DATA BUS
Enable
I/O PIN RC.n(RD.n)
PM4.n (or PM5.n)
MOV RC, R (or MOV RD, R) Instruction
Enable
MOVA R, RC (or MOVA R, RD) instruction
Figure 9. Architecture of RC & RD Input/Output Pins
Port Enable Flag (PEF)
The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to release the hold mode or preform interrupt function, the content of the PEF must be set first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows: 3 PEF
Note: W means write only.
2 w
1 w
0 w
w
PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.
Port Status Register 0 (PSR0)
Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows: 3 PSR0
Note: R means read only.
2 R
1 R
0 R
R
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Preliminary W741C20X
Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Signal change at RC.0 Signal change at RC.1 Signal change at RC.2 Signal change at RC.3
DATA BUS PM4.0 RC.0 Signal change detector PM4.1 RC.1 Signal change detector PM4.2 RC.2 Signal change detector PM4.3 RC.3 Signal change detector PEF.3 D ck R Q PSR0.3 PEF.2 D ck R Q PSR0.2 PEF.1 D ck R Q PSR0.1 EVF.2 D ck R IEF.2 Q PEF.0 D ck R Q PSR0.0
HEF.2
HCF.2
INT 2
CLR EVF, #I Reset
MOVA R, RC
Falling edge detector
SEF.0 PM4.0 SEF.1 PM4.1 SEF.2 PM4.2 SEF.3 PM4.3
Reset MOV PEF, #I CLR PSR0
Falling edge detector
Wake up from STOP mode
Falling edge detector
Falling edge detector
Figure 10. Input Architecture of Ports RC
Output Port RE
Output port RE can be used as an output of the internal RT port, or as a serial input/output port. The control flow is shown in Figure 8. When bit 1 of port mode 3 register (PM3) equals to 0, port RE works as an output of internal port RT. When the MOV RE, R instruction is executed, the data in the RAM will be output to port RT through port RE. When RE works as a parallel output port, it provides a high sink current to drive LEDs. When bit 1 of PM3 equals to 1, the RE port works as a serial input/output port, and RE.0 to RE.3 are used as DOUT, CLKO, DIN, and CLKI, respectively. In this case, the DIN pin will has a built-in pull-high resistor. The serial I/O functions are controlled by the instructions SOP R and SIP R. The functions of the two instructions are described below:
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
(1) When the SIP R instruction is executed, the data will be loaded from the serial input buffer to the ACC and RAM first, and bit 1 of port status register 2 will automatically be set to "1" (BUSYI = 1). Then the CLKI pin will send out 8 clocks and the data from the DIN pin will be loaded to SIB at the rising edge of the CLKI pin. After the 8 clocks have been sent, BUSYI will be reset to "0" and EVF.5 will be set to "1." At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is executed; if HEF.5 has been set (HEF.5 = 1), the hold state is terminated. Users can check the status of PSR2.1 (BUSYI) to know whether the serial input process is completed or not. If a serial input process is not completed, and the SIP R instruction is executed again, the data will be lost. The timing is shown in Figure 11.
T1 T2 T3 T4 Ins. CLKI
(RE3)
SIP R 1 2 3 4 5 6 7 8
Data latch BUSYI
(PSR2.1)
EVF5 DIN
(RE2)
Notes : 1. These clocks at the CLKI pin are internal clock and its frequency is Fosc/2. 2. When the internal signal of the data latch equals to "1," then the data in SIB will be loaded into RAM and ACC.
Figure 11. Timing of the Serial Input Function (SIP R)
(2) When the SOP R instruction is executed, the data will be loaded to the serial output buffer (SOB) and bit 3 of port status register 2 will be set to "1" (BUSYO = 1). Then the CLKO pin will send out 8 clocks and the data in SOB will be sent out at the falling edge of the CLKO pin. After the 8 clocks have been sent, BUSYO will be reset to "0" and EVF.6 will be set to "1." At this time, if IEF.6 has been set (IEF.6 = 1), an interrupt is executed; if HEF.6 has been set (HEF.6 = 1), the hold state is terminated. Users can check the status of PSR2.3 (BUSYO) to know whether the serial output process is completed or not. If a serial output process is not completed, and the SOP R instruction is executed again, the data will be lost. The timing is shown in Figure 12.
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Preliminary W741C20X
T1 T2 T3 T4 Ins. CLKO
(RE1)
SOP R 1 2 3 4 5 6 7 8
Data latch BUSYO
(PSR2.3)
EVF6 DOUT
(RE0)
Notes : 1. These clocks at the CLKO pin are internal clock and its frequency is Fosc/2. 2. When the internal signal of the data latch equals to "1," then the data of the RAM and ACC be loaded to SOB.
Figure 12. Timing of the Serial Output Function (SOP R)
In the above description, the low nibble location of the serial input/output register is contributed to the ACC, and the high nibble is to R. The port status register 2 (PSR2) including BUSYI, and BUSYO can be read out or cleared by the MOVA R, PSR2, or CLR PSR2 instruction.
Port Status Register 2 (PSR2)
Port status register 2 is organized as 4-bit binary register (PSR2.0 to PSR2.3). PSR2 is controlled by the MOVA R, PSR2, and CLR PSR2 instructions. The bit descriptions are as follows: 3 PSR2 R 2 1 R 0
Note: R means read only.
Bit 0 is reserved. Bit 1 (BUSYI): Serial port input busy flag. Bit 2 is reserved. Bit 3 (BUSYO): Serial port output busy flag.
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
MFP Output Pin (MFP)
The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal from among DC, 4096Hz, 2048Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (when using a 32.768 KHz crystal). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown as below.
(FOSC = 32.768 KHz)
R7 R6
00
01
10
11
R5 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1
R4 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0
R3 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0
R2 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
R1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
R0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0
FUNCTION Low level 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz 1 Hz High level 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz 1 Hz 2048 Hz 2048 Hz * 128 Hz 2048 Hz * 64 Hz 2048 Hz * 8 Hz 2048 Hz * 4 Hz 2048 Hz * 2 Hz 2048 Hz * 1 Hz 4096 Hz 4096 Hz * 128 Hz 4096 Hz * 64 Hz 4096 Hz * 8 Hz 4096 Hz * 4 Hz 4096 Hz * 2 Hz 4096 Hz * 1 Hz
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Preliminary W741C20X
Interrupts
The W741C20X provides five internal interrupt sources (Divider 0, Timer 0, Timer 1, serial I/O) and two external interrupt sources ( INT , port RC). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the C will enter hold mode again. The operation flow chart is shown in Figure 14. The control diagram is shown below.
EN INT Divider 0 overflow signal MOV IEF,#I S R Timer 0 underflow signal EVF.1 Q EVF.0
Initial Reset Enable
IEF.0
S R
Q
Interrupt IEF.1 Process Circuit
Interrupt Vector Generator
004H 008H 020H
Timer 1 underflow signal
S R
Q
EVF.7 IEF.7
Initial Reset Disable CLR EVF,#I instruction
DIS INT instruction
Figure 13. Interrupt event control diagram
Interrupt Enable Flag (IEF)
The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or EN INT is executed again. To enable these interrupts, the instructions MOV IEF, #I or EN INT must be executed again. Otherwise, these interrupts can be disabled by executing DIS INT instruction. The bit descriptions are as follows: 7 IEF
Note: W means write only.
6 w
5 w
4 w
3
2 w
1 w
0 w
w
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0. IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0. IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC. IEF.3 is reserved. IEF.4 = 1 Interrupt 4 is accepted by a falling edge signal at the INT pin. IEF.5 = 1 Interrupt 5 is accepted by the serial port received completely. IEF.6 = 1 Interrupt 6 is accepted by the serial port transmitted completely. IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
External INT
The external interrupt INT pin contains a pull-up resistor. When the HEF.4 or IEF.4 flag is set, the falling edge of the INT pin will execute the hold mode release or interrupt subroutine. A low level on the INT pin will release the stop mode.
Stop Mode Operation
In stop mode, all operations of the C cease (including the operation of the oscillator). The C enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a low level on the INT pin or a falling signal on the RC port). When the designated signal is accepted, the C awakens and warms up, and then executes the next instruction.
Stop Mode Wake-up Enable Flag for Ports RC (SEF)
The stop mode wake-up flag for ports RC is organized as a 4-bit binary register (SEF.0 to SEF.3). Before port RC may be used to make the device exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows: 3 SEF
Note: W means write only.
2 w
1 w
0 w
w
SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0 SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1 SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2 SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3
Hold Mode Operation
In hold mode, all operations of the C cease, except for the operation of the oscillator and timer. The C enters hold mode when the HOLD instruction is executed. The hold mode can be released in one of five ways: by the action of timer 0, timer 1, the divider, the INT pin, the RC port. Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction-set table and the following flow chart.
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Preliminary W741C20X
Divider 0, /INT, Timer 0, Timer 1, Serial I/O and signal Change at RC Port
Yes
In HOLD Mode?
No
Interrupt Enable? Yes
No
Interrupt Enable? Yes
No
IEF Flag Set? Yes Reset EVF Flag Execute Interrupt Service Routine (Note)
No
IEF Flag Set? Yes Reset EVF Flag Execute Interrupt Service Routine Yes
No
HEF Flag Set? No
(Note)
Disable interrupt
Disable interrupt
HOLD
PC <- (PC+1)
Note: The bit of EVF corresponding to the interrupt signal will be reset.
Figure 14. Hold Mode and Interrupt Operation Flow Chart
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Hold Mode Release Enable Flag (HEF)
The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I instruction. The bit descriptions are as follows: 7 HEF
Note: W means write only.
6 w
5 w
4 w
3
2 w
1 w
0 w
w
HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released. HEF.2 = 1 Signal change at port RC causes Hold mode to be released. HEF.3 is reserved. HEF.4 = 1 Falling edge signal at the INT pin causes Hold mode to be released. HEF.5 = 1 The serial port received completely causes Hold mode to be released. HEF.6 = 1 The serial port transmitted completely causes Hold mode to be released. HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released.
Hold Mode Release Condition Flag (HCF)
The hold mode release condition flag is organized as a 8-bit binary register (HCF0 to HCF7). It indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset by the CLR EVF or MOV HEF,#I (HEF = 0) instructions. When EVF and HEF have been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows: 7 HCF
Note: R means read only.
6 R
5 R
4 R
3
2 R
1 R
0 R
R
HCF.0 = 1 Hold mode was released by overflow from the Divider 0 HCF.1 = 1 Hold mode was released by underflow from the timer 0 HCF.2 = 1 Hold mode was released by a signal change at port RC HCF.3 is reserved. HCF.4 = 1 Hold mode was released by a falling edge signal at the INT pin HCF.5 = 1 Hold mode was released by underflow from the timer 1 HCF.6 = 1 Hold mode was released by the serial port received completely. HCF.7 = 1 Hold mode was released by the serial port transmitted completely.
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Preliminary W741C20X
Event Flag (EVF)
The event flag is organized as a 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset by CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows: 7 EVF
Note: R means read only.
6 R
5 R
4 R
3
2 R
1 R
0 R
R
EVF.0 = 1 Overflow from Divider 0 occurred. EVF.1 = 1 Underflow from Timer 0 occurred. EVF.2 = 1 Signal change at port RC occurred. EVF.3 is reserved. EVF.4 = 1 Falling edge signal at the INT pin occurred. EVF.5 = 1 The serial port received completely. EVF.6 = 1 The serial port transmitted completely. EVF.7 = 1 Underflow from Timer 1 occurred.
Reset Function
The W741C20X is reset either by a power-on reset or by using the external RES pin. The initial state of the W741C20X after the reset function is executed is described below. Program Counter (PC) TM0, TM1 MR0, MR1, PAGE registers PSR0, PSR2, PM3 registers IEF, HEF, HCF, PEF, EVF, SEF flags Timer 0 input clock Timer 1 input clock MFP output Input/output ports RA, RB Input/output ports RC, RD Output port RE RA and RB ports output type Input clock of the watchdog timer 000H Reset Reset Reset Reset FOSC/4 FOSC Low Input mode Input mode High CMOS type FOSC/1024
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature RATING -0.3 to +7.0 -0.3 to +7.0 120 0 to +70 -55 to +150 UNIT V V mW C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC CHARACTERISTICS
(VDD-VSS = 3.0V, Fosc. = 32.768 KHz, Ta = 25 C; unless otherwise specified)
PARAMETER Op. Voltage Op. Current (Crystal type) Op. Current (RC type) Hold Current (Crystal type) Hold Current (RC type) Stop Current (Crystal type) Stop Current (RC type) Input Low Voltage Input High Voltage MFP Output Low Voltage MFP Output High Voltage Port RA, RB Sink Current Port RA, RB Source Current Port RC, RD Output Low Voltage Port RC, RD Output High Voltage Port RE Sink Current Port RE Source Current
SYM. VDD IOP1 IOP2 IHM1 IHM2 ISM1 ISM2 VIL VIH VML VMH IABL IABH VCDL VCDH IEL IEH
CONDITIONS No load (Ext-V) No load (Ext-V) Hold mode No load (Ext-V) Hold mode No load (Ext-V) Stop mode No load (Ext-V) Stop mode No load (Ext-V) IOL = 3.5 mA IOH = -3.5 mA VOL = 0.9V VOH = 2.4V IOL = 2.0 mA IOH = -2.0 mA VOL = 0.9V VOH = 2.4V
MIN. 2.2 VSS 0.7 VDD 2.4 9 0.4 2.4 9 0.4
TYP. 8 35 4 16 0.1 0.1 1.2 1.2
MAX. 5.5 20 65 6 40 2 2 0.3 VDD VDD 0.4 0.4 -
UNIT V A A A A A A V V V V mA mA V V mA mA
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Preliminary W741C20X
DC Characteristics, continued
PARAMETER
INT Pull-up Resistor
SYM. RINT RDIN RRES
CONDITIONS RE.2 used as serial input pin -
MIN. 50 50 20
TYP. 250 250 100
MAX. 1000 1000 500
UNIT K K K
DIN Pin Pull-up Resistor
RES Pull-up Resistor
AC CHARACTERISTICS
(VDD-VSS = 3.0 V, Ta = 25 C; unless otherwise specified)
PARAMETER Op. Frequency
SYM. FOSC
CONDITIONS RC type Crystal type 1 (Option low speed type) Crystal type 2 (Option high speed type) f(3V) - f(2.4V) f(3V) One machine cycle FOSC = 32.768 KHz FOSC = 32.768 KHz
MIN. 400 -
TYP. 32.768 -
MAX. 4000 4190 10
UNIT KHz
Frequency Deviation by Voltage drop for RC Oscillator Instruction Cycle Time Serial Port Data Ready Time Serial Port Data Hold Time Reset Active Width Interrupt Active Width
f f TI TDR TDH TRAW TIAW
%
200 200 1 1
4/FOSC -
-
S nS nS S S
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
PAD ASSIGNMENT & POSITIONS
2580 m
3 4 5 2280 m 6
2
1
29
28
27 26
Y
25 24 X (0,0) 23 22 21 20
7 8 9 10 12 11 13 14
15
16
17
18 19
Note: The chip substrate must be connected to system ground (VSS).
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PAD NAME RA2 RA3
INT RES
X -576.30 -819.50 -1063.00 -1115.00 -1115.00 -1115.00 -1115.00 -1115.00 -1115.00 -1115.00 -1115.00 -813.30 -552.10 -302.10 -40.90
Y 943.70 943.70 943.70 671.70 464.20 207.00 -21.00 -264.20 -492.20 -749.40 -965.00 -965.00 -965.00 -965.00 -965.00
PAD NO. 16 17 18 19 20 21 22 23 24 25 26 27 28 29
PAD NAME RC0 RC1 RC2 RC3 VDD RD0 RD1 RD2 RD3 VDD XOUT XIN RA0 RA1
X 215.10 476.30 722.30 1113.90 1113.90 1113.90 1113.90 1113.90 1113.90 1113.90 1113.90 1061.30 752.20 509.00
Y -965.00 -965.00 -965.00 -959.30 -749.30 -492.10 -264.10 -20.90 207.10 464.30 738.00 943.70 943.70 943.70
VSS RE0 RE1 RE2 RE3 VSS RB0 RB1 RB2 RB3 MFP
- 30 -
Preliminary W741C20X
TYPICAL APPLICATION CIRCUIT
Vcc
VDD RA0 Output Signal RA3 Vcc Vcc RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC3
RD0 RD1 RD2 RD3
Vcc
INT RES XOUT or XIN VSS
RE0 RE1 RE2 RE3 MFP
Vcc
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
INSTRUCTION SET TABLE
Symbol Description
ACC: ACC.n: WR: PAGE: MR0: MR1: PM0: PM1: PM2: PM3: PM4: PM5: PSR0: PSR2: R: R.n: I: L: CF: ZF: PC: TM0L: TM0H: TM1L: TM1H: TABL: TABH: IEF.n: HCF.n: HEF.n: SEF.n: PEF.n: Accumulator Accumulator bit n Working Register Page Register Mode Register 0 Mode Register 1 Port Mode 0 Port Mode 1 Port Mode 2 Port Mode 3 Port Mode 4 Port Mode 5 Port Status Register 0 Port Status Register 2 Memory (RAM) of address R Memory bit n of address R Constant parameter Branch or jump address Carry Flag Zero Flag Program Counter Low nibble of the Timer 0 counter High nibble of the Timer 0 counter Low nibble of the Timer 1 counter High nibble of the Timer 1 counter Low nibble of the look-up table address buffer High nibble of the look-up table address buffer Interrupt Enable Flag n HOLD mode release Condition Flag n HOLD mode release Enable Flag n STOP mode wake-up Enable Flag n Port Enable Flag n
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Preliminary W741C20X
Continued
EVF.n: ! =: &: ^: EX: : [PAGE*10H+()]: [P()]:
Event Flag n Not equal AND OR Exclusive OR Transfer direction, result Contents of address PAGE(bit2, bit1, bit0)*10H+() Contents of port P
INSTRUCTION SET TABLE 1
Mnemonic Arithmetic ADD ADD ADDR ADDR ADC ADC ADCR ADCR ADU ADU ADUR ADUR SUB SUB SUBR SUBR SBC SBC SBCR SBCR R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I ACC(R) + (ACC) ACC(WR) + I ACC, R(R) + (ACC) ACC, WR(WR) + I ACC(R) + (ACC) + (CF) ACC(WR) + I + (CF) ACC, R(R) + (ACC) + (CF) ACC, WR(WR) + I + (CF) ACC(R) + (ACC) ACC(WR) + I ACC, R(R) + (ACC) ACC, W R(WR) + I ACC(R) - (ACC) ACC(WR) - I ACC, R(R) - (ACC) ACC, WR(WR) - I ACC(R) - (ACC) - (CF) ACC(WR) - I - (CF) ACC, R(R) - (ACC) - (CF) ACC, WR(WR) - I - (CF) ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF ZF ZF ZF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Function Flag Affected Cycle
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 1, continued
Mnemonic INC DEC ANL ANL ANLR ANLR ORL ORL ORLR ORLR XRL XRL XRLR XRLR Branch JMP JB0 JB1 JB2 JB3 JZ JNZ JC JNC DSKZ DSKNZ SKB0 SKB1 SKB2 SKB3 L L L L L L L L L R R R R R R R R R, ACC WR, #I R, ACC W, R #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I R, ACC WR, #I
Function ACC, R(R) + 1 ACC, R(R) - 1 ACC(R) & (ACC) ACC(WR) & I ACC, R(R) & (ACC) ACC, WR(WR) & I ACC(R) (ACC) ACC(WR) I ACC, R(R) (ACC) ACC, WR(WR) I ACC(R) EX (ACC) ACC(WR) EX I ACC, R(R) EX (ACC) ACC, WR(WR) EX I PC10~PC0L10~L0 PC10~PC0L10~L0; if ACC.0 = "1" PC10~PC0L10~L0; if ACC.1 = "1" PC10~PC0L10~L0; if ACC.2 = "1" PC10~PC0L10~L0; if ACC.3 = "1" PC10~PC0L10~L0; if ACC = 0 PC10~PC0L10~L0; if ACC ! = 0 PC10~PC0L10~L0; if CF = "1" PC10~PC0L10~L0; if CF != "1" ACC, R(R) - 1; skip if ACC = 0 ACC, R(R) - 1; skip if ACC != 0 Skip if R.0 = "1" Skip if R.1 = "1" Skip if R.2 = "1" Skip if R.3 = "1"
Flag Affected ZF, CF ZF, CF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF
Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Logic Operations
ZF, CF ZF, CF
1 1 1 1 1 1
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Preliminary W741C20X
Instruction Set Table 1, continued
Mnemonic Data Move MOV MOV MOVA MOVA MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVA MOVA MOVA MOVA MOV MOV MOV MOV MOV SOP SIP MOV MOVA MOV MOV MOV WR, R R, WR WR, R R, WR R, ACC ACC, R R, #I WR, @R @R, WR TABL, R TABH, R R WR, #I R, RA R, RB R, RC R, RD RA, R RB, R RC, R RD, R RE, R R R MFP, #I R, PAGE PAGE, R MR0, #I MR1, #I WR(R) R(WR)
Function
Flag Affected
Cycle 1 1
ACC, WR(R) ACC, R(WR) R(ACC) ACC(R) RI WR[PR(bit2, bit1, bit0)x10H +(R)] [PR(bit2, bit1, bit0)x10H +(R)]WR TABL(R) TABH(R) R[TAB x 10H + (ACC)] WR[(I6 ~ I0) x 10H + (ACC)] ACC, R[RA] ACC, R[RB] ACC, R[RC] ACC, R[RD] [RA](R) [RB](R) [RC](R) [RD](R) [RE](R) RE0(R), (ACC); RE1CLK R, ACC SIB; RE3CLK [MFP] I ACC, RPAGE (Page Register) PAGE(R) MR0I MR1I
ZF ZF ZF
1 1 1 1 1 2 2 1 1 2 2
Input & Output ZF ZF ZF ZF 1 1 1 1 1 1 1 1 1 1 2 1 ZF 1 1 1 1
Flag & Register
- 35 -
Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 1, continued
Mnemonic MOV MOVA MOV MOVA MOVA CLR SET MOV MOV MOV MOV MOV MOV CLR MOV MOV MOV MOV MOVA CLR MOVA CLR SET CLR CLR CLR PAGE, #I R, CF CF, R R, HCFL R, HCFH PMF, #I PMF, #I PM0, #I PM1, #I PM2, #I PM3, #I PM4, #I PM5, #I EVF, #I PEF, #I IEF, #I HEF, #I SEF, #I R, PSR0 PSR0 R, PSR2 PSR2 CF CF DIVR0 WDT PAGEI
Function
Flag Affected
Cycle 1
ACC.0, R.0CF CF(R.0) ACC, RHCF0~HCF3 ACC, RHCF4~HCF7 Clear Parameter Flag if In = 1 Set Parameter Flag if In = 1 Port Mode 0 I Port Mode 1 I Port Mode 2 I Port Mode 3 I Port Mode 4 I Port Mode 5 I Clear Event Flag if In = 1 Set/Reset Port Enable Flag Set/Reset Interrupt Enable Flag Set/Reset HOLD mode release Enable Flag Set/Reset STOP mode wake-up Enable Flag for RC port ACC, RPort Status Register 0 Clear Port Status Register 0 ACC, RPort Status Register 2 Clear Port Status Register 2 Set Carry Flag Clear Carry Flag Clear the last 4-bit of the Divider 0 Clear WatchDog Timer
ZF CF ZF ZF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ZF
1 1
ZF
1 1
CF CF
1 1 1 1
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Preliminary W741C20X
Instruction Set Table 1, continued
Mnemonic Shift & Rotate SHRC R
Function
Flag Affected
Cycle
ACC.n, R.n(R.n+1); ACC.3, R.30; CFR.0
ZF, CF
1
RRC
R
ACC.n, R.n(R.n+1); ACC.3, R.3CF; CFR.0
ZF, CF
1
SHLC
R
ACC.n, R.n(R.n-1); ACC.0, R.00; CFR.3
ZF, CF
1
RLC
R
ACC.n, R.n(R.n-1); ACC.0, R.0CF; CFR.3
ZF, CF
1
Timer MOV MOV MOV MOV MOV MOV Subroutine CALL L STACK(PC)+1; PC10 ~ PC0L10 ~ L0 RTN Other HOLD STOP NOP EN DIS INT INT Enter Hold mode Enter Stop mode No Operation Enable Interrupt Function Disable Interrupt Function 1 1 1 1 1 (PC)STACK 1 1 TM0L, R TM0H, R TM0, #I TM1L, R TM1H, R TM1, #I TM0L(R) TM0H(R) Timer 0 set TM1L(R) TM1H(R) Timer 1 set 1 1 1 1 1 1
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
INSTRUCTION SET TABLE 2
ADC R, ACC Add R to ACC with CF
0 0 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: Flag Affected: ADC WR, #I 1
ACC (R) + (ACC) + (CF) The contents of the data memory location addressed by R6 to R0, ACC, and CF are binary added and the result is loaded into the ACC. CF & ZF Add immediate data to WR with CF
0 0 0 0 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0
Machine Code: Machine Cycle: Operation: Description: Flag Affected: ADCR R, ACC Machine Code: Machine Cycle: Operation: Description: 1 1
ACC (WR) + I + (CF) The contents of the Working Register (WR), I and CF are binary added and the result is loaded into the ACC. CF & ZF Add R to ACC with CF
0 0 0 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0
ACC, R (R) + (ACC) + (CF) The contents of the data memory location addressed by R6 to R0, ACC, and CF are binary added and the result is placed in the ACC and the data memory. CF & ZF
Flag Affected:
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Preliminary W741C20X
Instruction Set Table 2, continued
ADCR
WR, #I
Add immediate data to WR with CF
0 0 0 0 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0
Machine Code: Machine Cycle: Operation: Description: 1
ACC, WR (WR) + I + (CF) The contents of the Working Register (WR), I, CF are binary added and the result is placed in the ACC and the WR. CF & ZF Add R to ACC
0 0 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: ADD R, ACC
Machine Code: Machine Cycle: Operation: Description: 1
ACC (R) + (ACC) The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is loaded into the ACC. CF & ZF Add immediate data to WR
0 0 0 1 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: ADD WR, #I
Machine Code: Machine Cycle: Operation: Description: 1
ACC (WR) + I The contents of the Working Register (WR) and the immediate data I are binary added and the result is loaded into the ACC. CF & ZF
Flag Affected:
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
ADDR R, ACC Machine Code: Machine Cycle: Operation: Description: Flag Affected:
Add R to ACC
0 0 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0
1 ACC, R (R) + (ACC) The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is placed in the ACC and the data memory. CF & ZF
ADDR
WR, #I
Add immediate data to WR
0 0 0 1 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0
Machine Code: Machine Cycle: Operation: Description: 1
ACC, WR (WR) + I The contents of the Working Register (WR) and the immediate data I are binary added and the result is placed in the ACC and the WR. CF & ZF Add R to ACC and Carry Flag unchange
0 0 1 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: ADU R, ACC
Machine Code: Machine Cycle: Operation: Description: 1
ACC (R) + (ACC) The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is loaded into the ACC. ZF
Flag Affected:
- 40 -
Preliminary W741C20X
Instruction Set Table 2, continued
ADU
WR, #I
Add immediate data to WR and Carry Flag unchange
0 0 1 0 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0
Machine Code: Machine Cycle: Operation: Description: 1
ACC (WR) + I The contents of the Working Register (WR) and the immediate data I are binary added and the result is loaded into the ACC. ZF Add R to ACC and Carry Flag unchange
0 0 1 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: ADUR R, ACC Machine Code: Machine Cycle: Operation: Description:
1 ACC, R (R) + (ACC) The contents of the data memory location addressed by R6 to R0 and ACC are binary added and the result is placed in the ACC and the data memory. ZF Add immediate data to WR and Carry Flag unchange
0 0 1 0 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: ADUR WR, #I
Machine Code: Machine Cycle: Operation: Description: 1
ACC, WR (WR) + I The contents of the Working Register (WR) and the immediate data I are binary added and the result is placed in the WR and the ACC. ZF
Flag Affected:
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
ANL
R, ACC
And R to ACC
0 0 1 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
ACC (R) & (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are ANDed and the result is loaded into the ACC. ZF And immediate data to WR
0 0 1 0 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: ANL WR, #I
Machine Code: Machine Cycle: Operation: Description: 1
ACC (WR) & I The contents of the Working Register (WR) and the immediate data I are ANDed and the result is loaded into the ACC. ZF And R to ACC
0 0 1 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: ANLR R, ACC Machine Code: Machine Cycle: Operation: Description:
1 ACC, R (R) & (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are ANDed and the result is placed in the data memory and the ACC. ZF
Flag Affected:
- 42 -
Preliminary W741C20X
Instruction set table 2, continued
ANLR
WR, #I
And immediate data to WR
0 0 1 0 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0
Machine Code: Machine Cycle: Operation: Description: 1
ACC, WR (WR) & I The contents of the Working Register (WR) and the immediate data I are ANDed and the result is placed in the WR and the ACC. ZF Call subroutine
0 1 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Flag Affected: CALL L
Machine Code: Machine Cycle: Operation: 1
STACK (PC)+1; PC10 ~ PC0 L10 ~ L0 The next program counter (PC10 to PC0) is saved in the STACK and then the direct address (L10 to L0) is loaded into the program counter. A subroutine is called. Clear CF
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Description:
CLR
CF
Machine Code: Machine Cycle: Operation: Description: Flag Affected: 1
Clear CF Clear Carry Flag to 0. CF
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
CLR
DIVR0
Reset the last 4 bits of the DIVideR 0
0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0
Machine Code: Machine Cycle: Operation: Description: 1
Reset the last 4 bits of the divider 0 When this instruction is executed, the last 4 bits of the divider 0 (14 bits) are reset. Clear EVent Flag
0 1 0 0 0 0 0 0 I7 I6 I5 I4 I3 I2 I1 I0
CLR
EVF, #I
Machine Code: Machine Cycle: Operation: Description: 1
Clear event flag The condition corresponding to the data specified by I7 to I0 is controlled.
I0~I7 I0 = 1 I1 = 1 I2 = 1 I3 I4 = 1 I5 = 1 I6 = 1 I7 = 1 Mode after execution of instruction EVF0 caused by overflow from the divider 0 is reset. EVF1 caused by underflow from the timer 0 is reset. EVF2 caused by the signal change at port RC is reset. Reserved EVF4 caused by the falling edge signal on INT pin is reset. EVF5 caused by the serial port received completely. EVF6 caused by the serial port transmitted completely. EVF7 caused by underflow from the timer 1 is reset.
- 44 -
Preliminary W741C20X
Instruction Set Table 2, continued
CLR
PMF, #I
Clear ParaMeter Flag
0 0 0 1 0 1 1 0 1 0 0 0 I3 I2 I1 I0
Machine Code: Machine Cycle: Operation: Description: 1
Clear Parameter Flag Description of each flag: I0, I1, I2 : Reserved I3 = 1 : The input clock of the watchdog timer is Fosc/1024.
CLR
PSR0
Clear Port Status Register 0 (RC port signal change flag)
0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Machine Code: Machine Cycle: Operation: Description: 1
Clear Port Status Register 0 (RC port signal change flag) When this instruction is executed, the RC port signal change flag (PSR0) is cleared. Clear Port Status Register 2 (serial port status flags)
0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0
CLR
PSR2
Machine Code: Machine Cycle: Operation: Description: CLR WDT 1
Clear Port Status Register 2 (serial port status flags) When this instruction is executed, the serial port status flags (PSR2) are cleared. Reset the last 4 bits of the Watchdog Timer
0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0
Machine Code: Machine Cycle: Operation: Description: 1
Reset the last 4 bits of the watchdog timer When this instruction is executed, the last 4 bits of the watchdog timer are reset.
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
DEC
R
Decrement R content
0 1 0 0 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
ACC, R (R) - 1 Decrement the data memory content and load result into the ACC and the data memory. CF & ZF Disable Interrupt function
0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0
Flag Affected: DIS INT
Machine Code: Machine Cycle: Operation: Description: DSKNZ R 1
Disable interrupt function Interrupt function is inhibited by executing this instruction. Decrement R content then skip if ACC ! = 0
0 1 0 0 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: 1
ACC, R (R) - 1; PC (PC) + 2 if ACC ! = 0 Decrement the data memory content and load result into the ACC and the data memory. If ACC ! = 0, the program counter is incremented by 2 and produces a skip. CF & ZF
Description:
Flag Affected:
- 46 -
Preliminary W741C20X
Instruction Set Table 2, continued
DSKZ
R
Decrement R content then skip if ACC is zero
0 1 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: 1
ACC, R (R) - 1; PC (PC) + 2 if ACC = 0 Decrement the data memory content and load result into the ACC and the data memory. If ACC = 0, the program counter is incremented by 2 and produces a skip. CF & ZF Enable Interrupt function
0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0
Description:
Flag Affected: EN INT
Machine Code: Machine Cycle: Operation: Description: HOLD Machine Code: Machine Cycle: Operation: Description: 1 1
Enable interrupt function This instruction enables the interrupt function. Enter the HOLD mode
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Enter the HOLD mode The following two conditions cause the HOLD mode to be released. (1) An interrupt is accepted. (2) The HOLD release condition specified by the HEF is met. In HOLD mode, when an interrupt is accepted the HOLD mode will be released and the interrupt service routine will be executed. After completing the interrupt service routine by executing the RTN instruction, the C will enter HOLD mode again.
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
INC
R
Increment R content
0 1 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: Flag Affected: JB0 L 1
ACC, R (R) + 1 Increment the data memory content and load the result into the ACC and the data memory. CF & ZF Jump when bit 0 of ACC is "1"
1 0 0 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0; if ACC.0 = "1" If bit 0 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 0 of the ACC is "0," the program counter (PC) is incremented. Jump when bit 1 of ACC is "1"
1 0 0 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
JB1
L
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0; if ACC.1 = "1" If bit 1 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 1 of the ACC is "0," the program counter (PC) is incremented. Jump when bit 2 of ACC is "1"
1 0 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
JB2
L
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0; if ACC.2="1" If bit 2 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 2 of the ACC is "0," the program counter (PC) is incremented.
- 48 -
Preliminary W741C20X
Instruction Set Table 2, continued
JB3
L
Jump when bit 3 of ACC is "1"
1 0 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0; if ACC.3 = "1" If bit 3 of the ACC is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If bit 3 of the ACC is "0," the program counter (PC) is incremented. Jump when CF is "1"
1 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
JC
L
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0; if CF = "1" If CF is "1," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the CF is "0," the program counter (PC) is incremented. Jump absolutely
0 1 1 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
JMP
L
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0 PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and an unconditional jump occurs.
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
JNC
L
Jump when CF is not "1"
1 1 0 1 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0; if CF = "0" If CF is "0," PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If CF is "1," the program counter (PC) is incremented. Jump when ACC is not zero
1 1 0 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
JNZ
L
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0; if ACC ! = 0 If the ACC is not zero, PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the ACC is zero, the program counter (PC) is incremented. Jump when ACC is zero
1 1 1 0 0 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
JZ
L
Machine Code: Machine Cycle: Operation: Description: 1
PC10 ~ PC0 L10 ~ L0; if ACC = 0 If the ACC is zero, PC10 to PC0 of the program counter are replaced with the data specified by L10 to L0 and a jump occurs. If the ACC is not zero, the program counter (PC) is incremented.
- 50 -
Preliminary W741C20X
Instruction Set Table 2, continued
MOV ACC, R Machine Code: Machine Cycle: Operation: Description:
Move R content to ACC
0 1 0 0 1 1 1 0 1 R6 R5 R4 R3 R2 R1 R0
1 ACC (R) The contents of the data memory location addressed by R6 to R0 are loaded into the ACC. ZF
MOV
CF, R
Move R.0 content to CF
0 1 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
CF (R.0) The bit 0 content of the data memory location addressed by R6 to R0 is loaded into CF. CF
Flag Affected:
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOV HEF, #I Machine Code: Machine Cycle: Operation: Description:
Set/Reset Hold mode release Enable Flag
0 1 0 0 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0
1 Hold mode release enable flag control
I0~I7 I0 = 1 I1 = 1 Operation The HEF0 is set so that overflow from the divider 0 caused the HOLD mode to be released. The HEF1 is set so that underflow from the Timer 0 caused the HOLD mode to be released. The HEF2 is set so that signal change at port RC caused the HOLD mode to be released. Reserved The HEF4 is set so that the falling edge signal at the INT pin caused the HOLD mode to be released. The HEF5 is set so that the serial port received completely caused the HOLD mode to be released. The HEF6 is set so that the serial port transmitted completely caused the HOLD mode to be released. The HEF7 is set so that underflow from the Timer 1 caused the HOLD mode to be released.
I2 = 1 I3 I4 = 1 I5 = 1 I6 = 1 I7 = 1
- 52 -
Preliminary W741C20X
Instruction Set Table 2, continued
MOV
IEF, #I
Set/Reset Interrupt Enable Flag
0 1 0 1 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0
Machine Code: Machine Cycle: Operation: Description: 1
Interrupt Enable flag Control The interrupt enable flag corresponding to the data specified by I7 - I0 is controlled:
I0~I7 I0 = 1 I1 = 1 I2 = 1 I3 I4 = 1 I5 = 1 I6 = 1 Operation The IEF0 is set so that interrupt 0 (overflow from the divider 0) is accepted. The IEF1 is set so that interrupt 1 (underflow from the Timer 0) is accepted. The IEF2 is set so that interrupt 2 (signal change at port RC) is accepted. Reserved The IEF4 is set so that interrupt 4 (falling edge signal at the INT pin) is accepted. The IEF5 is set so that interrupt 5 (the serial port received completely) is accepted. The IEF6 is set so that interrupt 6 (the serial port transmitted completely) is accepted. The IEF7 is set so that interrupt 7 (underflow from the Timer 1) is accepted.
I7 = 1
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOV
MFP, #I
Modulation Frequency Pulse generator
0 0 0 1 0 0 1 0 I7 I6 I5 I4 I3 I2 I1 I0
Machine Code: Machine Cycle: Operation: Description: 1
[MFP] I If the bit 2 of MR1 is "0," the waveform specified by I7 to I0 is delivered at the MFP output pin (MFP). The relation between the waveform and immediate data I is shown as follows:
I5~I0 Signal I0 = 1 Fosc 256
I6 0 1 0 1
I1 = 1 Fosc 512
Signal Low High Fosc/16 Fosc/8
I2 = 1 Fosc 4096
I3 = 1 Fosc 8192
I4 = 1 Fosc 16384
I5 = 1 Fosc 32768
I7 0 0 1 1
MOV
MR0, #I
Load immediate data to Mode Register 0 (MR0)
0 0 0 1 0 0 1 1 1 0 0 0 I3 I2 I1 I0
Machine Code: Machine Cycle: Operation: Description: 1
MR0 I The immediate data I are loaded to the MR0. MR0 bits description:
bit 0 bit 1 bit 2 bit 3 = 0 The fundamental frequency of Timer 0 is Fosc/4 = 1 The fundamental frequency of Timer 0 is Fosc/1024 Reserved Reserved = 0 Timer 0 stop down-counting = 1 Timer 0 start down-counting
- 54 -
Preliminary W741C20X
Instruction Set Table 2, continued
MOV
MR1, #I
Load immediate data to Mode Register 1 (MR1)
0 0 0 1 0 0 1 1 0 0 0 0 I3 I2 I1 I0
Machine Code: Machine Cycle: Operation: Description: 1
MR1 I The immediate data I are loaded to the MR1. MR1 bit description:
bit0 = 0 The internal fundamental frequency of Timer 1 is Fosc = 1 The internal fundamental frequency of Timer 1 is Fosc/64 = 0 The fundamental frequency source of Timer 1 is internal clock = 1 The fundamental frequency source of Timer 1 is external clock via RC.0 input pin = 0 The specified waveform of the MFP generator is delivered at the MFP output pin = 1 The specified frequency of the Timer 1 is delivered at the MFP output pin = 0 Timer 1 stop down-counting = 1 Timer 1 start down-counting
bit1
bit2
bit3
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOV PAGE, #I Machine Code: Machine Cycle: Operation: Description:
Load immediate data to Page Register
0 1 0 1 0 1 1 0 1 0 0 0 I3 I2 I1 I0
1 Page Register I The immediate data I are loaded to the PR. Bit 3 is reserved. Bit 0, bit 1, and bit 2 indirect addressing mode preselect bits:
bit2 0 0 0 0 1 1 1 1 bit1 0 0 1 1 0 0 1 1 bit0 0 1 0 1 0 1 0 1 = Page 0 (00H~0FH) = Page 1 (10H~1FH) = Page 2 (20H~2FH) = Page 3 (30H~3FH) = Page 4 (40H~4FH) = Page 5 (50H~5FH) = Page 6 (60H~6FH) = Page 7 (70H~7FH)
MOV
PEF, #I
Set/Reset Port Enable Flag
0 1 0 0 0 0 1 1 0 0 0 0 I3 I2 I1 I0
Machine Code: Machine Cycle: Operation: Description: 1
Port enable flag control The data specified by I can cause HOLD mode to be released or an interrupt to occur. The signal change on port RC is specified.
I0~I7 I0 = 1 I1 = 1 I2 = 1 I3 = 1 Signal change at port RC RC0 RC1 RC2 RC3
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Preliminary W741C20X
Instruction Set Table 2, continued
MOV PM0, #I Machine Code: Machine Cycle: Operation: Description:
Set/Reset Port Mode 0 register
0 1 0 1 0 0 1 1 0 0 0 0 I3 I2 I1 I0
1 Set/Reset Port mode 0 register I0 = 0: RA port is CMOS type; I0 = 1: RA port is NMOS type. I1 = 0: RB port is CMOS type; I1 = 1: RB port is NMOS type. I2 = 0: RC port pull-high resistor is disabled; I2 = 1: RC port pull-high resistor is enabled. I3 = 0: RD port pull-high resistor is disabled; I3 = 1: RD port pull-high resistor is enabled. RA port independent Input/Output control
0 1 0 1 0 1 1 1 0 0 0 0 I3 I2 I1 I0
MOV PM1, #I Machine Code: Machine Cycle: Operation: Description:
1 RA port 4 pins input/output control is independent. I0 = 0: RA.0 is output pin; I0 = 1: RA.0 is input pin. I1 = 0: RA.1 is output pin; I1 = 1: RA.1 is input pin. I2 = 0: RA.2 is output pin; I2 = 1: RA.2 is input pin. I3 = 0: RA.3 is output pin; I3 = 1: RA.3 is input pin. Default condition RA port is input mode (PM = 1111B). RB port independent Input/Output control
0 1 0 1 0 1 1 1 1 0 0 0 I3 I2 I1 I0
MOV PM2, #I Machine Code: Machine Cycle: Operation: Description:
1 RB port 4 pins input/output control is independent. I0 = 0: RB.0 is output pin; I0 = 1: RB.0 is input pin. I1 = 0: RB.1 is output pin; I1 = 1: RB.1 is input pin. I2 = 0: RB.2 is output pin; I2 = 1: RB.2 is input pin. I3 = 0: RB.3 is output pin; I3 = 1: RB.3 is input pin. Default condition RB port is input mode (PM2 = 1111B).
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOV PM3, #I Machine Code: Machine Cycle: Operation: Description:
Set/Reset Port Mode 3 register
0 1 0 1 0 1 1 0 0 0 0 0 I3 I2 I1 I0
1 Set/Reset Port mode 3 register I0 is reserved. I1 = 0: The port RE is used as the output of the internal parallel port RT. I1 = 1: The port RE works as the serial input/output port. I2 is reserved. I3 = 0: Serial Tx rate = FOSC/2 I3 = 1: Serial Tx rate = FOSC/256 RC port independent Input/Output control
0 0 1 1 0 1 1 1 0 0 0 0 I3 I2 I1 I0
MOV PM4, #I Machine Code: Machine Cycle: Operation: Description:
1 RC port 4 pins input/output control is independent. I0 = 0: RC.0 is output pin; I0 = 1: RC.0 is input pin. I1 = 0: RC.1 is output pin; I1 = 1: RC.1 is input pin. I2 = 0: RC.2 is output pin; I2 = 1: RC.2 is input pin. I3 = 0: RC.3 is output pin; I3 = 1: RC.3 is input pin. Default condition RC port is input mode (PM4 = 1111B). RD port independent Input/Output control
0 0 1 1 0 1 1 1 1 0 0 0 I3 I2 I1 I0
MOV PM5, #I Machine Code: Machine Cycle: Operation: Description:
1 RD port 4 pins input/output control is independent. I0 = 0: RD.0 is output pin; I0 = 1: RD.0 is input pin. I1 = 0: RD.1 is output pin; I1 = 1: RD.1 is input pin. I2 = 0: RD.2 is output pin; I2 = 1: RD.2 is input pin. I3 = 0: RD.3 is output pin; I3 = 1: RD.3 is input pin. Default condition RD port is input mode (PM5 = 1111B).
- 58 -
Preliminary W741C20X
Instruction Set Table 2, continued
MOV
R, ACC
Move ACC content to R
0 1 0 1 1 0 0 1 1 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
R (ACC) The contents of the ACC are loaded to the data memory location addressed by R6 to R0. Input RA port data to ACC & R
0 1 0 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0
MOVA R, RA Machine Code: Machine Cycle: Operation: Description:
1 ACC , R [RA] The data on port RA are loaded into the data memory location addressed by R6 to R0 and the ACC. ZF Input RB port data to ACC & R
0 1 0 1 1 0 1 1 1 R6 R5 R4 R3 R2 R1 R0
Flag Affected: MOVA R, RB
Machine Code: Machine Cycle: Operation: Description: 1
ACC , R [RB] The data on port RB are loaded into the data memory location addressed by R6 to R0 and the ACC. ZF
Flag Affected:
- 59 -
Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOVA R, RC Machine Code: Machine Cycle: Operation: Description:
Input RC port data to ACC & R
0 1 0 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0
1 ACC , R [RC] The input data on the input port RC are loaded into the data memory location addressed by R6 to R0 and the ACC. ZF Input RD port data to ACC & R
0 1 0 0 1 0 1 1 1 R6 R5 R4 R3 R2 R1 R0
Flag Affected: MOVA R, RD Machine Code: Machine Cycle: Operation: Description:
1 ACC , R [RD] The input data on the input port RD are loaded into the data memory location addressed by R6 to R0 and the ACC. ZF Move WR content to R
1 1 1 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: MOV R, WR
Machine Code: Machine Cycle: Operation: Description: 1
R (WR) The contents of the WR are loaded to the data memory location addressed by R6 to R0.
- 60 -
Preliminary W741C20X
Instruction Set Table 2, continued
MOV
R, #I
Load immediate data to R
1 0 1 1 1 I3 I2 I1 I0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
RI The immediate data I are loaded to the data memory location addressed by R6 to R0. Output R content to RA port
0 1 0 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0
MOV
RA, R
Machine Code: Machine Cycle: Operation: Description: 1
[RA] (R) The data in the data memory location addressed by R6 to R0 are output to the port RA. Output R content to RB port
0 1 0 1 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0
MOV
RB, R
Machine Code: Machine Cycle: Operation: Description: 1
[RB] (R) The contents of the data memory location addressed by R6 to R0 are output to the port RB. Output R content to RC port
1 0 0 0 1 1 0 0 0 R6 R5 R4 R3 R2 R1 R0
MOV
RC, R
Machine Code: Machine Cycle: Operation: Description: 1
[RC] (R) The data in the data memory location addressed by R6 to R0 are output to the port RC.
- 61 -
Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOV
RD, R
Output R content to RD port
1 0 0 0 1 1 0 0 1 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
[RD] (R) The contents of the data memory location addressed by R6 to R0 are output to the port RD. Output R content to port RE
0 1 0 1 1 1 1 0 0 R6 R5 R4 R3 R2 R1 R0
MOV
RE, R
Machine Code: Machine Cycle: Operation: Description: 1
[RE] (R) The contents of the data memory location addressed by R6 to R0 are output to port RE. Set/Reset STOP mode waked-up Enable Flag for port RC
0 1 0 1 0 0 1 0 0 0 0 0 I3 I2 I1 I0
MOV SEF, #I Machine Code: Machine Cycle: Operation: Description:
1 Set/reset STOP mode wake-up enable flag for port RC The data specified by I cause a wake-up from the STOP mode. The fallingedge signal on port RC can be specified independently.
I0~I7 I0 = 1 I1 = 1 I2 = 1 I3 = 1 Falling edge signal at port RC RC0 RC1 RC2 RC3
- 62 -
Preliminary W741C20X
Instruction Set Table 2, continued
MOV TM0, #I Machine Code: Machine Cycle: Operation: Description: MOV TM0L, R Machine Code: Machine Cycle: Operation: Description:
Timer 0 set
0 0 0 1 0 0 0 0 I7 I6 I5 I4 I3 I2 I1 I0
1 Timer 0 set The data specified by I7 to I0 is loaded to the Timer 0 to start the timer. Move R content to TM0L
0 0 0 1 0 1 0 0 0 R6 R5 R4 R3 R2 R1 R0
1 TM0L (R) The content of the data memory location addressed by R6 to R0 are loaded into the TM0L. Move R content to TM0H
0 0 0 1 0 1 0 0 1 R6 R5 R4 R3 R2 R1 R0
MOV TM0H, R Machine code: Machine Cycle: Operation: Description:
1 TM0H (R) The content of the data memory location addressed by R6 to R0 are loaded into the TM0H. Timer 1 set
0 0 0 1 0 0 0 1 I7 I6 I5 I4 I3 I2 I1 I0
MOV TM1, #I Machine Code: Machine Cycle: Operation: Description:
1 Timer 1 set The data specified by I7 to I0 is loaded to the Timer 1 to start the timer.
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOV TM1L, R Machine Code: Machine Cycle: Operation: Description:
Move R content to TM1L
0 0 0 1 0 1 0 1 0 R6 R5 R4 R3 R2 R1 R0
1 TM1L (R) The content of the data memory location addressed by R6 to R0 are loaded into the TM1L. Move R content to TM1H
0 0 0 1 0 1 0 1 1 R6 R5 R4 R3 R2 R1 R0
MOV TM1H, R Machine code: Machine Cycle: Operation: Description:
1 TM1H (R) The content of the data memory location addressed by R6 to R0 are loaded into the TM1H. Move R content to WR
1 1 1 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0
MOV
WR, R
Machine Code: Machine Cycle: Operation: Description: 1
WR (R) The contents of the data memory location addressed by R6 to R0 are loaded to the WR. Indirect load from R to WR
1 1 0 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0
MOV
WR, @R
Machine Code: Machine Cycle: Operation: Description: 2
WR [PR (bit2, bit1, bit0) x 10H + (R)] The data memory contents of address [PR (bit2, bit1, bit0) x 10H + (R)] are loaded to the WR.
- 64 -
Preliminary W741C20X
Instruction Set Table 2, continued
MOV
@R, WR
Indirect load from WR to R
1 1 0 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 2
[PR (bit2, bit1, bit0) x 10H + (R)] WR The contents of the WR are loaded to the data memory location addressed by [PR (bit2, bit1, bit0) x 10H + (R)] . Move R content to Page Register
0 1 0 1 1 1 1 0 1 R6 R5 R4 R3 R2 R1 R0
MOV PAGE, R Machine Code: Machine Cycle: Operation: Description:
1 PR (R) The contents of the data memory location addressed by R6 to R0 are loaded to the PR. Move CF content to ACC.0 & R.0
0 1 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0
MOVA
R, CF
Machine Code: Machine Cycle: Operation: Description: 1
ACC.0, R.0 (CF) The content of CF is loaded to bit 0 of the data memory location addressed by R6 to R0 and the ACC. The other bits of the data memory and ACC are reset to "0." ZF
Flag Affected:
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOVA R, HCFH Machine Code: Machine Cycle: Operation: Description:
Move HCF4~7 to ACC & R
0 1 0 0 1 0 0 1 1 R6 R5 R4 R3 R2 R1 R0
1 ACC, R HCF4~7 The contents of HCF bit 4 to bit 7 (HCF4 to HCF7) are loaded to the data memory location addressed by R6 to R0 and the ACC. The ACC contents and the meaning of the bits after execution of this instruction are as follows:
Bit 0 Bit 1 Bit 2 Bit 3 HCF4: "1" when the HOLD mode is released by the falling edge signal at the INT pin. HCF5: "1" when the HOLD mode is released by underflow from Timer 1. HCF6: "1" when the HOLD mode is released by the serial port receiving completely. HCF7: "1" when the HOLD mode is released by the serial port transmitting completely.
Flag Affected: MOVA R, HCFL Machine Code: Machine Cycle: Operation: Description:
ZF Move HCF0~3 to ACC & R
0 1 0 0 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0
1 ACC, R HCF0~3 The contents of HCF bit 0 to bit 3 (HCF0 to HCF3) are loaded to the data memory location addressed by R6 to R0 and the ACC. The ACC contents and the meaning of the bits after execution of this instruction are as follows:
Bit 0 Bit 1 Bit 2 Bit 3 HCF0: "1" when the HOLD mode is released by overflow from the Divider 0. HCF1: "1" when the HOLD mode is released by underflow from Timer 0. HCF2: "1" when the HOLD mode is released by a signal change on port RC. Reserved.
Flag Affected:
ZF
- 66 -
Preliminary W741C20X
Instruction Set Table 2, continued
MOVA R, PAGE Machine Code: Machine Cycle: Operation: Description:
Move Page Register content to ACC & R
0 1 0 1 1 1 1 1 1 R6 R5 R4 R3 R2 R1 R0
1 ACC , R (Page Register) The contents of the Page Register (PR) are loaded to the data memory location addressed by R6 to R0 and the ACC. ZF Move Port Status Register 0 content to ACC & R
0 1 0 0 1 1 1 1 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: MOVA R, PSR0 Machine Code: Machine Cycle: Operation: Description:
1 ACC, R RC port signal change flag (PSR0) The contents of the RC port signal change flag (PSR0) are loaded to the data memory location addressed by R6 to R0 and the ACC. When the signal changes on any pin of the RC port, the corresponding signal change flag should be set to 1. Otherwise, it should be 0. ZF Move Port Status Register 0 content to ACC & R
0 1 0 1 1 1 1 1 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: MOVA R, PSR2 Machine Code: Machine Cycle: Operation: Description:
1 ACC, R Serial I/O port status flags (PSR2) The contents of the serial I/O port status flags (PSR2) are loaded to the data memory location addressed by R6 to R0 and the ACC. ZF
Flag Affected:
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
MOVA
R, WR
Move WR content to ACC & R
0 1 1 1 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
ACC, R (WR) The contents of the WR are loaded to the ACC and the data memory location addressed by R6 to R0. ZF Move R content to ACC & WR
0 1 1 0 1 W3 W2 W1 W0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: MOVA WR, R
Machine Code: Machine Cycle: Operation: Description: 1
ACC, WR (R) The contents of the data memory location addressed by R6 to R0 are loaded to the WR and the ACC. ZF Move R content to TABL
1 0 0 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: MOV TABL, R Machine Code: Machine Cycle: Operation: Description: MOV TABH, R Machine code: Machine Cycle: Operation: Description:
1 TABL (R) The content of the data memory location addressed by R6 to R0 are loaded into the TABL. Move R content to TABH
1 0 0 1 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0
1 TABH (R) The content of the data memory location addressed by R6 to R0 are loaded into the TABH.
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Preliminary W741C20X
Instruction Set Table 2, continued
MOVC R Machine code: Machine Cycle: Operation: Description:
Move look-up table ROM addressed by TABL and TABH to R
1 0 0 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0
2 WR [(TABH) x 10H + (TABL)] The contents of the look-up table ROM location addressed by TABH and TABL are loaded to R. No Operation
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NOP Machine Code: Machine Cycle: Operation: ORL R, ACC
1 No Operation OR R to ACC
0 0 1 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
ACC (R) (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are ORed and the result is loaded into the ACC. ZF OR immediate data to WR
0 0 1 1 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: ORL WR , #I
Machine Code: Machine Cycle: Operation: Description: 1
ACC (WR) I The contents of the Working Register (WR) and the immediate data I are ORed and the result is loaded into the ACC. ZF
Flag Affected:
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
ORLR R, ACC Machine Code: Machine Cycle: Operation: Description:
OR R to ACC
0 0 1 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0
1 ACC, R (R) (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are ORed and the result is placed in the data memory and the ACC. ZF OR immediate data to WR
0 0 1 1 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: ORLR WR , #I Machine Code: Machine Cycle: Operation: Description:
1 ACC, WR (WR) I The contents of the Working Register(WR) and the immediate data I are ORed and the result is placed in the WR and the ACC. ZF Rotate Left R with CF
0 1 0 0 1 1 0 0 1 R6 R5 R4 R3 R2 R1 R0
Flag Affected: RLC R
Machine Code: Machine Cycle: Operation: Description: 1
ACC.n, R.n (R.n-1); ACC.0, R.0 CF; CF R.3 The contents of the ACC and the data memory location addressed by R6 to R0 are rotated left one bit, bit 3 is rotated into CF, and CF rotated into bit 0 (LSB). The same contents are loaded into the ACC. CF & ZF
Flag Affected:
- 70 -
Preliminary W741C20X
Instruction Set Table 2, continued
RRC
R
Rotate Right R with CF
0 1 0 0 1 1 0 1 1 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
ACC.n, R.n (R.n+1); ACC.3, R.3 CF; CF R.0 The contents of the ACC and the data memory location addressed by R6 to R0 are rotated right one bit, bit 0 is rotated into CF, and CF is rotated into bit 3 (MSB). The same contents are loaded into the ACC. CF & ZF Return from subroutine
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Flag Affected: RTN Machine Code: Machine Cycle: Operation: Description:
1 (PC) STACK The program counter (PC10 to PC0) is restored from the stack. A return from a subroutine occurs. Subtract ACC from R with Borrow
0 0 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0
SBC
R, ACC
Machine Code: Machine Cycle: Operation: Description: 1
ACC (R) - (ACC) - (CF) The contents of the ACC and CF are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is loaded into the ACC. CF & ZF
Flag Affected:
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
SBC
WR, #I
Subtract immediate data from WR with Borrow
0 0 0 0 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0
Machine Code: Machine Cycle: Operation: Description: 1
ACC (WR) - I - (CF) The immediate data I and CF are binary subtracted from the contents of the WR and the result is loaded into the ACC. CF & ZF Subtract ACC from R with Borrow
0 0 0 0 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: SBCR R, ACC Machine Code: Machine Cycle: Operation: Description:
1 ACC, R (R) - (ACC) - (CF) The contents of the ACC and CF are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is placed in the ACC and the data memory. CF & ZF Subtract immediate data from WR with Borrow
0 0 0 0 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: SBCR WR, #I
Machine Code: Machine Cycle: Operation: Description: 1
ACC, R (WR) - I - (CF) The immediate data I and CF are binary subtracted from the contents of the WR and the result is placed in the ACC and the WR. CF & ZF
Flag Affected:
- 72 -
Preliminary W741C20X
Instruction Set Table 2, continued
SET
CF
Set CF
0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0
Machine Code: Machine Cycle: Operation: Description: Flag Affected: SET PMF, #I 1
Set CF Set Carry Flag to 1. CF Set ParaMeter Flag
0 0 0 1 0 1 1 0 0 0 0 0 I3 I2 I1 I0
Machine Code: Machine Cycle: Operation: Description: 1
Set Parameter Flag Description of each flag: I0, I1, I2 : Reserved I3 = 1 : The input clock of the watchdog timer is Fosc/16384.
SHLC
R
SHift Left R with CF and LSB = 0
0 1 0 0 1 1 0 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
ACC.n, R.n (R.n-1); ACC.0, R.0 0; CF R.3 The contents of the ACC and the data memory location addressed by R6 to R0 are shifted left one bit, but bit 3 is shifted into CF, and bit 0 (LSB) is replaced with "0." The same contents are loaded into the ACC. CF & ZF
Flag Affected:
- 73 -
Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
SHRC
R
SHift Right R with CF and MSB = 0
0 1 0 0 1 1 0 1 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
ACC.n, R.n (R.n+1); ACC.3, R.3 0; CF R.0 The contents of the ACC and the data memory location addressed by R6 to R0 are shifted right one bit, but bit 0 is shifted into CF, and bit 3 (MSB) is replaced with "0." The same contents are loaded into the ACC. CF & ZF If bit 0 of R is equal to 1 then skip
1 0 0 0 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: SKB0 R
Machine Code: Machine Cycle: Operation: Description: 1
PC (PC) + 2; if R.0 = 1"1" If bit 0 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 0 of R is not equal to 1, the program counter (PC) is incremented. If bit 1 of R is equal to 1 then skip
1 0 0 0 1 0 0 0 1 R6 R5 R4 R3 R2 R1 R0
SKB1
R
Machine Code: Machine Cycle: Operation: Description: 1
PC (PC) + 2; if R.1 = 1"1" If bit 1 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 1 of R is not equal to 1, the program counter (PC) is incremented.
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Preliminary W741C20X
Instruction Set Table 2, continued
SKB2
R
If bit 2 of R is equal to 1 then skip
1 0 0 0 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
PC (PC) + 2; if R.2 = 1"1" If bit 2 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 2 of R is not equal to 1. The program counter (PC) is incremented. R If bit 3 of R is equal to 1 then skip
1 0 0 0 1 0 1 0 1 R6 R5 R4 R3 R2 R1 R0
SKB3
Machine Code: Machine Cycle: Operation: Description: 1
PC (PC) + 2; if R.3 = 1"1" If bit 3 of R is equal to 1, the program counter is incremented by 2 and a skip is produced. If bit 3 of R is not equal to 1, the program counter (PC) is incremented. Enter the STOP mode
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
STOP Machine Code: Machine Cycle: Operation: Description:
1 STOP oscillator Device enters STOP mode. When the falling edge signal of RC port is accepted, the C will wake up and execute the next instruction.
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
SUB
R, ACC
Subtract ACC from R
0 0 0 1 1 0 1 0 0 R6 R5 R4 R3 R2 R1 R0
Machine Code: Machine Cycle: Operation: Description: 1
ACC (R) - (ACC) The contents of the ACC are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is loaded into the ACC. CF & ZF Subtract immediate data from WR
0 0 0 1 1 1 1 0 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: SUB WR , #I
Machine Code: Machine Cycle: Operation: Description: 1
ACC (WR) - I The immediate data I are binary subtracted from the contents of the WR and the result is loaded into the ACC. CF & ZF Subtract ACC from R
0 0 0 1 1 0 1 1 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: SUBR R, ACC Machine Code: Machine Cycle: Operation: Description:
1 ACC, R (R) - (ACC) The contents of the ACC are binary subtracted from the contents of the data memory location addressed by R6 to R0 and the result is placed in the ACC and the data memory. CF & ZF
Flag Affected:
- 76 -
Preliminary W741C20X
Instruction Set Table 2, continued
SUBR
WR, #I
Subtract immediate data from WR
0 0 0 1 1 1 1 1 I3 I2 I1 I0 W3 W2 W1 W0
Machine Code: Machine Cycle: Operation: Description: 1
ACC, WR (WR) - I The immediate data I are binary subtracted from the contents of the WR and the result is placed in the ACC and the WR. CF & ZF Exclusive OR R to ACC
0 0 1 1 1 0 0 0 0 R6 R5 R4 R3 R2 R1 R0
Flag Affected: XRL R, ACC
Machine Code: Machine Cycle: Operation: Description: 1
ACC (R) EX (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are exclusive-ORed and the result is loaded into the ACC. ZF Exclusive OR immediate data to WR
0 0 1 1 1 1 0 0 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: XRL WR, #I
Machine Code: Machine Cycle: Operation: Description: 1
ACC (WR) EX I The contents of the Working Register (WR) and the immediate data I are exclusive-ORed and the result is loaded into the ACC. ZF
Flag Affected:
- 77 -
Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
Instruction Set Table 2, continued
XRLR R, ACC Machine Code: Machine Cycle: Operation: Description:
Exclusive OR R to ACC
0 0 1 1 1 0 0 1 0 R6 R5 R4 R3 R2 R1 R0
1 ACC, R (R) EX (ACC) The contents of the data memory location addressed by R6 to R0 and the ACC are exclusive-ORed and the result is placed in the data memory and the ACC. ZF Exclusive OR immediate data to WR
0 0 1 1 1 1 0 1 I3 I2 I1 I0 W3 W2 W1 W0
Flag Affected: XRLR WR, #I
Machine Code: Machine Cycle: Operation: Description: 1
ACC, WR (WR) EX I The contents of the Working Register(WR) and the immediate data I are exclusive-ORed and the result is placed in the WR and the ACC. ZF
Flag Affected:
- 78 -
Preliminary W741C20X
PACKAGE DIMENSIONS
18L PDIP-300mil
D
18 10
1
E
1
9
S
2
E c
1
AA L B B1 e1
A
Base Plane
Seating Plane
\
eA
Dimension in inches Symbol
Dimension in mm
Min. Nom
0.010 0.125 0.016 0.058 0.008 0.130 0.018 0.060 0.010 0.900 0.290 0.245 0.090 0.120 0 0.335 0.355 0.300 0.250 0.100 0.130
Max.
0.175
Min. Nom
0.25
Max.
4.45
A A1 A2 B B1 c D E E1 e1 L \ eA S
0.135 0.022 0.064 0.014 0.910 0.310 0.255 0.110 0.140 15 0.375 0.055
3.18 0.41 1.47 0.20
3.30 0.46 1.52 0.25 22.86
3.43 0.56 1.63 0.36 23.11 7.87 6.48 2.79 3.56 15
7.37 6.22 2.29 3.05 0 8.51
7.62 6.35 2.54 3.30
9.02
9.53 1.40
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
20L PDIP
D
20 11
E
1
1
10
S AA L B B1 e1
2
E c A
1
Base Plane
Seating Plane
\
eA
Dimension in inches Symbol
Dimension in mm
Min.
0.010 0.125 0.016 0.058 0.008
Nom
Max.
0.175
Min. Nom
0.25
Max.
4.45
A A1 A2 B B1 c D E E1 e1 L
\
0.130 0.018 0.060 0.010 1.026
0.135 0.022 0.064 0.014 1.040 0.310 0.255 0.110 0.140 15
3.18 0.41 1.47 0.20
3.30 0.46 1.52 0.25 20.06
3.43 0.56 1.63 0.36 26.42 7.87 6.48 2.79 3.56 15
0.290 0.245 0.090 0.120 0 0.335
0.300 0.250 0.100 0.130
7.37 6.22 2.29 3.05 0 8.51
7.62 6.35 2.54 3.30
eA S
0.355
0.375 0.075
9.02
9.53 1.91
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Preliminary W741C20X
28-Lead P-DIP Skinny
D
28 15
E1
1
14
S
E
Base Plane
A A2 L A1
c
Mounting Plane
B B1 e1 a eA
Dimension in Inches
Dimension in mm
Symbol
Min.
Nom
Max.
0.175
Min.
Nom
Max.
4.45
A A1 A2 B B1 c D E E1 e1 L
a
0.010 0.125 0.016 0.058 0.008 0.130 0.018 0.060 0.010 1.388 0.300 0.283 0.090 0.120 0 0.330 0.350 0.310 0.288 0.100 0.130 0.135 0.022 0.064 0.014 1.400 0.320 0.293 0.110 0.140 15 0.370 0.055
0.25 3.18 0.41 1.47 0.20 3.30 0.46 1.52 0.25 35.26 7.62 7.19 2.29 3.05 0 8.38 8.89 7.87 7.32 2.54 3.30 3.43 0.56 1.63 0.36 35.56 8.13 7.44 2.79 3.56 15 9.40 1.40
eA S
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
20L SOP-300mil
20
11
c
E
HE
L
1
D
10
0.25 O
A Y SEATING PLANE b e A1 GAUGE PLANE
Control demensions are in milmeters .
Symbol A A1 b c E D e HE Y L q Dimension in mm Min. 2.35 0.10 0.33 0.23 Max. 2.65 0.30 0.51 Dimension in inches Min. 0.093 0.004 0.013 0.009 0.291 0.496 Max. 0.104 0.012 0.020
0.32 7.40 7.60 13.00 12.60 1.27 BSC 10.65 10.00 0.10 1.27 0.40 0 8
0.013 0.299 0.512 0.050 BSC 0.394 0.419 0.004 0.016 0.050 0 8
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Preliminary W741C20X
28L SOP-300mil
28
15
c
E
HE
L
1
D
14
0.25 O
A Y SEATING PLANE b e A1 GAUGE PLANE
Control demensions are in milmeters .
Symbol A A1 b c E D e HE Y L q Dimension in mm Min. 2.35 0.10 0.33 0.23 Max. 2.65 0.30 0.51 Dimension in inches Min. Max. 0.093 0.104 0.012 0.004 0.013 0.020 0.009 0.013 0.291 0.299 0.697 0.713 0.050 BSC 0.394 0.419 0.004 0.016 0.050 0 8
0.32 7.40 7.60 17.70 18.10 1.27 BSC 10.65 10.00 0.10 0.40 1.27 0 8
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Publication Release Date: March 1998 Revision A3
Preliminary W741C20X
NOTES:
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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