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(R)
74VHCT174A
HEX D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
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HIGH SPEED: fMAX =150 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (Max.)
SOP
PACKAGE SOP TSSOP T UBE 74VHCT174AM
TSSOP
T&R 74VHCT174AMTR 74VHCT174ATTR
ORDER CODES
DESCRIPTION The 74VHCT174A is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are
transfered to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 2000
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INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2,5, 7,10, 12, 15 3,4, 6,11, 13, 14 9 SYMBOL CLEAR Q0 to Q5 D0 to D5 CLOCK NAME AND FUNCT ION Asyncronous Master Reset (Active LOW) Flip-Flop Outputs Data Inputs Clock Input (LOW-to-HIGH, EdgeTriggered) Ground (0V) Positive Supply Voltage
8 16
GND VCC
TRUTH TABLE
INPUTS CL EAR L H H H
X:Don't Care
OUT PUT S CLO CK X Q L L H Qn
F UNCTIO N CLEAR
D X L H X
NO CHANGE
LOGIC DIAGRAM
Thislogic diagram has notbe used to estimate propagation delays
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO ICC orIGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current DC VCC or Ground Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V V mA mA mA mA
o o
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) VCC=0 2) High or Low State
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (V CC = 5.0 0.5V) Parameter Valu e 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 to 20 Unit V V V V
o
C
ns/V
1) VCC=0 2) High or Low State 3)VIN from0.8V to 2 V
DC SPECIFICATIONS
Symb ol Parameter T est Cond ition s V CC (V) VIH VIL VOH VOL II ICC ICC High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 IO=-50 A IO=-8 mA IO=50 A IO=8 mA VI = 5.5V or GND VI = VCC orGND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V 4.4 3.94 0.0 0.1 0.36 0.1 4 1.35 4.5 Min. 2 0.8 4.4 3.8 0.1 0.44 1.0 40 1.5 Typ . Value T A = 25 o C Max. -40 to 85 o C Min . 2 0.8 Max. V V Un it
V V A A mA
IOPD
0
0.5
5.0
A
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AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
Symb ol Parameter V CC (V) tPLH tPHL tPHL Propagation Delay Time CK to Q Propagation Delay Time CLR to Q CLR pulse Width LOW CK pulse Width HIGH or LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Removal Time CLR to CK Maximum Clock Frequency 5.0(*) 5.0(*) 5.0(*) 5.0
(*)
Test Co ndition CL (pF ) 15 50 15 50
Value T A = 25 o C Min. Typ . Max. 7.2 11.0 9.7 7.4 9.9 14.5 11.4 14.9 5.0 5.0 5.0 0.0 3.0
Un it -40 to 85 o C Min . Max. 1.0 13.0 1.0 1.0 1.0 16.5 13.5 17.0 5.0 5.0 6.0 0.0 3.0 80 50 ns ns
tw tw ts th tREM fMAX
5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 15 50 95 55 150 85
ns ns ns ns ns MHz
(*) Voltage range is 5V 0.5V
CAPACITIVE CHARACTERISTICS
Symb ol Parameter T est Cond ition s
o
Value T A = 25 C Min. Typ . 4 29 Max. 10 -40 to 85 C Min . Max. 10
o
Un it
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
pF pF
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/6 (per Flip-Flop)
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DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter T est Cond ition s V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 -0.8 5.0 5.0 CL = 50 pF 2.0 0.8 Min. Typ . 0.3 -0.3 V Value T A = 25 o C Max. 0.8 -40 to 85 o C Min . Max. Un it
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n -1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
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WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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74VHCT174A
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 3: REMOVAL TIME (f=1MHz; 50% duty cycle)
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SO-16 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
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TSSOP16 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 4.9 6.25 4.3 5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.20 5.1 6.5 4.48 0.002 0.335 0.0075 0.0035 0.193 0.246 0.169 0.197 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.201 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com .
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