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INTEGRATED CIRCUITS
74ALVT16601 18-bit universal bus transceiver (3-State)
Product specification Supersedes data of 1996 Nov 14 IC23 Data Handbook 1998 Feb 13
Philips Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
FEATURES
* 18-bit bidirectional bus interface * 5V I/O Compatible * 3-State buffers * Output capability: +64mA/-32mA * TTL input and output switching levels * Input and output interface capability to systems at 5V supply * Bus-hold data inputs eliminate the need for external pull-up * Live insertion/extraction permitted * Power-up reset * Power-up 3-State * No bus current loading when output is tied to 5V bus * Positive edge triggered clock inputs * Latch-up protection exceeds 500mA per JEDEC Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model resistors to hold unused inputs
DESCRIPTION
The 74ALVT16601 is a high-performance BiCMOS product designed for VCC operation at 2.5V and 3.3V with I/O compatibility up to 5V. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Input capacitance (Control pins) I/O pin capacitance Total supply current CL = 50pF VI = 0V or VCC Outputs disabled; VI/O = 0V or VCC Outputs disabled CONDITIONS Tamb = 25C TYPICAL UNIT 2.5V 1.9 2.5 4 8 40 3.3V 1.5 1.9 4 8 60 ns pF pF A
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ALVT16601 DL 74ALVT16601 DGG NORTH AMERICA AV16601 DL AV16601 DGG DWG NUMBER SOT371-1 SOT364-1
PIN DESCRIPTION
PIN NUMBER 1, 27 29, 56 2, 28 55,30 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL OEAB/OEBA CEBA/CEAB LEAB/LEBA CPAB/CPBA A0-A17 B0-B17 GND VCC NAME AND FUNCTION A-to-B/ B-to-A Output enable input (active Low) B-to-A/A-to-B clock enable A-to-B/B-to-A Latch enable input A-to-B/B-to-A Clock input (active rising edge) Data inputs/outputs (A side) Data inputs/outputs (B side) Ground (0V) Positive supply voltage
1998 Feb 13
2
853-1885 18958
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
PIN CONFIGURATION
OEAB LEAB A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CEAB CPAB B0 GND B1 B2 VCC B3 B4 B5 GND B6 B7 B8 B9 B10 B11 GND B12 B13 B14 VCC B15 B16 GND B17 CPBA CEBA
FUNCTION TABLE
INPUTS CEAB X X X H L L L L X= H= L= = Z= = OEAB H L L L L L L L LEAB X H H L L L L L CPAB X X X X H L A X L H X L H X X OUTPUT B Z L H BO L H BO BO
Don't care High voltage level Low voltage level Low to High High impedance "off " state A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CPBA, and CEBA. = Output level before the indicated steady-state input conditions were established. = Output level before the indicated steady-state input conditions were established, provided that CPAB was Low before LEAB went Low.
SW00192
1998 Feb 13
3
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
LOGIC SYMBOL (Positive Logic)
OEAB 1
CEAB
56
CPAB
55
LEAB
2
LEBA
28
CPBA
30
CEBA
29
OEBA
27 CE
A0
3
ID C1 CLK CE ID C1 CLK
54
B0
To 17 other channels
SW00193
ABSOLUTE MAXIMUM RATINGS 1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 Output in Off or High state Output in Low state DC output current out ut Output in High state Storage temperature range -64 -65 to +150 C VI < 0 CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +7.0 -50 -0.5 to +7.0 128 mA UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
1998 Feb 13
4
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1kHz Input transition rise or fall rate; Outputs enabled Operating free-air temperature range -40 PARAMETER 2.5V RANGE LIMITS MIN 2.3 0 1.7 0.7 -8 8 24 10 +85 -40 MAX 2.7 5.5 3.3V RANGE LIMITS MIN 3.0 0 2.0 0.8 -32 32 64 10 +85 MAX 3.6 5.5 UNIT V V V V mA mA ns/V C
DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE)
LIMITS SYMBOL VIK VOH PARAMETER Input clamp voltage High-level out ut voltage output TEST CONDITIONS VCC = 3.0V; IIK = -18mA VCC = 3.0 to 3.6V; IOH = -100A VCC = 3.0V; IOH = -32mA VCC = 3.0V; IOL = 100A VOL Low-level out ut voltage output VCC = 3.0V; IOL = 16mA VCC = 3.0V; IOL = 32mA VCC = 3.0V; IOL = 64mA VRST Power-up output low voltage6 VCC = 3.6V; IO = 1mA; VI = VCC or GND VCC = 3.6V; VI = VCC or GND VCC = 0 or 3.6V; VI = 5.5V II Input leakage current VCC = 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 0V IOFF IHOLD Off current Bus Hold current Data inputs7 Current into an output in the High state when VO > VCC Power up/down 3-State output current3 Quiescent supply current Additional supply current per input pin2 VCC = 0V; VI or VO = 0 to 4.5V VCC = 3V; VI = 0.8V VCC = 3V; VI = 2.0V VCC = 0V to 3.6V; VCC = 3.6V VO = 5.5V; VCC = 3.0V VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC OE = Don't care VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND 75 -75 500 10 1.0 0.06 3.5 0.06 0.04 125 100 0.1 5 0.1 0.4 mA mA A A Data pins4 Control pins 0.1 0.1 0.1 0.5 0.1 0.1 130 -140 A VCC-0.2 2.0 Temp = -40C to +85C MIN TYP1 -0.85 VCC 2.3 0.07 0.25 0.3 0.4 0.2 0.4 0.5 0.55 0.55 1 10 20 10 -5 100 A A V V MAX -1.2 V V UNIT
IEX IPU/PD ICCH ICCL ICCZ ICC
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V 0.3V a transition time of 100sec is permitted. This parameter is valid for Tamb = 25C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 13
5
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
AC CHARACTERISTICS (3.3V "0.3V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay An to Bn or Bn to An Propagation delay Clock Low or High LEAB to Bn or LEBA to An Propagation delay CPAB to Bn or CPBA to An Output enable time to High and Low level Output disable time from High and Low Level 1 2 3 1 5 6 5 6 1.0 1.0 1.5 1.5 1.5 1.5 1.0 1.0 1.5 1.5 1.5 1.9 2.2 2.6 2.2 2.9 2.3 1.6 2.9 2.4 2.3 2.9 3.5 3.9 3.3 4.1 3.9 2.8 4.1 3.6 VCC = 3.3V 0.3V TYP1 MAX MHz ns ns ns ns ns UNIT
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC SETUP REQUIREMENTS (3.3V "0.3V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V 0.3V MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) Setup time, High or Low An to CPAB or Bn to CPBA Hold time, High or Low An to CPAB or Bn to CPBA Setup time, High or Low Clock Low An to LEAB or Bn to LEBA Hold time, High or Low Clock High An to LEAB or Bn to LEBA Setup time CEAB before CPAB or CEBA before CPBA Hold time CEAB after CPAB or CEBA after CPBA Pulse width, High or Low CPAB or CPBA LEAB or LEBA pulse width, High 4 4 4 4 1.5 1.5 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.0 1.5 1.0 2.0 2.0 1.5 TYP1 0.4 0.6 -0.5 -0.3 -0.5 -0.1 0.1 0.5 0.3 -0.4 0.7 -0.3 ns ns ns ns UNIT
4
ns
4
ns
1 3
ns ns
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
1998 Feb 13
6
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
DC ELECTRICAL CHARACTERISTICS (2.5V "0.2V RANGE)
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIK VOH Input clamp voltage High-level out ut voltage output VCC = 2.3V; IIK = -18mA VCC = 2.3 to 3.6V; IOH = -100A VCC = 2.3V; IOH = -8mA VCC = 2.3V; IOL = 100A VOL VRST Low-level output voltage Power-up output low voltage7 VCC = 2.3V; IOL = 24mA VCC = 2.3V; IOL = 8mA VCC = 2.7V; IO = 1mA; VI = VCC or GND VCC = 2.7V; VI = VCC or GND VCC = 0 or 2.7V; VI = 5.5V II Input leakage current VCC = 2.7V; VI = 5.5V VCC = 2.7V; VI = VCC VCC = 2.7V; VI = 0 IOFF IHOLD Off current Bus Hold current Data inputs6 IEX IPU/PD ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Current into an output in the High state when VO > VCC Power up/down 3-State output current3 VCC = 0V; VI or VO = 0 to 4.5V VCC = 2.3V; VI = 0.7V VCC = 2.3V; VI = 1.7V VO = 5.5V; VCC = 2.3V VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE = Don't care VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0 VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO VCC = 2.3V to 2.7V; One input at VCC-0.6V, Other inputs at VCC or GND = 05 Data pins4 Control pins 0.1 0.1 0.1 0.1 0.1 0.1 90 -75 10 1 0.04 2.5 0.04 0.01 125 100 0.1 4.5 0.1 0.4 mA mA VCC-0.2 1.8 0.07 0.3 0.2 0.5 0.4 0.55 1 10 20 10 -5 "100 A A A A A V V TYP1 -0.85 MAX -1.2 V V UNIT
NOTES: 1. All typical values are at VCC = 2.5V and Tamb = 25C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V 0.2V a transition time of 100sec is permitted. This parameter is valid for Tamb = 25C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. Not guaranteed. 7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
1998 Feb 13
7
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
AC CHARACTERISTICS (2.5V "0.2V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay An to Bn or Bn to An Propagation delay Clock Low or High LEAB to Bn or LEBA to An Propagation delay CPAB to Bn or CPBA to An Output enable time to High and Low level Output disable time from High and Low Level 1 2 3 1 5 6 5 6 1.0 1.0 2.0 2.0 2.0 2.0 2.0 1.0 1.5 1.0 1.9 2.5 3.1 3.5 3.4 4.0 3.3 2.1 2.6 1.9 3.0 3.7 4.6 5.2 5.0 5.9 4.8 3.2 4.2 3.4 VCC = 2.5V 0.2V TYP1 MAX MHz ns ns ns ns ns UNIT
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC SETUP REQUIREMENTS (2.5V "0.2V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.5V 0.2V MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) Setup time, High or Low An to CPAB or Bn to CPBA Hold time, High or Low An to CPAB or Bn to CPBA Setup time, High or Low Clock Low or High An to LEAB or Bn to LEBA Hold time, High or Low Clock Low or High An to LEAB or Bn to LEBA Setup time CEAB before CPAB or CEBA before CPBA Hold time CEAB after CPAB or CEBA after CPBA Pulse width, High or Low CPAB or CPBA LEAB or LEBA pulse width, High 4 4 4 4 2.0 2.0 0.0 0.0 0.0 1.5 1.5 1.9 1.0 0.3 2.0 0.5 3.0 3.0 1.5 TYP1 0.4 1.2 -1.1 -0.3 -1.0 0.4 0.4 1.0 0.3 -0.4 0.4 -0.1 ns ns ns ns UNIT
4
ns
4
ns
1 3
ns ns
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
1998 Feb 13
8
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
AC WAVEFORMS
NOTES: 1. VM = 1.5V at VCC w 3.0V, VM = VCC/2 at VCC v 2.7V 2. VX = VOL + 0.3V at VCC w 3.0V, VX = VOL + 0.150V . VCC at VCC v 2.7V 3. VY = VOH - 0.3V at VCC w 3.0V, VY = VOH - 0.150V . VCC at VCC v 2.7V
CPBA or CPAB
VM
VM
3.0V or VCC, whichever is less
nAx, nBx CEAB CEBA
0V tW(L) tPHL An or Bn VM tW(H) tPLH VOH VM VOL
LEAB or LEBA
CPAB or CPBA
SW00181
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
OEBA or OEAB
An or Bn
VM
VM
3.0V or VCC, whichever is less 0V
tPLH
tPHL VOH VM VM VOL An or Bn
An or Bn
SW00176
Waveform 2. Propagation Delay, Transparent Mode
3.0V or VCC, whichever is less
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
LEAB or LEBA
VM
VM
VM
0V tW(H) tPHL VOH An or Bn VM VM VOL tPLH
OEBA or OEAB
An or Bn
SW00177
Waveform 3. Propagation Delay, Enable to Output, and Enable Pulse Width
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
1998 Feb 13
9
EEE EEEE EEE EEE EEEE EEE EEE EEEE EEE
VM VM VM VM tS(H) th(H) tS(L) th(L) VM VM
1/fMAX
3.0V or VCC whichever is less 0V
3.0V or VCC whichever is less
0V
SW00272
Waveform 4. Data Setup and Hold Times
VM
VM
3.0V or VCC, whichever is less 0V
tPZH
tPHZ VOH VM VY
0V
SW00273
VM
VM
3.0V or VCC, whichever is less
0V tPZL tPLZ 3.0V or VCC VM VX VOL
SW00274
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
74ALVT16601
TEST CIRCUIT
VCC
6.0V or VCC x 2 90%
tW VM 10% tTHL (tF) 10% VM
90%
VIN
Open
VIN PULSE GENERATOR RT D.U.T. CL RL VOUT RL
GND
NEGATIVE PULSE
0V tTLH (tR) tTHL (tF) VIN VM 10% tW 0V
tTLH (tR) 90% 90% POSITIVE PULSE 10%
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPLZ/tPZL tPLH/tPHL tPHZ/tPZH SWITCH 6V or VCC x 2 Open GND INPUT PULSE REQUIREMENTS FAMILY Amplitude Rep. Rate tW 500ns tR tF
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
74ALVT16
3.0V or VCC whichever v10MHz is less
v2.5ns v2.5ns
SW00220
1998 Feb 13
10
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVT16601
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1998 Feb 13
11
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVT16601
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Feb 13
12
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVT16601
NOTES
1998 Feb 13
13
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVT16601
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03571
Philips Semiconductors
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