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| US1260 DUAL 6A AND 1A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR FEATURES Guaranteed <1.3V Dropout at 6A (output #2) Guaranteed <0.6V Dropout at 1A (output #1) Fast Transient Response 1% Voltage Reference Initial Accuracy Built in Thermal Shutdown DESCRIPTION The US1260 product using a proprietary process combines a dual low drop out adjustable output regulators in a single package with one output having a minimum of 6A and the other one having a 1A output current capability. This product is specifically designed to provide well regulated supplies for low voltage ICs such as 3.3V to 1.5V and 2.5V supplies for the GTL+ termination and the new clock for Pentium II applications.Other applications include low cost dual supply for processors such as Intel P55CTM where 2.8V and 3.3 V are needed for the Core and the I/O supplies from the 5V input. APPLICATIONS Providing a single package solution for GTL+ and High Speed Bus Termination Dual supply P55CTM applications TYPICAL APPLICATION 3.3V C1 R1 C2 Vout1 2.5V / 1A U1 Vin Vout2 US1260 Gnd Vfb2 Vfb1 Vctrl 7 6 5 4 3 2 1 R2 C4 R3 C3 R4 1.5V / 6A R5 C5 1260app7-1.0 5V Typical application of US1260 in the Pentium TM design with the 1.5V output providing for GTL+ termination while 2.5V supplies the clock chip. Notes: Pentium is trade mark of Intel Corp. Notes: P55C is trade mark of Intel Corp. PACKAGE ORDER INFORMATION Tj (C) 0 TO 150 7 PIN PLASTIC TO220(T) US1260CT 7 PIN PLASTIC TO263(M) US1260CM 7 PIN PLASTIC POWER FLEX(P) US1260CP Rev. 1.9 3/22/99 3-1 US1260 ABSOLUTE MAXIMUM RATINGS Input Voltage (Vin) ............................................................. 7V Power Dissipation ............................................ Internally Limited Storage Temperature Range ................................ -65C TO 150C Operating Junction Temperature Range ...................... 0C TO 150C PACKAGE INFORMATION 7 PIN PLASTIC TO220 FRONT VIEW 7 6 5 4 3 2 1 7 PIN PLASTIC TO263 FRONT VIEW 7 6 5 4 3 2 1 7 PIN POWER FLEX (P) FRONT VIEW 7 6 5 4 3 2 1 Vout1 Vin Vout2 Gnd Vfb2 Vfb1 Vctrl M7 Vout1 Vin Vout2 Gnd Vfb2 Vfb1 Vctrl Vout1 Vin Vout2 Gnd Vfb2 Vfb1 Vctrl JT =2.7C/W JA =60C/W JA =30C/W for 1"sq pad JA =30C/W for 1"sq pad ELECTRICAL SPECIFICATIONS Unless otherwise specified ,these specifications apply over ,Cin=1 uF,Cout=10uF,and Tj=0 to 150C.Typical values refer to Tj=25C. Ifl=6A for output #1,and Ifl=1A for output #2. Vfb=Vo for both outputs.Vctrl=Vin=3.3V. PARAMETER Vctrl Input Voltage Reference Voltage Line Regulation Load Regulation (note 1) Dropout Voltage (output #2) (Note 2) Dropout Voltage (output #1) (Note 2) Current Limit (output #2) Current Limit (output #1) Thermal Regulation Ripple Rejection SYM Vref MIN TYP 3.0 Io=10mA,Tj=25C 1.188 1.200 Io=10mA 1.176 1.200 Io=10mA,Vout+1.3V ICL2 ICL1 0.02 Feedback Pin Input Current Ifb Temperature Stability Long Term Stability RMS Output Noise Minimum Load Current(Note 3) 1 Note 1 : Low duty cycle pulse testing with Kelvin connections are required in order to maintain accurate data. Note 2 : Drop-out voltage is defined as the minimum differential voltage between Vin and Vout required to maintain regulation at Vout. It is measured when the output voltage drops 1% below its nominal value. Note 3 : Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor dividers are selected such that it automatically maintains this current. 3-2 Rev. 1.9 3/22/99 US1260 PIN DESCRIPTIONS PIN # 3 2 5 7 6 PIN SYMBOL Vfb2 Vfb1 Vout2 Vout1 Vin PIN DESCRIPTION A resistor divider from this pin to the Vout #2 pin and ground sets the output voltage. See application ckt for the divider setting for 1.5V output. A resistor divider from this pin to Vout #1 pin and ground sets the output voltage.See application ckt for the divider setting for 2.5V output. The output #2 (high current) of the regulator. A minimum of 100uF capacitor must be connected from this pin to ground to insure stability. The output #1 (low current) of the regulator. A minimum of 100uF capacitor must be connected from this pin to ground to insure stability. The power input pin of the regulator. Typically a large storage capacitor is connected from this pin to ground to insure that the input voltage does not sag below the minimum drop out voltage during the load transient response. This pin must always be higher than both Vout pins by the amount of the dropout voltage(see datasheet) in order for the device to regulate properly. This pin is connected to GND. It is also the TAB of the package. The control input pin of the regulator. This pin via a 10 resistor is connected to the 5V supply to provide the base current for the pass transistor of both regulators. This allows the regulator to have very low dropout voltage which allows one to generate a well regulated 2.5V supply from the 3.3V input. A high frequency, 1 uF capacitor is connected between this pin and Vin pin to insure stability. 4 1 Gnd Vctrl BLOCK DIAGRAM Vin 6 Vctrl 1 2 Vfb1 7 Vout1 THERMAL SHUTDOWN 1.20V + 4 Gnd 3 Vfb2 1260blk1-1.1 5 Vout2 Figure 1 - Simplified block diagram of the US1260 Rev. 1.9 3/22/99 3-3 US1260 APPLICATION INFORMATION Introduction The US1260 is a dual adjustable Low Dropout (LDO) regulator packaged in a 7 pin TO220 which can easily be programmed with the addition of two external resistors to any voltages within the range of 1.20 to 5.5 V. This voltage regulator is designed specifically for applications that require two separate regulators such as the Intel PII processors requiring 1.5V and 2.5 V supplies, eliminating the need for a second regulator which results in lower overall system cost. When Vctrl pin is connected to a supply which is at least 1V higher than Vin, the dropout voltage improves by 30% which makes it ideal for applications requiring less than the standard 1.3V dropout given in the LDO products such as US10XX series. The US1260 also provides an accurate 1.20V voltage reference common to both regulators for programming each output voltage. Other features of the device include; fast response to sudden load current changes, such as GTL+ termination application for Pentium II TM family of microprocessors. The US1260 also includes thermal shutdown protection to protect the device if an overload condition occurs. The US1260 keeps a constant 1.20V between the Vfb pin and ground pin. By placing a resistor R1 across these two pins a constant current flows through R1, adding to the IFB current and into the R2 resistor producing a voltage equal to the (1.2/R1)*R2 + IFB* R2 which will be added to the 1.20V to set the output voltage as shown in the above equation. Since the input bias current of the amplifier (IFB) is only 0.02uA typically , it adds a very small error to the output voltage and for most applications can be ignored. For example, in a typical 1.5V GTL+application if R1=10.2k and R2=2.55k the error due to the Iadj is only 0.05mV which is less than 0.004% of the nominal set point. The effective input impedance seen by the feedback pins (R1 II R2) must always be higher than 1.8k in order for the regula tor to start up properly. Load Regulation Since the US1260 does not provide a separate ground pin for the reference voltage, it is not possible to provide true remote sensing of the output voltage at the load. Figure 3 shows that the best load regulation is achieved when the bottom side of R1 resistor is connected directly to the ground pin of US1260 (preferably to the tab of the device) and the top side of R2 resistor is connected to the load. In fact , if R1 is connected to the load side, the effective resistance between the regulator and the load is gained up by the factor of (1+R2/R1) ,or the effective resistance will be ,Rp(eff)=Rp*(1+R2/R1).It is important to note that for high current applications, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to minimize this effect. Output Voltage Setting The US1260 can be programmed to any voltages in the range of 1.20V to 5.5V with the addition of R1 and R2 external resistors according to the following formula: R2 VOUT = VREF 1 + + R2 x IB R1 Wehre : VREF = 120V Typically . IB = 0.02uA Typical R1 & R2 as shown in figure 2 Vin Vin Vout US1260 Vin Vin Vout Vout R2 Ib Vctrl Vctrl Gnd Vfb R2 RL R1 US1260 Vctrl Vctrl Gnd Vref Vfb R1 1260app2-1.0 Rp PARASITIC LINE RESISTANCE 1260app3-1.1 Figure 2 - Typical application of the US1260 for programming the output voltage. (Only one output is shown here) Figure 3 - Schematic showing connection for best load regulation. (Only one output is shown here) 3-4 Rev. 1.9 3/22/99 US1260 Stability The US1260 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for the microprocessor applications use standard electrolytic capacitors with typical ESR in the range of 50 to 100 m and the output capacitance of 500 to 1000uF. Fortunately as the capacitance increases, the ESR decreases resulting in a fixed RC time constant. The US1260 takes advantage of this phenomena in making the overall regulator loop stable. For most applications a minimum of 100uF aluminum electrolytic capacitor with the maximum ESR of 0.3 such as Sanyo, MVGX series ,Panasonic FA series as well as the Nichicon PL series insures both stability and good transient response. The US1260 also requires a 1 uF ceramic capacitor connected from Vin to Vctrl and a 10, 0.1W resistor in series with Vctrl pin in order to further insure stability. Thermal Design The US1260 incorporates an internal thermal shutdown that protects the device when the junction temperature exceeds the maximum allowable junction temperature. Although this device can operate with junction temperatures in the range of 150C ,it is recommended that the selected heat sink be chosen such that during maximum continuous load operation the junction temperature is kept below this number. Two examples are given which shows the steps in selecting the proper regulator heat sink for driving the Pentium II processor GTL+ termination resistors and the Clock IC using 1260 in TO220 or TO-263 packages. Example # 1 Assuming the following specifications : VIN = 3.3V VOUT 2 = 1.5 V VOUT 1 = 2.5 V IOUT 2 MAX = 5.4A IOUT 1 MAX = 0.4 A TA = 35 C The steps for selecting a proper heat sink to keep the junction temperature below 135C is given as : 1) Calculate the maximum power dissipation using : PD = IOUT1 x ( VIN - VOUT1) + IOUT2 x ( VIN - VOUT2) PD = 0.4 x ( 3.3 - 2.5 ) + 5.4 x ( 3.3 - 1.5) = 10 W 2) Select a package from the datasheet and record its junction to case (or Tab) thermal resistance. Selecting TO220 package gives us : JC =2.7 C / W 3) Assuming that the heat sink is Black Anodized, calculate the maximum Heat sink temperature allowed : Assume , SA = 0.05 C/W (Heat sink to Case thermal resistance for Black Anodized) TS = TJ - PD x (JC + CS) TS = 135 - 10 x ( 2.7 + 0.05) = 107.4 C 4) With the maximum heat sink temperature calculated in the previous step, the Heat Sink to Air thermal resistance SA is calculated as follows : T = TS - TA = 107.4 - 35 = 72.4 C T PD 72.4 = 7.24 C / W SA = 10 SA = 5) Next , a heat sink with lower SA than the one calculated in step 4 must be selected. One way to do this is to simply look at the graphs of the "Heat Sink Temp Rise Above the Ambient" vs. the "Power Dissipation" and select a heat sink that results in lower temperature rise than the one calculated in previous step. The following heat sinks from AAVID and Thermaloy meet this criteria. Air Flow (LFM) 0 100 200 300 400 7021B 7020B 6021PB 7173D 7141D 593101B 551002B 534202B 577102B 576802B Thermalloy AAVID Note : For further information regarding the above companies and their latest product offering and application support contact your local representative or the numbers listed below: Thermalloy AAVID PH# (214) 243-4321 PH# (603) 528-3400 Rev. 1.9 3/22/99 3-5 US1260 Example # 2 : Assuming the following specifications : VIN = 3.3V VOUT 2 = 1.5 V VOUT 1 = 2.5 V IOUT 2 MAX = 1.5A IOUT 1 MAX = 0.2 A TA = 35 C The steps for selecting a proper heat sink to keep the junction temperature below 135C is given as : 1) Calculate the maximum power dissipation using : PD = IOUT1 x ( VIN - VOUT1) + IOUT2 x ( VIN - VOUT2) PD = 0.2 x ( 3.3 - 2.5) + 1.5 x (3.3 - 1.5) = 2.86 W In this application, the US1260 is used on the VGA card to convert 3.3V supply to 2.7V to power the Intel 740 chip rather than the conventional LDO which due to its 1.5V minimum dropout spec must use the 5V supply to achieve the same result. The difference is a substantial decrease in the power dissipation as shown below. The maximum power dissipation of 740 chip is 5.8W, which at 2.7V results in Io=5.8/2.7=2.15A a) Using standard LDO, the power dissipated in the device is; Pd=(Vin - Vo)*Io=(5-2.7)*2.15=4.94W Using surface mount TO263 package with 25 C/W junction to air thermal resistance results in: Tj=Pd*ja + Ta=(4.94)(25) + 25=148 C This is very close to the thermal shutdown of the IC. b) Using 1260, the power dissipated in the device is drastically reduced by using 3.3V supply instead of 5V Pd=(Vin - Vo)*Io=(3.3-2.7)*2.15=1.3W Using surface mount TO263 package with 25 C/W junction to air thermal resistance results in: Tj=Pd*ja + Ta=(1.3)(25) + 25=57 C A reduction of 91 C in junction temperature. 2) Assuming a TO-263 surface mount package, the junction to ambient thermal resistance of the package is: JA = 30 C / W for 1" square pad area 3) The maximum junction temperature of the device is calculated using the equation below : TJ = TA + PD x JA TJ = 35 + 2.86 x 30 = 121 C Since this is lower than our selected 135C maximum junction temperature (150C is the thermal shutdown of the device), TO-263 package is a suitable package for our application. Layout Consideration The US1260 like all other high speed linear regulators need to be properly laid out to insure stable operation. The most important component is the output capacitor, which needs to be placed close to the output pin and connected to this pin using a plane connection with a low inductance path. US1260 in Ultra LDO, Single Output Application The US1260 can also be used in single supply applications where the difference between input and output is much lower than the standard 1.5V dropout that is obtainable with standard LDO devices. The schematic in figure 6 shows the application of the US1260 in a single supply with the second LDO being disabled. 3-6 Rev. 1.9 3/22/99 US1260 TYPICAL APPLICATION PENTIUM TM APPLICATION 3.3V C1 R1 C2 Vout1 2.5V / 1A U1 Vin Vout2 US1260 Gnd Vfb2 Vfb1 Vctrl 7 6 5 4 3 2 1 R2 C4 R3 C3 R4 1.5V / 6A R5 C5 1260app7-1.0 5V Figure 4 - Typical application of US1260 in the Pentium TM design with the 1.5V output providing for GTL+ termination while 2.5V supplies the clock chip. Notes: Pentium is trade mark of Intel Corp. Ref Desig U1 C1,C3 C2 C4 C5 R1 R2,R4 R3 R5 HS1 Description Qty Part # Manuf Dual LDO Regulator 1 US1260CM Unisem Capacitor 2 Elect,680uF,EEUFA1A681L Panasonic Capacitor 1 Elect,220uF,6.3V,ECAOJFQ221 Panasonic Capacitor 1 Ceramic, 0.1 uF, SMT , 0805 Panasonic Capacitor 1 Elect,100uF,6.3V,ECAOJFQ101 Panasonic Resistor 1 11 k , 1%, SMT , 0805 Panasonic Resistor 2 10.2 k , 1%, SMT , 0805 Panasonic Resistor 1 2.55 k , 1%, SMT , 0805 Panasonic Resistor 1 3 , 5%, SMT , 0805 Panasonic Heat Sink Use 1" Square Copper Pad area if Iout2<1.7A & Iout1<0.2A For Iout2<3A & Iout1<0.5A Use US1260CT and Thermalloy 6030B Rev. 1.9 3/22/99 3-7 US1260 TYPICAL APPLICATION RAMBUS APPLICATION 5V 2.5V C2 Vout1 C1 R1 U1 Vin Vout2 US1260 Gnd Vfb2 Vfb1 Vctrl 7 6 5 4 3 2 1 R2 R3 C3 R4 3.3V 1260app6-1.0 Figure 5- Typical application of US1260 in the RambusTM design with the 2.5V output providing for memory termination while 3.3V supplies the on board logic. Notes:Rambus is trade mark of Rambus Corp. Ref Desig U1 C1,C2,C3 R1 R2,R4 R3 HS1 Description Qty Part # Manuf Dual LDO Regulator 1 US1260CM Unisem Capacitor 3 Elect,220uF,6.3V,ECAOJFQ221 Panasonic Resistor 1 11 k , 1%, SMT , 0805 Panasonic Resistor 2 10.2 k , 1%, SMT , 0805 Panasonic Resistor 1 17.8 k , 1%, SMT , 0805 Panasonic Heat Sink 1" Square Copper Pad area if Iout2<1.2A & Iout1<0.5A For Iout2<3A & Iout1<0.5A Use Thermalloy 6030B 3-8 Rev. 1.9 3/22/99 US1260 TYPICAL APPLICATION INTEL I740 GRAPHICS CHIP APPLICATION 3.3V C1 Vout1 U1 Vin Vout2 US1260 Gnd Vfb2 Vfb1 Vctrl 7 6 5 4 3 2 1 2.7V C4 R3 C3 R5 C5 R4 1260app8-1.0 5V Figure 6 - Typical application of US1260 to provide 2.7V from the 3.3V bus for the Intel 740 graphics chip. Ref Desig U1 C1,C3 C4 C5 R4 R3 R5 Description Qty Dual LDO Regulator 1 Capacitor 2 Capacitor 1 Capacitor 1 Resistor 1 Resistor 1 Resistor 1 Part # US1260CM Elect,680uF,EEUFA1A681L Ceramic, 0.1 uF, SMT , 0805 Elect,100uF,6.3V,ECAOJFQ101 10.2 k , 1%, SMT , 0805 12.7 k , 1%, SMT , 0805 3 , 5%, SMT , 0805 Manuf Unisem Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Rev. 1.9 3/22/99 3-9 |
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