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V4374128C24V 1GB 168-PIN REGISTERED PLL ECC SDRAM DIMM 3.3 VOLT 128M x 72
Description
PRELIMINARY
s 168 Pin Registered ECC 134,217,728 x 72 bit Oganization SDRAM Modules s Utilizes High Performance 64M x 4 SDRAM in SOC Packages s Fully PC Board Layout Compatible to INTEL'S Rev 1.2 Module Specification s Single +3.3V ( 0.3V) Power Supply s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 8192 Refresh Cycles every 64 ms s Serial Presence Detect (SPD) s
Part Number Speed Grade Configuration
128M x 72
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Features
V4374128C24VXXG-75
V4374128C24V Rev. 1.1 January 2002
The V4374128C24V memory module is organized 134,217,728 x 72 bits in a 168 pin dual in line memory module (DIMM). The 128M x 72 registered DIMM uses 36 Mosel-Vitelic 64M x 4 ECC SDRAM. The x72 registered modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
V4374128C24VXXG-75PC -75PC, CL=2,3 (133 MHz) -75, CL=3 (133 MHz)
128M x 72
V4374128C24VXXG-10PC -10PC, CL=2,3 (100 MHz)
128M x 72
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V4374128C24V
Front DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2 CB3 VSS I/O17 I/O18 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front I/O19 I/O20 VCC I/O21 NC DU CKE1* VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2* NC WP SDA SCL VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4 CB5 VSS NC NC VCC CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1* A12 VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6 CB7 VSS I/O49 I/O50 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back I/O51 I/O52 VCC I/O53 NC DU REGE VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3* NC SA0 SA1 SA2 VCC
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Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO CB1 VSS NC NC VCC WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Pin Configurations (Front Side/Back Side)
Notes:
* These pins are not used in this module.
Pin Names
A0-A12 I/O1-I/O64 RAS CAS WE BA0, BA1 CKE0 CS0, CS2 CLK0-CLK3 DQM0-DQM7 VCC VSS SCL Address Inputs Data Inputs/Outputs Row Address Strobe Column Address Strobe Read/Write Input Bank Selects Clock Enable Chip Select Clock Input Data Mask Power (+3.3 Volts) Ground Clock for Presence Detect CB0-CB4 NC REGE DU SA0-A2 SDA Serial Data OUT for Presence Detect Serial Data IN for Presence Detect Check Bits (x72 Organization) No Connection Register Enable Don't Use
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V
MOSEL VITELIC MANUFACTURED
Module Part Number Information
4
3
74 128
C
2
4
V
X
X
G - XX
SPEED 75PC = PC133 CL3,2 75 = PC133 CL3 10PC = PC133 CL3,2 LEAD FINISH G = GOLD
SDRAM 3.3V WIDTH DEPTH 168 PIN Registered DIMM X4 COMPONENT REFRESH RATE 8K
COMPONENT PACKAGE S=SOC COMPONENT A=0.17um REV LEVEL B=0.14um LVTTL 4 BANKS
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Block Diagram
RS0 RS1 RDQMB0 DQ0 DQ1 DQ2 DQ3 DQM CS DQ0 DQ1 U11 DQ2 DQ3 DQM CS DQ0 DQ1 U12 DQ2 DQ3 DQM CS DQ0 DQ1 U29 DQ2 DQ3 DQM CS DQ0 DQ1 U30 DQ2 DQ3 RDQMB4 DQ32 DQ33 DQ34 DQ35 DQM CS DQ0 DQ1 U1 DQ2 DQ3 DQM CS DQ0 DQ1 U2 DQ2 DQ3 DQM CS DQ0 DQ1 U19 DQ2 DQ3 DQM CS DQ0 DQ1 U20 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB1 DQ8 DQ9 DQ10 DQ11 DQM CS DQ0 DQ1 U13 DQ2 DQ3 DQM CS DQ0 DQ1 U14 DQ2 DQ3 DQM CS DQ0 DQ1 U5 DQ2 DQ3 DQM CS DQ0 DQ1 U31 DQ2 DQ3 DQM CS DQ0 DQ1 U32 DQ2 DQ3 DQM CS DQ0 DQ1 U23 DQ2 DQ3 DQ36 DQ37 DQ38 DQ39 RDQMB5 DQ40 DQ41 DQ42 DQ43 DQM CS DQ0 DQ1 U3 DQ2 DQ3 DQM CS DQ0 DQ1 U4 DQ2 DQ3 DQM DQ0 DQ1 U6 DQ2 DQ3 CS DQM CS DQ0 DQ1 U21 DQ2 DQ3 DQM CS DQ0 DQ1 U22 DQ2 DQ3 DQM DQ0 DQ1 U24 DQ2 DQ3 CS DQ12 DQ13 DQ14 DQ15 DQ44 DQ45 DQ46 DQ47 CB0 CB1 CB2 CB3 RS2 RS3 RDQMB2 DQ16 DQ17 DQ18 DQ19 DQM CS DQ0 DQ1 U15 DQ2 DQ3 DQM CS DQ0 DQ1 U16 DQ2 DQ3 DQM CS DQ0 DQ1 U33 DQ2 DQ3 DQM CS DQ0 DQ1 U34 DQ2 DQ3 CB4 CB5 CB6 CB7 RDQMB6 DQ48 DQ49 DQ50 DQ51 DQM CS DQ0 DQ1 U7 DQ2 DQ3 DQM CS DQ0 DQ1 U8 DQ2 DQ3 DQM CS DQ0 DQ1 U25 DQ2 DQ3 DQM CS DQ0 DQ1 U26 DQ2 DQ3 DQ20 DQ21 DQ22 DQ23 RDQMB3 DQ24 DQ25 DQ26 DQ27 DQM CS DQ0 DQ1 U17 DQ2 DQ3 DQM CS DQ0 DQ1 U18 DQ2 DQ3 DQM CS DQ0 DQ1 U35 DQ2 DQ3 DQM CS DQ0 DQ1 U36 DQ2 DQ3 DQ52 DQ53 DQ54 DQ55 RDQMB7 DQ56 DQ57 DQ58 DQ59 DQM CS DQ0 DQ1 U9 DQ2 DQ3 DQM CS DQ0 DQ1 U10 DQ2 DQ3 DQM CS DQ0 DQ1 U27 DQ2 DQ3 DQM CS DQ0 DQ1 U28 DQ2 DQ3 DQ28 DQ29 DQ30 DQ31 DQ60 DQ61 DQ62 DQ63 U37, U38, U40 RAS CAS CKEO WE A0-A11 A0-A12 BA0 BA1 S0-S3 DQMB0 - DQMB7 10K Vcc REGE PLL CLK R E G I S T E R S U41 SCL WP 47K RRAS: SDRAMs U1-U36 RCAS: SDRAMs U1-U36 RCKE0: SDRAMs U1-U36 RWE: SDRAMs U1-U36 RA0-RA11: SDRAMs U1-U36 RA0-RA12: SDRAMs U1-U36 RBA0: SDRAMs U1-U36 RBA1: SDRAMs U1-U36 RS0-RS3 RDQMB0 - RDQMB7 SPD U42 A0 A1 A2 SA0 SA1 SA2 U39 CK0 PLL 12pF CK1-CK3 12pF Vcc Vss NOTE: 1. All resistor values are 10 ohms unless otherwise specified
V4374128C24V Rev. 1.1 January 2002
SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 SDRAM x 4 REGISTER x 3
SDRAMs U0-U35 SDRAMs U0-U35
U1-U36 = MT48BLC32M4A2F SDRAMs (512MB) U1-U36 = MT48BLC64M4A2F SDRAMs (1GB)
4
V4374128C24V
written into the E2PROM device during module production using a serial presence detect protocol (I 2C synchronous 2-wire bus)
E2PROM
A serial presence detect storage device - - is assembled onto the module. Information about the module configuration, speed, etc. is
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SPD-Table:
0 1 2 3 4 Memory Type 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS Latencies WE Latencies 24 25 26 27
Serial Presence Detect Information
Byte Number Function Described
Number of SPD bytes Total bytes in Serial PD
Hex Value SPD Entry Value
128 256 SDRAM 13 11
-75PC
80 08 04 0D 0B
-75
80 08 04 0D 0B
-10PC
80 08 04 0D 0B
Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies
2 72 0 LVTTL 7.5 ns/10.0 ns 5.4 ns/6.0 ns ECC Self-Refresh, 7.8s x4 n/a / x4 tccd = 1 CLK 1, 2, 4, 8 4 CL =2, 3 CS Latency = 0 WL = 0 Registered/Buffered Vcc tol 10% 7.5 ns/10.0 ns
02 48 00 01 75 54 02 82 04 04 01
02 48 00 01 75 54 02 82 04 04 01
02 48 00 01 A0 60 02 82 04 04 01
0F 04 06 01 01 1F 0E 75
0F 04 06 01 01 1F 0E A0
0F 04 06 01 01 1F 0E A0
SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency =2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time
5.4 ns/6.0 ns
54
60
60
Not Supported Not Supported
00 00
00 00
00 00
15 ns/20 ns
0F
14
14
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28 29 30 31 32 33 34 35 36-61 62 63 64 65-71 72 73-90 91-92 93 94 95-98 99-125 126 127 128+ SPD Revision Reserved Reserved
SPD-Table: (Continued)
Byte Number Function Described
Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) Revision 2/1.2
Hex Value SPD Entry Value
14 ns/15 ns/16 ns
-75PC
0F
-75
0F
-10PC
0F
15 ns/20 ns 42 ns/45 ns 512 MByte 1.5 ns/2.0 ns 0.8 ns/1.0 ns 1.5 ns/2.0 ns 0.8 ns/1.0 ns
0F 2A 80 15 08 15 08 00
14 2D 80 15 08 15 08 00
14 2D 80 20 10 20 10 00
02 69
02 AD 40 00
12 1A 40 00
Checksum for Bytes 0 - 62 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code (cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Assembly Manufacturing Date (Year) Assembly Manufacturing Date (Week) Assembly Serial Number V4374128C24V Mosel Vitelic
40 00
00 64 8D 00
00 64 8D 00
00 64 8D 00
Intel Specification for Frequency
Unused Storage Location
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DC Characteristics
TA = 0C to 70C; VSS = 0 V; VDD, VDDQ = 3.3V 0.3V
Limit Values Symbol
VIH V IL V OH V OL II(L) IO(L)
Parameter
Input High Voltage Input Low Voltage Output High Voltage (IOUT = -4.0 mA) Output Low Voltage (IOUT = 4.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < V CC)
Min.
2.0 -0.3 2.4 -- -10
Max.
VCC +0.3 0.8 -- 0.4 10
Unit
V V V V A A
-10
10
Capacitance
Symbol
CI1 CI2 CICL CI3 CI4 CIO CSC CSD
TA = 0C to 70C; VDD = 3.3V 0.3V, f = 1 MHz
Parameter
Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0-CS3) Input Capacitance (CLK0) Input Capacitance (CKE0) Input Capacitance (DQM0-DQM7) Input/Output Capacitance (I/O1-I/064) Input Capacitance (SCL, SA0-2) Input/Output Capacitance
Limit Values
15 15 20 15 15 16 8 18
Unit
pF pF pF pF pF pF pF pF
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Absolute Maximum Ratings
Parameter
Voltage on VDD Supply Relative to VSS Voltage on Input Relative to V SS Operating Temperature Storage Temperature Power Dissipation
Max.
-1 to 4.6 -1 to 4.6 0 to +70 -55 to 125 29
Units
V V C C W
Standby and Refresh Currents1
TA = 0C to 70C, VCC = 3.3V 0.3V
Symbol
ICC 1
Parameter
Operating Current
Test Conditions
Burst length = 4, CL = 3 tRC > = tRC(min), tCK> = tCK(min), IO = 0 mA 2 Bank Interleave Operation CKE< = VIL(max), tCK> = tCK(min) CKE> = V IH(min), tCK> = tCK(min), Input changed once in 3 cycles CKE< = VIL(max), tCK> = tCK(min)
-75PC/75
4200
-10PC
3780
Unit
mA
Note
1,2
ICC 2P ICC 2N ICC 3P ICC 3N
Precharged Standby Current in Power Down Mode Precharged Standby Current in Non-Power Down Mode Active Standby Current in Power Down Mode
72
72
mA
720
630
mA
CS = High
360
360
mA
Active Standby Current in Non-Pow- CKE> = V IH(min), tCK> = tCK(min), Iner Down Mode put changed one time
900
810
mA
CS = High
ICC 4
Burst Operating Current
tRC = Infinite, CL = 3, tCK> = tCK(min), IO = 0 mA 2 Banks Activated tRC >= tRC (min) CKE = <0,2 V Standard L-version
2700
1920
mA
1, 2
ICC 5 ICC 6
Auto Refresh Current Self Refresh Current
8640 108 62
7920 108 62
mA mA
1,2 1,2
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# Symbol Parameter Clock and Clock Enable
1 tCK 2 fCK 3 tAC 4 5 6 7 8 9 10 tCH tCL tCS tCH tCKSP tCKSR tT
AC Characteristics 3,4
TA = 0 to 70C; VSS = 0V; VCC = 3.3V 0.3V, tT = 1 ns
Limit Values -75PC Min. Max. Min. -75 Max. -10PC Min. Max. Unit Note
Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Input Setup time Input Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall)
7.5 7.5 - - - - 2.5 2.5 1.5 0.8 2.5 8 1 133 133 5.4 6 - - - - - - -
7.5 10 - - - - 2.5 2.5 1.5 0.8 2.5 8 1 133 100 5.4 6 - - - - - - -
10 10 - - - - 3 3 2 1 2 8 1 100 100 6 6 - - - - - - -
ns ns MHz MHz 4,5 ns ns ns ns ns ns ns ns ns 6 6 7 7 8 9
Common Parameters
11 12 13 14 15 16 tRCD tRC tRAS tRP tRRD tCCD RAS to CAS delay Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS delay time (same bank) 15 70 42 15 14 1 - 120K - - - - 20 70 45 20 15 1 - 120K - - - - 20 60 45 20 20 1 - 120K - - - - ns ns ns ns ns CLK 6 6 6 6 6
Refresh Cycle
17 18 tSREX tREF Self Refresh Exit Time Refresh Period (8192 cycles) 10 64 - - 10 64 - - 10 64 - - ns ms
Read Cycle
19 20 21 22 tOH tLZ tHZ tDQZ Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 3 1 3 - - - 7.5 2 3 1 3 - - - 7.5 2 3 1 3 - - - 8 2 ns ns ns CLK 7 2
Write Cycle
23 24 tDPL tDQW Data input to Precharge (write recovery) DQM Write Mask Latency 2 0 - - 2 0 - - 1 0 - - CLK CLK
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10. 11.
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Notes:
2. The specified values are valid when data inputs (DQ's) are stable during t RC(min.).
tCH 2.4V CLOCK 0.4V
1. The specified values are valid when addresses are changed no more than once during t CK(min.) and when No Operation commands are registered on every rising clock edge during t RC(min). Values are shown per module bank.
3. All AC characteristics are shown for device level. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V.
+ 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF
INPUT 1.4V
tCL
tSETUP tHOLD
tT
tAC tLZ tOH
tAC
I/O 50 pF
1.4V
OUTPUT
Measurement conditions for tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. tDAL is equivalent to t DPL + tRP.
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Package Diagram
SDRAM DIMM Module Package
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) .118 (3.00) R (2X) .118 (3.00) TYP. .250 (6.35) TYP. .118 (3.00) TYP. PIN 1 4.550 (115.57) .039 (1.00) R(2X) .040 (1.02) TYP. .050 (1.27) TYP. PIN 84
.157 (3.99) MAX
1.705 (43.31) 1.695 (43.05)
.700 (17.78) TYP.
.054 (1.37) .046 (1.17)
BACK VIEW
.128 (3.25) .118 (3.00) 1.661 (42.18) PIN 168 2.625 (66.68) PIN 85 NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN
(2X)
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Label Information
Module Density
MOSEL VITELIC
Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code
V4374128C24VXXX-XX PC133R-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan
1GB CLX
CAS Latency 2=CL2 3=CL3
PC133 R -XXX
REGISTERED DIMM CL= 3 or 2 (CLK) tRCD= 3 or 2 (CLK) tRP= 3 or 2 (CLK)
54 2
A
Gerber file Intel PC100 x4 Based JEDEC SPD Revision 2
tAC = 5.4 ns
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V4374128C24V
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WEST
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
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WORLDWIDE OFFICES
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(c) Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
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