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VISION VV 5402 Monolithic Sensor
Multi-standard Monochrome CMOS Image Sensor.
PRODUCT DATASHEET DISTINCTIVE CHARACTERISTICS
* * * * *
Complete Video Camera on a single chip EIA/CCIR standard compatible Low power operation (250mW Typical) Integral 75 driver Control options pin selectable for ease of use
* * * * *
Low light operation to 0.5 lux Automatic Exposure and Gain Control Automatic Black Level Calibration Linear or Gamma corrected output option Industry standard 48 pin LCC package
GENERAL DESCRIPTION
The VV5402 is a highly-integrated VLSI camera device based on VISION's unique CMOS sensor technology. It is suitable for applications requiring a composite video output with minimum external circuitry. The device incorporates a 388 x 295 pixel image sensor and all the necessary support circuits to generate fully formatted composite video into a 75 load.
Automatic control of exposure, gain and black
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BLOCK DIAGRAM
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DIGITAL CONTROL LOGIC. AGC AEC RESETB LIN BKLIT CCIR
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ANALOG VOLTAGE REFS. VIDEO BUFFER AVO VIDEO AMP
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VRT Vbloom VOFF VBG EBCK EVWT 2V7
level allow use of a single fixed-aperture lens over a wide range of operating conditions. Normal and Backlit modes further enhance difficult scene types. All major control functions are pin selectable giving maximum flexibility with ease of use. The VV5402 offers a complete camera system with only a few external components.
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Pixel Format Pixel Size Array Size Min. illumination S/N Exposure control Gain Control Power Supply Power Temperature
VERTICAL SHIFT REGISTER
PHOTO DIODE ARRAY
5V CKOUT CKIN SIN
COLUMN SENSE AMPLIFIERS
CLOCK CIRCUIT SAMPLE & HOLD
HORIZONTAL SHIFT REGISTER
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384 x 287 (CCIR) 320 x 243 (EIA) 12m x 12m 4.66mm x 3.54mm 0.5 lux (Standard Clock) Typically 52dB Automatic (to 146000:1) Automatic (to +20dB) 5v 5% < 300 mW 0oC - 40oC
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VISION V V 5402 Sensor
MAIN FEATURES
Contents
Main Features Specifications Pin List Video Standards Example Support Circuit page 3 5 9 12 15
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Main Features
Video Output
The VV5402 delivers a fully-formatted composite monochrome video signal. Standards options include EIA (320 x 244) and CCIR (384 x 287). On chip signal conditioning allows user-selection of linear or gammacorrected output. The integrated 75 driver eliminates the need for additional active components to drive standard loads, including double terminated lines.
Automatic Gain Control (AGC)
The VV5402 automatically increases the system gain of its output stage if with the current gain setting and maximum exposure the image is too dark. Gain can be varied from x1 to x16 in times-two steps, giving five different gain settings. If the scene is too dark and the integration period has almost reached its maximum value, the gain value is incremented by one step (times two). In the same frame period the exposure value is divided by two, halving the integration period. The exposure controller then increases the exposure value as necessary. Similarly if the image is too bright and the integration period is short then gain will be reduced by one step (divide by two) and the exposure value will be doubled. The exposure controller can then adjust the exposure value as necessary to provide a correctly exposed image.
Automatic Exposure and Gain Control
Automatic exposure and gain control are enabled with AEC=1 (pin 21) and AGC=1 (pin22). However, If AEC is inhibited by pin 21, AGC is also inhibited. Inhibiting AEC or AGC by taking pin 21 or 22 low freezes the current value(s) for these.
Automatic exposure control is achieved by varying pixel current integration time according to the average light level on the sensor. This integration time can vary from one pixel clock period to one frame period.
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The VV5402 controls exposure over a range of 99,000:1 in EIA mode and 146,000:1 in CCIR mode, and operates at illumination levels as low as 0.5 lux at standard clock frequencies. (The system clock frequency can be reduced to provide increased sensitivity.)
Pixels above a threshold white level are counted every frame, and the number at the end of the frame defines the image exposure. If the image is other than correctly exposed, a new value for integration time is calculated and applied for the next frame. Corrections are either 1/8 or 1/64, depending upon the degree of over or under exposure.
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Automatic Exposure Control (AEC)
Backlit Mode
The VV5402 can be configured to operate in two auto-exposure modes, selected by the BKLIT pin (pin28) state. The default mode (BKLIT = 0) provides exposure control for normally illuminated scenes. For scenes where a bright background can cause the foreground subject to be severely under exposed, the `Backlit' mode (BKLIT = 1) offers superior performance. `Backlit Mode' (BKLIT=1) operates by using a higher threshold level for the exposure control comparator over the central area of an image, which is therefore exposed for longer and so enhanced. The area in which the higher comparator threshold is used when BKLIT=1 is illustrated below:
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VISION V V 5402 Sensor
Backlit Mode Threshold Area:
Normal operation (BKLIT=0) 10%
Higher threshold area (BKLIT=1)
30%
80%
25%
80% 90% 25% 75% Higher Threshold
Spectral Response
Normalised Response
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1.0 0.8 0.6 0.4 0.2 1000 400 500 600 700 800 900 1100 0 Wavelength nm
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Note: The threshold level used for the central area is a preset mutiple of the normal mode reference level, and is not alterable.
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Visible image
Exposure control area
Specifications
SPECIFICATIONS Package Details
1.52 TYP 13.7 0.55 0.53 14.22
Glass Lid Die Base
0.51 TYP
0.5
0.86
Viewed from side
2.16 PIN 1 1.016 PITCH TYP Viewed from below
Tolerances on package dimensions 10% Glass lid placement is controlled so that no package overhang exists. All dimensions in millimetres
Absolute Maximum Ratings
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Parameter
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Supply Voltage Voltage on other input pins Temperature under bias Storage Temperature Maximum DC TTL output Current Magnitude
-0.5 to +7.0 volts -0.5 to VDD + 0.5 volts -15oC to 85oC -30oC to 125oC 10mA (per o/p, one at a time, 1sec. duration)
Note: Stresses exceeding the Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied.
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Value
The optical array is centred within the package to a tolerance of 0.2 mm, and rotated no more than 0.5o
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VISION V V 5402 Sensor
DC Operating Conditions
Symbol VDD VIH VIL TA Parameter Operating supply voltage Input Voltage Logic "1" Input Voltage Logic "0" Ambient Operating Temperature Min. 4.75 2.4 -0.5 0 Typ. 5.0 Max. 5.25 VDD+0.5 0.8 70 Units Volts Volts Volts
oC
Notes
Still air
AC Operating Conditions
Symbol
CKIN CKIN
Parameter EIA Crystal frequency CCIR Crystal frequency
Min.
Typ. 12.0000 14.7456
Max.
Units MHz MHz
Notes 1 1
Electrical Characteristics
Symbol Parameter
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Min. Typ. 10 25 35 2.700 1.22 2.4 0.6 -1 1 Max. Units mA mA mA Volts Volts Volts Volts A A IOH = 2mA IOL = -2mA Notes 1 1 1
1. Pixel Clock = CKIN/2
IDCC IADD IDD
Digital supply current
Analog supply current
VREF2V7 VBG VOH VOL
IILK
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Overall supply current
Internal voltage reference Internal bandgap reference Output Voltage Logic "1" Output Voltage Logic "0"
Input Leakage current
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VIH on input VIL on input Typical conditions, VDD = 5.0 V, TA = 27oC
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1. Digital and Analogue outputs unloaded - add output current.
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Specifications
Operating Characteristics
Parameter Dark Current Signal min. typ. 50 max. units mV/Sec Note Modal pixel voltage due to photodiode leakage under zero illumination with Gain=1 (Vdark = (Vt1 - Vt2)/(t1-t2), averaged over two different frames) VAve/Lux*10ms, where Lux gives 50% saturation with Gain=1 and Exposure=10ms Standard CCIR clock Variance of Vave over eight equal blocks at 50% saturation level illumination
Sensitivity Min. Illumination Shading Random Noise Smear
6 0.5 TBA -52 TBA
V/Lux*Sec Lux % dB %
Blooming
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TBA
Lag
TBA
Note: Devices are normaly not 100% tested for the above characterisation parameters, other than Dark Current Signal (see Blemish Specification below). All voltage (VA, Vave, Vsat, Vxx%) measurements are referenced to the black level, Vblack, and spot blemishes are excluded (see Blemish Specification below). Vxx% refers to the output that is xx% of saturation, that is peak white.
Test Conditions
The sensor is tested using the example support circuit illustrated later in this document. Standard imaging conditions used for optical tests employ a tungsten halogen lamp to uniformly illuminate the sensor (to better than 0.5%), or to illuminate specific areas. A neutral density filter is used to control the level of llumination where required.
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%
Flicker
TBA
%
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Clock Frequency Exposure Gain Correction mode
RMS variance of all pixels, at 66% saturation, over four frames Ratio of Vave of the area outside a rectangle 25 lines high illuminated at 500xV50% level to VAve of the rectangle Variation of Vave of one line from field to field at 66% saturation level illumination
Average residual signal with no illumination in the field following one field of 66% sat. illumination Ratio of spot illumination level that produces 0.1xVsat output from immediately around the spot to the Vsat spot illumination level (pinhole target)
Illumination Colour Temp.
3200o K Std. CCIR Maximum x1 Off Linear
Auto. Gain Control (AGC)
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VISION V V 5402 Sensor
Blemish Specification
A Blemish is an area of pixels that produces output significantly different from its surrounding pixels for the same illumination level. The definition of a Blemish Pixel varies according to testing conditions as follows:
Test 1 - Black Frame 2 - Dark Current 3 - Pixel Variation Exposure Minimum Maximum Mid range Illumination Black Black 66% Sat. Blemish Pixel output definition Differing more than 100mV. from modal value. Output more than three times the modal value (see Dark Current Signal above). Differing more than 35mV from modal value. Note: The mode of pixel values must be within 70 mV of 66% of Vsat for all devices.
The pixel area of the sensor is divided into the following areas to qualify the blemish specification:
Area A is the central area of the array as defined by the box with sides 50% of the linear height and 50% of the linear width of the array. Area C is 10 vertical pixels by 10 horizontal pixels around the edge of the array. Area B is the remaining area of the array.
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Notes
Note: Gain is set to Minimum and Correction set to Linear for all tests; measurement of blemishes for Test 3 is conducted under standard illumination (see above), set to produce average output of 66% saturation level.
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The blemish specification is then defined as follows:
Image Area Area A Area B Of up to four connected pixels (2x2 max.) Blemishes in this area are not significant, but the device shall, however, have no row or column (>50% of row or column) faults in any area. Area C Any number Max. No. of Blemishes
This is the most critical image area Unconnected single pixels
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Area A
Area B Area C
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Pin List
Pinout Diagram
RESETB
CKOUT
BKLIT
SAB0
CCIR
CKIN
DNC
AGC
VDD
AEC
VSS
30 29 28 27 26 25 24 23 22 21 20 19 VSS 31 DNC 32 DNC 33 VDD 34 DNC 35
LIN 18 SCE 17 SIN 16 SAB1 15 VGND 14 AVO 13 VVDD 12 DNC 11 DNC 10 AVSS 9 EVWT 8 EBCK 7 AVDD 6 DNC
48 Pin LCC
Viewed from top of package
DNC 36 ODD 37 SCI 38 DNC 40 VDD 41 VSS 42 DNC 39
43 44 45 46 47 48 1 VBLWT
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2 3 4 VOFF/VPED VBLOOM VRT AVCC VBG DEC2V2
5 DEC2V7
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VCM
Pins Marked "DNC" must be left `floating'.
PIN LIST
Pin
Name
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Type PWR PWR GND PWR GND GND PWR PWR GND GND 75ohm buffer supply. 75ohm buffer ground. Core digital power. Core digital ground.
Description
POWER SUPPLIES 1 7 10 13 15 24,31 27,34 41 42 48 AVCC AVDD AVSS VVDD VGND VSS VDD DVDD DVSS AGND
Core analogue power and reference supplies. output stage power. AVDD3 output stage logic. Output stage ground. AVSS3 output stage logic.
Digital padring & logic ground. Digital padring & logic power.
Core analogue ground and reference supplies.
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VREF2V7
AGND
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VISION V V 5402 Sensor
Pin
Name
Type
Description
ANALOGUE VOLTAGE REFERENCES 2 3 4 5 8 9 43 44 45 46 47 VBG VOFF/ VPED DEC2V2 DEC2V7 EBCK EVWT VBLWT VBLOOM VRT VCM VREF2V7 OA IA OA OA IA IA IA OA IA IA OA Internal bandgap reference voltage (1.22V nominal). Requires external 0.1uF capacitor. Pedestal DAC & Offset Comp. DAC bias. Connect to VBG or external reference. Decouple 2.2V reference. Requires external 0.1uF capacitor. Decouple 2.7V reference. Requires external 0.1uF capacitor. External black level bias. Internally generated. Decouple to VGND External white pixel threshold for exposure control. Decouple to VGND
Anti-blooming voltage reference. Requires external 0.1uF capacitor.
Offset DAC common mode input. Connect to VREF2V7.
ANALOGUE OUTPUTS 14 AVO OA
Buffered Analogue video out. Can drive a doubly terminated 75ohm load.
SYSTEM CLOCKS 25 26 CKOUT CKIN OD ID
IMAGE TIMING SIGNALS 37 ODD OD
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Oscillator output. Connect Crystal for standard timing.
Oscillator input. Connect Crystal for standard timing.
Odd/even field signal. (ODD = 1 for odd fields, ODD = 0 for even)
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Internally generated 2.7V reference. Requires external 4.7uF capacitor.
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Pixel reset voltage. Connect to VREF2V7 or external reference.
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Defines white level for clamp circuitry. Requires external 0.1uF capacitor.
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Pin List
Pin
Name
Type
Description
DIGITAL CONTROL SIGNALS 16 17 18 19 20 21 22 23 28 29 38 SAB1 SIN SCE LIN SAB0 AEC AGC CCIR BKLIT ID ID ID ID ID ID ID ID ID ID Chip Address, Bit 1 Used to reset video timing control logic without resetting any other part of VV5402. Resets video logic on the falling edge of the SIN pulse. Scan Mode Enable - only relevant to test mode. Gamma corrected or Linear output. LIN = 0, gamma corrected output, LIN = 1, linear output. Default is gamma. Chip Address, Bit 0 Automatic exposure control. AEC = 1, auto exposure is enabled; AEC = 0 auto exposure and auto gain control are disabled. Automatic gain control enable. AGC = 1, auto-gain is enabled (if AEC = 1); AGC = 0, auto-gain is disabled. Select default video mode for power-on. CCIR = 1 for CCIR video. EIA video mode is selected when CCIR = 0. Default is CCIR if unconnected Normal or Backlit exposure control mode. BKLIT = 0, normal mode; BKLIT = 1, backlit mode. Default is normal. See Exposure Control for details. Active low camera reset. All camera systems are reset to power-on state. Scan Chain Input - only relevant to test mode.
RESETB SCI
OTHER PINS
6, 11, 12, 30, 32, 33, 35, 36, 39, 40
Key: OA OD OD BI Analogue output Digital output Digital output with internal pull-down Bidirectional IA ID ID DNCAnalogue input Digital input Digital input with internal pull-up Do Not Connect
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ID DNC
DO NOT CONNECT. These pins must be left `floating' for correct operation.
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VISION V V 5402 Sensor
VIDEO STANDARDS
The VV5402 has 2 different video format modes, producing CCIR or EIA standard composite Monochrome video output. Line standards and frequencies are as follows:
Video Mode CCIR EIA
Format 4:3 4:3
Image (Pixels) 384 x 287 320 x 243
Crystal Frequency 14.7456 MHz 12.0000 MHz
CCIR pin 1 0
VV5402 Video Modes
Video signal Characteristics
The following table summarises the composite video output levels (AVO) for the two standards, which are graphically illustrated on the following pages:
Symbol
Parameter
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Min. Typ. 0.3 0.9 0.9 1.0 2.3 2.4
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Max. V V V V V V
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Units
Notes
Vblank Vblack
CCIR, EIA Blanking level CCIR Black level EIA Black level
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VSync
CCIR, EIA Sync. level
DC reference level
Note: All measurements are made with AVO driving one 75 load.
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VSat
CCIR Saturation level
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EIA Saturation level
Peak White; AVO clipped at this level
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Video Standards
CCIR Timing Diagram
line time reference point line period H = 64s line sync. 4.7s back porch 5.8s
rise times (10% - 90%)
line 0.3 { line blank 0.250.1s sync. 0.05s
front porch 1.5s 2.3v
peak white level
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CCIR composite video signal - line level timing
0.9v
black & blanking level sync. level
0.3v
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frame start field 1 field 0 2.5H 2.5H 26H field 1 2.5H field 2 2.5H 25H 09/04/97
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2.5H
2.5H
CCIR composite video signal - field level timing
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VISION V V 5402 Sensor
EIA Timing Diagrams
line blank 0.3 {line sync. 0.250.1s 0.05s
line time reference point line period H = 63.5s line sync. 4.83s back porch 4.00s
rise times (10% - 90%)
front porch 1.33s
peak white level
2.4v
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EIA composite video signal - line level timing field 0
0.9v 0.3v
1.0v black level blanking level sync. level
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field 1 3H
3H
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field 1 3H 3H
frame start
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3H 19H field 2 20H
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14
3H
EIA composite video signal - field level timing
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Example Support Circuit
EXAMPLE SUPPORT CIRCUIT
AVD VDD 8
REG1
2, 3, 6, 7
1 C2
+7 to +12v dc
C1
R1 C5 C3 C6
0v
C4 27 34 41 1 7 13 14 15 R4 MONITOR C7 VDD1 VDD2 DVDD AVCC AVDD VVDD 24 31 42 10 48 VSS1 VSS2 DVSS AVSS AGND AVO VGND
1. Keep nodes Supply and Ground pins low impedance and independent 2. Video output should be referred to VGND. 3. Keep circuit components close to chip pins (especially de-coupling capacitors)
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IC1 (48 pin LCC)
CCIR
23
16 20
VDD
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SAB0 BKLIT LIN AGC AEC 44 VBLOOM VRT VCM 45 46 47 VREF2V7 SIN 17 26 C11
SAB1
28 19 22 21
SCI SCE
38 18
VV5402
Component IC1 REG1 C1,C2 C3 C4-C9,C13, C16-C19 C10 C11, C12 C14 R1 R2 R3 R4 R5 X1
Value
VV5402
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LM78L05
EBCK EVWT VBLTW DEC2V7 DEC2V2
8 9 43 5 4
C19 C18
0.22 F 68 F (6V Tant.) 0.1 F 4.7F 10 pF 100pF 5R6 10R 10M 75R 33R
C8
C17 C16 C15
R5
C9
C10
VOFF/VPED 3 CKIN CKOUT 25 R3 R2 C12 VBG
2
C13
C14
Crystal CCIR:14.7456 MHz EIA:12.0000 MHz
X1
Use Surface Mount components throughout.
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VISION V V 5402 Sensor
VLSI VISION LIMITED
UK Office Aviation House, 31 PInkhill, Edinburgh, UK EH12 7BF Tel: +44 (0)131 539 7111 Fax: +44 (0)131 539 7140 Email: info@vvl.co.uk
USA West Office 18805 Cox Avenue, Suite 260, Saratoga, California 95070, USA Tel: +1 408 374 5323 Fax: +1 408 374 4722 Email: info@vvl.co.uk
USA East Office 2517 Highway 35 Bldg F, Suite 202 Manasquan New Jersey 08736 Tel: +1 908 528 2222 Fax: +1 908 528 9305 Email: info@vvl.co.uk
(c) Copyright 1996, VLSI VISION
VLSI Vision agent or distributor
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VLSI Vision Ltd. reserves the right to make changes to its products and specifications at any time. Information furnished by VISION is believed to be accurate, but no responsibility is assumed by VISION for the use of said information, nor any infringements of patents or of any other third party rights which may result from said use. No license is granted by implication or otherwise under any patent or patent rights of any VISION group company.
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