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| N-CHANNEL 40V - 0.0036 - 100A TO-220 STripFETTM II POWER MOSFET TYPE STP100NF04L s s s s STP100NF04L VDSS 40 V RDS(on) <0.0042 ID 100 A TYPICAL RDS(on) = 0.0036 LOW THRESHOLD DRIVE 100% AVALANCHE TESTED LOGIC LEVEL DEVICE 3 1 2 DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s HIGH CURRENT, HIGH SWITCHING SPEED s MOTOR CONTROL, AUDIO AMPLIFIERS s DC-DC & DC-AC CONVERTERS s SOLENOID AND RELAY DRIVERS TO-220 INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID(*) ID IDM(*) Ptot dv/dt (1) Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 40 40 16 100 70 400 300 2 3.6 1.4 -65 to 175 175 (1) ISD 100A, di/dt 240A/s, VDD 32V, T j T JMAX (2) Starting T j = 25 oC, IAR = 50A, V DD= 30V Unit V V V A A A W W/C V/ns J C C EAS (2) Tstg Tj (*) Pulse width limited by safe operating area. (*) Current Limited by package February 2002 . 1/8 STP100NF04L THERMAL DATA Rthj-case Rthj-amb Tj Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max Typ 0.5 62.5 300 C/W C/W C ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 16 V Min. 40 1 10 100 Typ. Max. Unit V A A nA IGSS ON (*) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 A ID = 50 A ID = 50 A Min. 1 0.0036 0.0040 0.0042 0.0065 Typ. Max. Unit V DYNAMIC Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15 V ID = 20 A Min. Typ. 50 6400 1300 190 Max. Unit S pF pF pF VDS = 25V, f = 1 MHz, VGS = 0 2/8 STP100NF04L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 50 A VDD = 20 V RG = 4.7 VGS = 4.5 V (Resistive Load, Figure 3) VDD= 32V ID= 100A VGS= 4.5V Min. Typ. 37 270 72 20 28.5 90 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf tr(Voff) tf tc Parameter Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 20 V D = 50 A RG = 4.7, VGS = 4.5 V (Resistive Load, Figure 3) ID = 100 A Vclamp = 32 V RG = 4.7, VGS = 4.5 V (Inductive Load, Figure 5) Min. Typ. 90 80 85 125 160 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 100A VGS = 0 88 240 5.5 Test Conditions Min. Typ. Max. 100 400 1.3 Unit A A V ns nC A di/dt = 100A/s ISD = 100 A VDD = 20 V Tj = 150C (see test circuit, Figure 5) (*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (*)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STP100NF04L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP100NF04L Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage Temperature. . . 5/8 STP100NF04L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP100NF04L TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 F1 D G1 E Dia. L5 L7 L6 L4 P011C L9 F2 F G H2 7/8 STP100NF04L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 8/8 |
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