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Preliminary Data Sheet August 2000
TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Features
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Applications
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TRCV012G5 supports OC-48/STM-16 data rate TRCV012G7 supports: -- OC-48/STM-16 data rate -- RS (255, 239) forward error correction (FEC) OC-48/STM-16 data rate Fully-integrated limiting amplifier, clock recovery, 1:16 data demultiplexer No reference clock required for CDR 2.5 Gbits/s data output and 2.5 GHz recovered clock output available for wavelength division multiplex (WDM) or regenerator applications Programmable limiting amplifier offset Programmable data sampling phase Additional CML serial data input for system loopback Parity bit generation Analog and digital loss of signal (LOS) indicators Optional demultiplexer powerdown mode conserves power Single 3.3 V supply Available in either MBIC 025 BiCMOS technology or lower-power MBIC 025 silicon germanium BiCMOS technology High-speed LVPECL digital I/O Jitter tolerance, transfer, and generation compliant with the following: -- Telcordia Technologies* GR-253 -- ITU-T G.825 -- ITU-T G.958 Loss of signal compliant with the following: -- Telcordia Technologies GR-253
SONET/SDH line termination equipment SONET/SDH add/drop multiplexers SONET/SDH cross connects SONET/SDH test equipment
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Description
The Lucent Technologies Microelectronics Group TRCV012G5 operates at the OC-48/STM-16 data rate of 2.5 Gbits/s. The TRCV012G7 device operates at either 2.5 Gbits/s or the RS FEC OC-48/STM-16 data rate of 2.7 Gbits/s. For clarity, this data sheet refers to the TRCV012G5 serial data rate as 2.5 Gbits/s and the parallel data and reference clock frequency as 155 MHz. (The precise rates are 2.48832 Gbits/s and 155.52 MHz.) When using the TRCV012G7 at the FEC rate, the 2.5 Gbits/s data rate should be interpreted as 2.7 Gbits/s and the parallel and clock frequency should be interpreted as 166 MHz. (The precise rates are 2.66606 Gbits/s and 166.62 MHz.) The devices contain a limiting amplifier with 30 dB gain, a clock and data recovery PLL with high-speed serial clock and data outputs, and a 1:16 demultiplexer with differential PECL data and clock outputs. The device provides improved optical receiver performance when used in optically amplified systems due to a direct slice adjust input pin and a 6 ps adjustment capability in the slicing decision time. Both devices are available in either BiCMOS or in SiGe BiCMOS technology for lower power operation.
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* Telcordia Technologies is a registered trademark of Bell Communications Research, Inc.
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Table of Contents
Contents Page
Features .................................................................................................................................................................... 1 Applications ............................................................................................................................................................... 1 Description.................................................................................................................................................................1 Pin Information ..........................................................................................................................................................4 Functional Overview ................................................................................................................................................10 Limiting Amplifier .....................................................................................................................................................10 Limiting Amplifier Operation..................................................................................................................................10 Clock and Data Recovery (CDR).............................................................................................................................11 Clock Recovery Operation ....................................................................................................................................11 Clock Recovery PLL Loop Filter ...........................................................................................................................11 CDR Acquisition Time...........................................................................................................................................11 CDR Generated Jitter ...........................................................................................................................................11 CDR Input Jitter Tolerance ...................................................................................................................................12 CDR Jitter Transfer ...............................................................................................................................................12 Clock Recovery Jitter Tolerance and Jitter Transfer Specifications......................................................................13 Data Path Configuration Option (ENDATAN) .......................................................................................................14 High-Speed Serial Clock and Data Output Enables (ENCK2G5N, END2G5N)....................................................14 High-Speed Serial Data Output Mute (MUTE2G5N) ............................................................................................14 Data and CDR Configuration Options (REFSELN, INLOSN, MUTEDMXN).........................................................14 Decision Circuit--Adjustable Sampling Time (ASTREF, AST[4:0]).........................................................................15 Loss of Signal Detection..........................................................................................................................................16 Digital Loss of Signal (LOSDN).............................................................................................................................16 Analog Loss of Signal (LOSAN, PRG_LOSA) ......................................................................................................16 Demultiplexer Operation..........................................................................................................................................17 Parity Generation (PARITYP/N)............................................................................................................................17 Demultiplexer Powerdown (PDDMXN) .................................................................................................................17 Demultiplexer Data Mute (MUTEDMXN) ..............................................................................................................17 CK155P/N Low-Speed Output Mute (MUTE155N)...............................................................................................17 CML Output Structure (Used on Pins D2G5P/N, CK2G5P/N).................................................................................18 Choosing the Value of the External CML Reference Resistors (RREF1, RREF2) ...............................................18 Absolute Maximum Ratings.....................................................................................................................................19 Handling Precautions ..............................................................................................................................................19 Operating Conditions...............................................................................................................................................19 Electrical Characteristics .........................................................................................................................................20 Limiting Amplifier Specifications ...........................................................................................................................20 Optional Reference Frequency (REFCLKP/N) Specifications ..............................................................................20 LVPECL, CMOS, CML Input and Output Pins ......................................................................................................21 Timing Characteristics .............................................................................................................................................23 Output Timing .......................................................................................................................................................23 Outline Diagram.......................................................................................................................................................25 128-Pin QFP .........................................................................................................................................................25 Board Installation Recommendations ...................................................................................................................26 Thermal Considerations (MBIC 025 BiCMOS and MBIC 025 SiGe BiCMOS) .....................................................26 Ordering Information................................................................................................................................................27 DS00-234HSPL Replaces DS00-154HSPL to Incorporate the Following Updates.................................................27
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Description (continued)
Additional features include a user-programmable threshold for generating analog loss of signal (LOS) alarms, a digital LOS transition detector, an optional reference clock input that can maintain synchronization with no data input signal present, and a loopback data input. To reduce power consumption, the demultiplexer unit, high-speed serial recovered data and clock output, low-speed clock, and low-speed demultiplexer clock output can be independently powered down in applications where they are not required. The device may be used with the TTRN012G5 or TTRN012G7 transmit synthesizer and multiplexer.
ENCK2G5N LOSDN SLADJ VTHP VTHN LOSS OF DATA 0 OFFSET CANCEL & SLICE ADJUST 1 MUTE2G5 LAINP LAINN LIMITING AMPLIFIER MUTEDMX 0 D0P 1 PRG_LOSA LOSAN ENDATA DATAP DATAN ENDATAN RECOVERED CLOCK LOSS OF SIGNAL RECOVERED DATA 0 D1P 1:16 DEMULTIPLEXER 1 D1N OUTPUT REGISTER D0N CK2G5P CK2G5N END2G5N D2G5P D2G5N MUTE2G5N MUTEDMXN
ASTREF AST[4:0]
SAMPLER CIRCUIT
D15P D15N
ENDATCKN DATCKP DATCKN DATA PHASE/FREQ. DETECTION REFCLKP REFCLKN REFSELN INLOSN RESETN REFERENCE PHASE/FREQ. DETECTION INLOS CHARGE PUMP
ENDATCK
PARITY GENERATOR
PARITYP PARITYN
PDDMX 1 VCO 0 DIVIDE BY 16
PDDMXN
MUTE155 1 0
MUTE155N CK155P CK155N RREF2 RREF1
TO DIGITAL LOGIC LFP LFN VCP VCN
5-8067(F)r.2
Note: Diagram is representative of device functionality and conceptual signal flow. Internal implementation details may be different than shown.
Figure 1. Functional Block Diagram Lucent Technologies Inc. 3
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Pin Information
MUTEDMXN ENDATCKN MUTE2G5N ENCK2G5N
MUTE155N
ENDATAN
END2G5N
REFCLKN
REFSELN
REFCLKP
PDDMXN
PARITYN 104
PARITYP 105
RESETN
CK155N
INLOSN
CK155P
LOSDN
LOSAN
GND
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
GND AST4 AST3 AST2 AST1 AST0 GND VCCD VCCA VCCA NC NC GND NC GND VCN LFN LFP VCP GND GND VCCA VCCA VCCLA PRG_LOSA SLADJ VCCLA VTHP GND LAINP GND LAINN GND VTHN VCCLA GND ASTREF GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
103
GND 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VCCD
VCCD
VCCD
VCCD
NC
GND D15P D15N VCCD D14P D14N D13P D13N VCCD D12P D12N D11P D11N VCCD D10P D10N GND D9P D9N D8P D8N VCCD D7P D7N D6P D6N VCCD D5P D5N D4P D4N VCCD D3P D3N GND GND GND GND
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62 D2N
63 D2P
CK2G5N
DATAN
D2G5N
GND
GND
GND
GND
DATCKN
CK2G5P
D2G5P
DATCKP
DATAP
VCCD
VCCD
RREF2
RREF1
VCCD
GND
D0N
D1N
D0P
VCCD
VCCD
D1P
64
5-8071(F)r.5
Figure 2. Pin Diagram of 128-Pin QFP (Top View)
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Pin Information (continued)
Note: In Table 1, when operating the TRCV012G7 device at the OC-48/STM-16 rate, 2.5 Gbits/s should be interpreted as 2.48832 Gbits/s. When operating the TRCV012G7 device at the RS FEC OC-48/STM-16 rate, 2.5 Gbits/s should be interpreted as 2.66606 Gbits/s. (A similar interpretation should be made for 2.5 GHz.) Table 1. Pin Descriptions--2.5 Gbits/s and Related Signals Pin 30 32 50 51 Symbol* LAINP LAINN D2G5P D2G5N Type I O Level Analog CML Name/Description Limiting Amplifier Inputs (2.5 Gbits/s). ac coupling required. Data Output (2.5 Gbits/s NRZ). 2.5 Gbits/s differential data output.
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Pins are high impedance when END2G5N = 1.
122
END2G5N
Iu
CMOS
118
MUTE2G5N
Iu
CMOS
53 54 123
CK2G5P CK2G5N ENCK2G5N
O Iu
CML CMOS
Pins are active but forced to differential logic low when MUTE2G5N = 0. Enable D2G5P/N Data Outputs (Active-Low). 0 = D2G5P/N buffer enabled 1 or no connection = D2G5P/N buffer powered off Mute D2G5P/N Data Output (Active-Low). 0 = muted 1 or no connection = normal data Recovered Clock Output (2.5 GHz). 2.5 GHz recovered differential clock output. Pins are high impedance when ENCK2G5N = 1. Enable CK2G5P/N Clock Output (Active-Low). 0 = CK2G5P/N buffer enabled 1 or no connection = CK2G5P/N buffer powered off Resistor Reference 1. CML current bias reference resistor. (See Table 16, page 22 for values.) Resistor Reference 2. CML bias reference resistor. Place a 1.5 k resistor to VCCD. Voltage Threshold Adjust Input. This input is for monitoring purposes only and should be left open (see Figure 3 on page 10).
41 40 28 34 26 119 25 120 121
RREF1 RREF2 VTHP VTHN SLADJ LOSAN PRG_LOSA LOSDN INLOSN
I I I I O I O Iu
Analog Analog Analog Analog
18 17 19 16
LFP LFN VCP VCN
O I
Slice Level Adjustment. Adjusts slice level for the limiting amp (see Figure 3 on page 10). Open Drain Loss of Analog Signal (Active-Low). Analog Programming Voltage for LOSA Threshold. Programming voltage is scaled (see Figure 7 on page 16). Open Drain Loss of Digital Data (Active-Low). CMOS Input Loss of Signal (Active-Low). Forces VCO to decrease to its minimum frequency. 0 = force VCO low 1 or no connection = normal operation Analog Loop Filter PLL. Connect LFP to VCP, and LFN to VCN. Analog VCO Control. Connect VCP to LFP, and VCN to LFN.
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. I = input, O = output. Iu = an internal pull-up resistor on this pin, Id = an internal pull-down resistor on this pin, It = an internal termination resistance of 50 on this pin.
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Pin Information (continued)
Table 1. Pin Descriptions--2.5 Gbits/s and Related Signals (continued) Pin 43 44 124 Symbol* DATCKP DATCKN ENDATCKN Type It Iu Level CML CMOS Name/Description Clock Input for DATAP/N. Buffer is powered down when ENDATCKN = 1. External DATCKP/N Clock Select (Active-Low). Selects external DATCKP/N clock to demultiplexer. 0 = select DATCKP/N 1 or no connection = select VCO clock Data Input for CML. Use this input for system loopback data when LAINP/N is used. Enable DATAP/N Inputs (Active-Low). Selects DATAP/N as data source rather than limiting amplifier output. 0 = select DATAP/N 1 or no connection = select LAINP/N Adjustable Sampling Circuit Reference Resistor. Connect a 2.1 k resistor to VCCA. Adjustable Sampling Time Control Inputs. AST[4:0] allows introduction of an offset into the sampling time. The most significant bit (A4) is the sign bit and bits A[3:0] represent the magnitude. (See the Decision Circuit-- Adjustable Sampling Time (ASTREF, AST[4:0]) section, page 15.) A4 is the polarity bit as follows: 1 = advance 0 = delay sampling point AST[3:0] provides adjustments in steps (increments or decrements) of 6.25 ps in the sampling instant.
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. I = input, O = output. Iu = an internal pull-up resistor on this pin, Id = an internal pull-down resistor on this pin, It = an internal termination resistance of 50 on this pin.
46 47 125
DATAP DATAN ENDATAN
It Iu
CML CMOS
37 2 3 4 5 6
ASTREF AST4 AST3 AST2 AST1 AST0
I Id
Analog CMOS
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Pin Information (continued)
Note: In Table 2, when operating the TRCV012G7 device at the OC-48/STM-16 rate, 155 Mbits/s should be interpreted as 155.52 Mbits/s. When operating the TRCV012G7 device at the RS FEC OC-48/STM-16 rate, 155 Mbits/s should be interpreted as 166.62 Mbits/s. (A similar interpretation should be made for 155 MHz.) Table 2. Pin Descriptions--155.52 Mbits/s and Related Signals Pin 101 100 98 97 96 95 93 92 91 90 88 87 85 84 83 82 80 79 78 77 75 74 73 72 70 69 63 62 61 60 58 57 Symbol* D15P D15N D14P D14N D13P D13N D12P D12N D11P D11N D10P D10N D9P D9N D8P D8N D7P D7N D6P D6N D5P D5N D4P D4N D3P D3N D2P D2N D1P D1N D0P D0N Type O Level LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL Name/Description Data Output (155 Mbits/s). 155 Mbits/s differential data output. D15 is the most significant bit and is the first received on the LAINP/N or DATAP/N input. When PDDMXN = 0, data outputs can be left floating to reduce power consumption.
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. I = input, O = output. Iu = an internal pull-up resistor on this pin, Id = an internal pull-down resistor on this pin, It = an internal termination resistance of 50 on this pin.
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Pin Information (continued)
Table 2. Pin Descriptions--155.52 Mbits/s and Related Signals (continued) Pin 115 Symbol* PDDMXN Type Iu Level CMOS Name/Description Powerdown Demultiplexer Circuit (Active-Low). 0 = demultiplexer powered off, D[15:0]P/N and PARITYP/N are high-impedance 1 or no connection = demultiplexer powered on Mute Data to Demultiplexer Circuit (Active-Low). 0 = mute data 1 or no connection = normal data Recovered Clock Output (155 MHz). 155 MHz recovered differential clock output. Pins are active but forced to differential logic low when MUTE155N = 0. Mute CK155P/N Clock Output (Active-Low). Forces CK155P/N to logic low when MUTE155N is active. 0 = muted 1 or no connection = enabled Parity Input Over Data (D[15:0]). Active only when PDDMXN = 1. Reference Clock Input (155 MHz). This clock is optional. If applying the REFCLKP/N, set the REFCLKP/N to one of the following frequencies:
s
117
MUTEDMXN
Iu
CMOS
108 107 114
CK155P CK155N MUTE155N
O
LVPECL
Iu
CMOS
105 104 111 110
PARITYP PARITYN REFCLKP REFCLKN
O I
LVPECL LVPECL
155.52 MHz if using the TRCV012G5, or the TRCV012G7 at the 0C-48/STM-16 rate of 2.48832 GHz.
s
113
REFSELN
Iu
CMOS
166.62 MHz if using the TRCV012G7 at the RS FEC 0C-48/STM-16 rate of 2.66606 GHz. Reference Select to PLL. Selects LAINP/N or DATAP/N, or REFCLKP/N as the input to the CDR PLL. 0 = select REFCLKP/N 1 or no connection = select LAINP/N or DATAP/N
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. I = input, O = output. Iu = an internal pull-up resistor on this pin, Id = an internal pull-down resistor on this pin, It = an internal termination resistance of 50 on this pin.
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Pin Information (continued)
Table 3. Pin Descriptions--Global Signal Pin 116 Symbol* RESETN Type Iu Level CMOS Name/Description Reset (Active-Low). Resets all synchronous logic. During a reset, the true data outputs are in the low state and the barred data outputs are in the high state. 0 = reset 1 or no connection = normal operation
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. I = input, O = output. Iu = an internal pull-up resistor on this pin, Id = an internal pull-down resistor on this pin, It = an internal termination resistance of 50 on this pin.
Table 4. Pin Descriptions--Power and No-Connect Signals Note: VCCA, VCCLA, and VCCD have the same dc value, which is represented as VCC unless otherwise specified. However, high-frequency filtering is suggested between the individual supplies. Pin 9, 10, 22, 23 24, 27, 35 8, 42, 45, 48, 56, 59, 71, 76, 81, 89, 94, 99, 106, 109, 112, 127 13, 15, 20, 21 29, 31, 33 1, 7, 36, 38, 39, 49, 52, 55, 64--68, 86, 102, 103, 128 11, 12, 14, 126 Symbol* VCCA VCCLA VCCD Type I I I Level Power Power Power Name/Description Analog Power Supply (3.3 V). Limiting Amplifier Power Supply (3.3 V). Digital Power Supply (3.3 V).
GND
I
Ground
Ground.
NC
No Connection. These pins must be left open.
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low. I = input, O = output. Iu = an internal pull-up resistor on this pin, Id = an internal pull-down resistor on this pin, It = an internal termination resistance of 50 on this pin.
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Functional Overview
The Lucent Technologies Microelectronics Group TRCV012G5 operates at the OC-48/STM-16 data rate of 2.5 Gbits/s.* The TRCV012G7 device operates at either 2.5 Gbits/s or the RS FEC OC-48/STM-16 data rate of 2.7 Gbits/s. The device performs the data detection, clock recovery, and 1:16 demultiplexing operations required to support 2.5 Gbits/s applications compliant with Telcordia Technologies and ITU standards. A differential limiting amplifier with an adjustable threshold amplifies the 2.5 Gbits/s serial data waveform from an off-chip transimpedance amplifier (TIA). Alternatively, a CML logic level input can be selected as the data source. A PLL recovers the clock which is used to retime the data. The decision sampling phase can be adjusted for optimal system performance. The 2.5 Gbits/s serial data and the 2.5 GHz recovered clock signal are available at CML outputs, or alternatively, they can be disabled or the data can be muted. A 1:16 data demultiplexer performs the serial-to-parallel conversion and generates 16 parallel outputs at a 155 Mbits/s rate as well as a parity indicator. The parallel output data is aligned to a 155 MHz clock derived from the 2.5 GHz recovered clock. Loss of analog signal (LOSA) and loss of digital transitions (LOSD) are indicated. A 155 MHz reference clock may optionally be applied to serve as a frequency reference when data timing is lost.
Limiting Amplifier
Limiting Amplifier Operation
The limiting amplifier receives the input serial 2.5 Gbits/s data waveform from a transimpedance amplifier interface. The limiting amplifier inputs are internally terminated with 50 resistors to ensure high input return loss performance. The signal is amplified with a small signal gain of approximately 30 dB to a saturation level of approximately 800 mVp-p in order to provide a digital waveform to the clock and data recovery PLL. Full limiting is guaranteed for inputs of 15 mVp-p or greater on each input rail (30 mVp-p differential). If the input signal level is below a user-configurable threshold for a sufficiently long period of time, the LOSA signal is asserted. (For more detail on the LOSA functions, see the Analog Loss of Signal (LOSAN, PRG_LOSA) section on page 16.) A typical interface between the lightwave receiver and the limiting amplifier is shown in Figure 3. Note: It is recommended to use a differential interface from the lightwave receiver device with ac coupling. The slicing level can be adjusted by varying the voltage on the SLADJ pin within 300 mV of VCC/2. This feature can be used to improve BER performance in optical receivers and optical amplifier systems. The relationship between the external voltage and the slicing level is given in Table 9 on page 20. If the voltage at this pin is tied below 0.5 V, the external slice adjustment is disabled and only the internal offset cancellation feature is active. The user should connect the SLADJ pin to GND if the slice adjust feature is not needed. The limiting amplifier will perform in accordance with the specifications shown in Table 9.
SLADJ VTHP LIGHTWAVE RECEIVER DEVICE 0.1 F TIA 0.1 F VTHN 0.047 F LAINP LAINN 0.047 F 50 50
OFFSET CANCEL & SLICE ADJUST
LIMITING AMPLIFIER
5-8068(F)
Figure 3. Typical TIA to Limiting Amplifier Interface
* The OC-48/STM-16 data rate of 2.48832 Gbits/s is typically approximated as 2.5 Gbits/s in this document when referring to the application rate. The RS FEC OC-48/STM-16 data rate is 2.66606 Gbits/s and is approximated as 2.7 Gbits/s in this document. Similarly, the OC-3/ STM-1 data rate of 155.52 Mbits/s is typically approximated as 155 Mbits/s, and the RS FEC OC-3/STM-1 data rate of 166.62 Mbits/s is approximated as 166 Mbits/s. The exact frequencies are used only when necessary for clarity.
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Clock and Data Recovery (CDR)
Clock Recovery Operation
The CDR circuit uses a PLL to extract the clock and retime the 2.5 Gbits/s data. The 2.5 Gbits/s data and the 2.5 GHz recovered clock are available as outputs, as well as a 155 MHz clock derived from the recovered clock.
Clock Recovery PLL Loop Filter
A typical loop filter that meets the OC-48 jitter transfer template is shown in Figure 4. Connect the filter components and also connect LFP to VCP and connect LFN to VCN. The component values can be varied to adjust the loop dynamic response (see Table 5). Table 5. Clock Recovery Loop Filter Component Values Components C1* C2, C3 R1 R2 Values for 2 MHz Loop Bandwidth 0.47 F 10% 10 pF 20% 82.5 5% 100 k 5%
* Capacitor C1 should be either ceramic or nonpolar. LFP/VCP C1 C2 LFN/VCN R1 C3
5-8061(F).a
R2
Figure 4. Clock Recovery PLL Loop Filter Components
CDR Acquisition Time
The limiting amplifier plus CDR will acquire phase/frequency lock within 10 ms after powerup and a valid SONET signal or a 223 - 1 PRBS data signal is applied.
CDR Generated Jitter
The limiting amplifier plus CDR's generated jitter performance meets the requirements shown in Table 6. These specifications apply to the jitter generated at the 2.5 Gbits/s recovered clock pins (CK2G5P/N) when the following occur: no jitter is present on the input, the limiting amplifier's input signal is within the valid level range given in Table 9 on page 20, and the data sequence is a valid OC-48 SONET/SDH signal. Table 6. Clock and Data Recovery Generated Jitter Specifications Parameter Generated Jitter (p-p): Measured with 12 kHz to 20 MHz Bandpass Filter Generated Jitter (rms): Measured with 12 kHz to 20 MHz Bandpass Filter Typical 0.06 0.008 Max (Device)* 0.10 0.01 Unit UIp-p UIrms
* This denotes the device specification for system SONET/SDH compliance when the loop filter in Table 5 and Figure 4 is used.
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Clock and Data Recovery (CDR) (continued)
CDR Input Jitter Tolerance
The limiting amplifier plus CDR's jitter tolerance performance meets the requirement shown in Figure 5 on page 13 when the limiting amplifier's input signal is within the valid level range given in Table 9 on page 20, the loop filter in Figure 4 is used, and the data sequence is a valid OC-48 SONET/SDH signal.
CDR Jitter Transfer
Using the loop filter in Figure 4, the CDR's jitter transfer performance meets the requirement shown in Figure 6 when the input jitter magnitude is within the jitter tolerance requirements given in Figure 5 and the data sequence is a valid OC-48 SONET/SDH signal. This specification applies to the jitter transferred from the limiting amplifier's input to the 2.5 Gbits/s recovered clock pins (CK2G5P/N).
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Clock and Data Recovery (CDR) (continued)
Clock Recovery Jitter Tolerance and Jitter Transfer Specifications
100 UI
(10 Hz, 15 UIp-p) 10 UI
(600 Hz, 15 UIp-p)
(100 kHz, 1.5 UIp-p) 1 UI (6 kHz, 1.5 UIp-p)
0.1 UI
(1 MHz, 0.15 UIp-p)
0.01 UI 10 100 1k 10k FREQUENCY (Hz)
5-8069(F)r.1
100k
1M
10M
Figure 5. Receiver Jitter Tolerance
(2 MHz, 0.1 dB) 0
10 JITTER OUT/JITTER IN (dB)
20
30
40
50
60 1k 10k 100k FREQUENCY (Hz)
5-8062(F)r.2
1M
10M
100M
Figure 6. Receiver Jitter Transfer Lucent Technologies Inc. 13
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Clock and Data Recovery (CDR) (continued)
Data Path Configuration Option (ENDATAN)
Either the limiting amplifier (LAINP/N) or a CML logic level input (DATAP/N) can be selected as the source of the 2.5 Gbits/s data signal. The DATAP/N input can be used if the limiting amplifier is not needed, or it can be used as a system loopback path when the limiting amplifier is the normal data path. If the limiting amplifier is not used in normal operation, the LAINP/N pins should be grounded through a series ac coupling of 0.1 F.
High-Speed Serial Clock and Data Output Enables (ENCK2G5N, END2G5N)
Separate output enables are provided for the 2.5 GHz recovered clock output (CK2G5P/N) and the 2.5 Gbits/s data output (D2G5P/N). These enables are active-low CMOS inputs with internal pull-up resistors. A ground or logic low applied to the pin enables the corresponding output. When disabled, the pins should be either left floating, or be connected to a load which returns to VCC. The high-speed serial clock and data outputs must not be connected directly to ground when they are disabled.
High-Speed Serial Data Output Mute (MUTE2G5N)
The 2.5 Gbits/s data output (D2G5P/N) may be forced to a logic-low state using MUTE2G5N. This may be desirable if the quality of the input data is suspect, as may be the case under LOSA or LOSD conditions. MUTE2G5N is an active-low CMOS input.
Data and CDR Configuration Options (REFSELN, INLOSN, MUTEDMXN)
A 155 MHz clock (REFCLKP/N) may optionally be provided as a frequency reference to the clock recovery PLL in order to control the recovered clock frequency when data timing is lost, as may be the case under LOSA or LOSD conditions. If REFCLKP/N is provided, REFSELN can be used to select REFCLKP/N as the frequency reference to the clock recovery PLL. The INLOSN pin will force the VCO to decrease to its minimum frequency. This will prevent the VCO frequency from drifting to a high value during invalid signal conditions. INLOSN may be used to limit the recovered clock frequency in systems that do not provide a REFCLKP/N signal. The MUTEDMXN pin will force logic-low data into the demultiplexer, and therefore, keep all demultiplexer outputs in the logic-low state. MUTEDMXN will not affect the operation of the CDR circuits. This may be desirable if the quality of the input data is suspect as may be the case under LOSA or LOSD conditions. The user may utilize the REFSELN, INLOSN, and MUTEDMXN pins in any combination to achieve the desired response under LOS conditions.
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Decision Circuit--Adjustable Sampling Time (ASTREF, AST[4:0])
The adjustable sampling time (AST) feature allows a deliberate time offset to be introduced for the data recovery sampling instant relative to the recovered clock. The sampling instant is normally set by the clock recovery phaselocked loop (PLL) to be midway between the mean values of adjacent NRZ data polarity transitions, which provides an ideal setup and hold time margin of one half the data period. By setting the AST[4:0] control bits, the user may shift the instant at which the PLL's recovered clock samples the receive data eye. The AST[4] bit acts as a polarity setting, AST[3] represents the most significant magnitude bit, and AST[0] represents the least significant magnitude bit. Since this results in two decoded zero time offset states, AST[4:0] = 00000 is used to disable the sampling offset feature entirely and will result in traditionally defined midpoint sampling, whereas AST[4:0] = 10000 will also result in midpoint sampling by using the AST feature in its zero time offset condition. With AST[4] set to a logic high, increasing the AST[3:0] hexadecimal code causes the sampling point to monotonically advance in time; with AST[4] set to a logic low, the sample time is delayed more as AST[3:0] increases. The ASTREF pin should be tied to the positive power supply through a low-capacitance 1%, 2.1 k resistor. This provides a stable reference resistor to the AST circuitry. The AST control bit configurations and corresponding offset times are shown in Table 7. Table 7. Adjustable Sampling Time (AST) Control Code Note: When operating the TRCV012G7 at the FEC rate, the 6.25 ps step should be scaled down by 7%. AST[4:0] 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 Time Offset (ps) -93.75 -87.50 -81.25 -75.00 -68.75 -62.50 -56.25 -50.00 -43.75 -37.50 -31.25 -25.00 -18.75 -12.50 -6.25 0.00 AST[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Time Offset (ps) 0.00 6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25 62.50 68.75 75.00 81.25 87.50 93.75
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Loss of Signal Detection
The loss of signal circuits are used to detect the conditions of low input signal level or no data transitions at the input. The LOSDN and LOSAN signals can be processed and/or filtered to meet various system-dependent requirements on declaring loss of signal.
Digital Loss of Signal (LOSDN)
The LOSDN signal alarm is set when no transitions appear in the data path for more than 2.3 s. The LOSDN signal will become active before 100 s of no transitions has occurred. When ac coupling the 2.5 Gbits/s data to the high gain limiting amplifier, in the presence of no significant amplitude data transitions, noise at the limiting amplifier's input may be amplified and appear to be a data transition. This may change the state of LOSDN.
Analog Loss of Signal (LOSAN, PRG_LOSA)
Low signal levels are detected by the limiting amplifier with an optional user-programmable analog loss of signal (LOSA) threshold. As shown in Figure 7, applying a voltage to the PRG_LOSA pin will adjust the LOSA trip point. When the voltage on PRG_LOSA is 0 V, LOSAN will never be active even if the level at the limiting amplifier input is zero. When the voltage on PRG_LOSA is greater than approximately 1 V and less than 2 V, LOSAN will always be active regardless of the signal level at the limiting amplifier input. If the voltage of the PRG_LOSA pin exceeds 2 V, the threshold defaults to approximately 12 mVp-p differential. This voltage can be adjusted while monitoring the BER of the system, and is typically set to activate LOSAN for input levels corresponding to a BER of just above 10-3. LOSAN will not be asserted unless the alarm condition exists for at least 2.3 s. The LOSAN pin will be deasserted when the input level becomes greater than the LOSA threshold by an amount corresponding to 1 dB (typical) optical power input. The input resistance of the PRG_LOSA pin is typically 50 k, so a resistor voltage divider between VCC and ground may be used to set the PRG_LOSA level if the VCC tolerance and variability is adequate.
45 40 VIN (mVp-p) AT WHICH LOSA ACTIVATES DATA PATTERN 35 30 25 20 15 10 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 PROGRAM VOLTAGE
5-8070(F)r.2
1/1 PRBS 8/8
Figure 7. Typical LOSA Threshold vs. PRG_LOSA Voltage vs. Data Pattern
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Demultiplexer Operation
The serial 2.5 Gbits/s data is clocked into a 1:16 demultiplexer by the recovered 2.5 GHz clock. The demultiplexed parallel data is retimed with a 155 MHz clock that is derived from the recovered clock. The relationship between the serial input data and the parallel D[15:0] bits is given in Figure 8. D15 is the bit that was received first in time in the serial input data stream.
D15 (MSB)
D14
D1
D0 (LSB) (D0 RECEIVED LAST)
D15
(D15 RECEIVED FIRST) TIME
5-8063(F).a
Figure 8. Serial Input to Parallel Output Data Relationship
Parity Generation (PARITYP/N)
The parity pin (PARITYP/N) is a logic 0 when the number of 1s in the 16-bit output register is an even number, and the parity pin is a logic 1 when the number of 1s in the output register is an odd number.
Demultiplexer Powerdown (PDDMXN)
The entire demultiplexer and parity generator functionality can be powered down for systems requiring only the 2.5 GHz clock and data outputs. Setting PDDMXN = 0 powers down the demultiplexer and parity generation functions as well as the CK155P/N output clock signal. When PDDMXN = 0, the D[15:0] and PARITYP/N pins should be left unconnected.
Demultiplexer Data Mute (MUTEDMXN)
Setting the MUTEDMXN = 0 mutes the data going into the demultiplexer and forces all zeros to appear at the parallel outputs (D[15:0]).
CK155P/N Low-Speed Output Mute (MUTE155N)
The 155 MHz low-speed clock output (CK155P, CK155N) can be forced to logic low by setting MUTE155N, which is an active-low CMOS input with an internal pull-up resistor. A ground or logic low applied to MUTE155N mutes the CK155P/N output.
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
CML Output Structure (Used on Pins D2G5P/N, CK2G5P/N)
The CML architecture is essentially a current-steering mechanism combined with an amplifier. This makes the output swing of the signal a function of the termination resistor and the programmable output current. The user should connect external termination resistors from the CML output pins to VCC. The on-chip, 100 pull-up resistors provide a dc path when using an ac-coupled load. The voltage swing of a CML signal is typically 400 mV, half that of ECL/PECL. The lower pulse amplitude reduces noise transients, crosstalk, and EMI. It also uses half the amount of current through the termination resistors. The schematic of a typical CML output structure is shown in Figure 9.
DEVICE-INTERNAL CML OUTPUT BUFFER CIRCUIT VCC VCC 50 100 100 IOUT 50
VCC
VCC
EXTERNAL OUTPUT TERMINATION
IOUT VCC
RREF1 + 18X VREF RREF2 -
5-8065(F)r.2
Figure 9. Typical CML Output Structure
Choosing the Value of the External CML Reference Resistors (RREF1, RREF2)
The flexibility of the CML interface permits certain parameters to be customized for a particular application. The RREF1 resistor controls the CML output driver current source. Adjusting this tail current and termination resistors will allow signal amplitude control (see the CML output specifications for limitations, page 22 and page 24) and flexibility in termination schemes. With RREF2 set to 1.5 k, the equation for the CML output current is the following: Iout = (18)*(1.21)/RREF1 The CML outputs have on-chip 100 load resistors to VCC in order to accommodate capacitive ac coupling. With a 50 1% load, the effective load resistance will be 33.33 6%. For a 400 mV voltage swing into the 50 load, set RREF1 to 1.8 k. For a 600 mV voltage swing, set RREF1 to 1.2 k. In both cases, RREF2 remains fixed at a value of 1.5 k.
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Power Supply Voltage (VCC) Storage Temperature Pin Voltage Min -- -40 GND - 0.5 Max 4.0 125 VCC + 0.5 Unit V C V
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in the defined model. No industrywide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes: Device TRCV012G5 TRCV012G7 Voltage 200 V 200 V
Operating Conditions
Table 8. Recommended Operating Conditions Parameter Power Supply (dc voltage) Ground Input Voltage: Low High Temperature: Ambient Junction Power Dissipation: MBIC 025 BiCMOS MBIC 025 SiGe BiCMOS Symbol -- -- VIL VIH TA -- PD PD Min Typ Max 3.135 3.3 3.465 -- -- -- (See Table 11, (See Table 11, (See Table 11, Table 13, Table 13, Table 13, Table 15.) Table 15.) Table 15.) -40 0 -- -- -- -- 2.5 1.45 85 125 3.43 1.73 Unit V V V V C C W W
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Electrical Characteristics
Limiting Amplifier Specifications
Table 9. Limiting Amplifier Characteristics Parameter Data Input Level for Full Amplifier Limiting (differential input) Small-signal Gain Small-signal Bandwidth Input Referred Wideband Noise (dc--2.5 GHz) Input Return Loss (LAINP/LAINN pins): 100 MHz--2 GHz 2 GHz--3 GHz Input Slice Level Adjustment SLADJ Input Range Slice Feature Disable Voltage (SLADJ) Min 30 26 3 -- Typical -- 30 -- -- Max 1200 32 -- 170 Unit mVp-p dB GHz Vrms
-- -- -- VCC/2 - 0.3 --
-- -- 0.01*(SLADJ - VCC/2) -- --
-20 -15 -- Vcc/2 + 0.3 0.5
dB dB V V V
Optional Reference Frequency (REFCLKP/N) Specifications
The CDR operates without any reference clock. However, a reference clock input is available should the user want to maintain the CDR frequency lock without any data input.
s
When using the TRCV012G5 device, a 155.52 MHz differential LVPECL clock can be applied to the REFCLKP/N input. When using the TRCV012G7 device at the OC-48/STM-16 rate, a 155.52 MHz differential LVPECL clock can be applied to the REFCLKP/N input. When using the TRCV012G7 device at the RS FEC OC-48/STM-16 rate, a 166.62 MHz differential LVPECL clock can be applied to the REFCLKP/N input.
s
s
Table 10 provides the characteristics of the REFCLKP/N input. Table 10. Reference Frequency Characteristics Parameter Reference Frequency (REFCLKP/N) Reference Frequency Tolerance* Duty Cycle Temperature Supply Voltage Min -- -- -20 40 -40 3.10 Typ 155.52 166.62 -- -- -- -- Max -- -- 20 60 85 3.60 Unit MHz MHz ppm % C V
* Includes effects of power supply variation, temperature, electrical loading, and aging. The 20 ppm tolerance is required to meet SONET/SDH requirements if the reference frequency is used for system clocking when timing recovery is lost. Specified range is to be compatible with environmental specification of TRCV012G5 or TRCV012G7. Applications requiring a reduced temperature range may specify the reference frequency oscillator accordingly.
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Electrical Characteristics (continued)
LVPECL, CMOS, CML Input and Output Pins
Notes: 1. For Table 11 through Table 18, VCC = 3.3 V 5%, TA = -40 C to +85 C; these tables apply to both MBIC 025 BiCMOS and MBIC 025 SiGe BiCMOS technologies. 2. For more information on interpreting CML specifications, see the CML Output Structure (Used on Pins D2G5P/N, CK2G5P/N) section on page 18. Table 11. LVPECL Input Pin Characteristics Applicable Pins REFCLKP/N Symbol VIH VIL IIH IIL Parameter Input Voltage High Input Voltage Low Input Current High Leakage Input Current Low Leakage Conditions Referred to VCC Referred to VCC VIN = VIH (max) VIN = VIL (min) Min -1165 -1810 -- 5 Typ -- -- -- -- Max -880 -1475 20 -- Unit mV mV A A
Table 12. LVPECL Output Pin Characteristics Applicable Pins D[15:0]P/N, PARITYP/N, CK155P/N Symbol VOH Parameter Output Voltage High Conditions Load = 50 connected to VCC - 2.0 V Load = 50 connected to VCC - 2.0 V Min Typ Max Unit V
VCC - 1.31 VCC - 1.20 VCC - 0.90
VOL
Output Voltage Low
VCC - 1.95 VCC - 1.88 VCC - 1.80
V
Table 13. CMOS Input Pin Characteristics Applicable Symbol Parameter Pins VIH Input Voltage High END2G5N, ENCK2G5N, VIL Input Voltage Low RESETN, IIH Input Current High Leakage ENDATAN, Input Current Low Leakage IIL ENDATCKN, REFSELN, MUTEDMXN, PDDMXN, MUTE155N, MUTE2G5N AST[4:0] IIH Input Current High Leakage IIL Input Current Low Leakage Table 14. Open Drain Output Pin Characteristics Applicable Pins LOSAN, LOSDN Symbol VOH VOL Cl Parameter Output Voltage High Output Voltage Low Output Load Capacitance Conditions RL 5 k RL 5 k -- Min VCC - 0.5 GND -- Max VCC 0.5 30 Unit V V pF 21 Conditions -- -- VIN = VCC VIN = GND Min VCC - 1.0 GND -- -225 Max VCC 1.0 10 -- Unit V V A A
VIN = VCC VIN = GND
-- -10
225 --
A A
Lucent Technologies Inc.
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Electrical Characteristics (continued)
LVPECL, CMOS, CML Input and Output Pins (continued)
Table 15. CML Input Pin dc Characteristics Applicable Pins DATAP/N, DATCKP/N Symbol VIL VIH Parameter Input Voltage Low Input Voltage High Conditions -- Min -- -- Typ VCC - 0.4 VCC Max -- -- Unit V V
Table 16. CML Output Pin dc Characteristics Applicable Pins D2G5P/N, CK2G5P/N Symbol VOL VOH IOL IOH Parameter Output Voltage Low Output Voltage High Output Current Low Output Current High Conditions RREF2 = 1.5 k RL = 50 All signals differential Min* VCC - 1.2 -- 3.6 -- Typ VCC - 0.4 VCC 12 0 Max -- VCC + 0.3 18 1 Unit V V mA A
* Applies when RREF1 = 1 k. Applies when RREF1 = 1.8 k. Applies when RREF1 = 6 k.
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Timing Characteristics
Output Timing
The timing relationships between the 155 MHz or 166 MHz output clock (CK155P/N) and the output demultiplexer data (D[15:0]P/N) and the output parity (PARITYP/N) are shown in Figure 10.
tPERIOD CK155P OUTPUT CK155N tDD1 D[15:0]P/N OUTPUTS PARITYP/N DATA 1 tDD2 PARITY 1 PARITY 2 PARITY 3
5-7726(F).fr.4
DATA 2
DATA 3
Figure 10. Transmit Timing Waveform with 155 MHz or 166 MHz Clock The 155 MHz or 166 MHz output clock and data signals from Figure 10 are characterized in Table 17. Table 17. LVPECL Output Pin ac Timing Characteristics Applicable Pins CK155P/N Symbol -- tPERIOD tDD1 tDD2 tRISE, tFALL tSKEW Parameter Duty Cycle 155.52 MHz Clock Period 166.62 MHz Clock Period Time Delay from Clock Edge to D[15:0]P/N Edge Time Delay from Clock Edge to PARITYP/N Edge Rise, Fall Times: 20%--80% Transition Skew Rise to Fall Conditions All signals differential Min 48 -- -- 2.9 3.3 200 -100 Typ 50 6.43 6.00 3.2 4.0 500 0 Max 52 -- -- 3.9 4.7 800 100 Unit % ns ns ns ns ps ps
D[15:0]P/N, PARITYP/N, CK155P/N
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Timing Characteristics (continued)
Output Timing (continued)
The timing relationship between the 2.5 GHz or 2.7 GHz output clock (CK2G5P/N) and the 2.5 Gbits/s or 2.7 Gbits/s output data (D2G5P/N) is shown in Figure 11.
tPERIOD CK2G5P OUTPUT CK2G5N tDD OUTPUT D2G5P/N DATA 1 DATA 2 DATA 3
5-7726(F).er.4
Figure 11. Transmit Timing Waveform with 2.5 GHz or 2.7 GHz Clock The 2.5 GHz or 2.7 GHz output clock and data signals from Figure 11 are characterized in Table 18. Table 18. CML Output Pin ac Timing Characteristics Applicable Pins CK2G5P/N Symbol -- tPERIOD tDD tRISE, tFALL tSKEW Parameter Duty Cycle 2.48832 GHz Clock Period 2.66606 GHz Clock Period Time Delay from Clock Edge to D2G5P/N Edge Rise, Fall Times: 20%--80% Transition Skew Rise to Fall Conditions RREF1 = 1.8 k RREF2 = 1.5 k RL = 50 All signals differential Min 40 -- -- 151 50 -10 Typ 50 402 375 201 80 0 Max 60 -- -- 251 120 10 Unit % ps ps ps ps ps
D2G5P/N, CK2G5P/N
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Lucent Technologies Inc.
Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Outline Diagram
128-Pin QFP
Dimensions are in millimeters.
17.20 0.20 13.89 0.10 8.13 (REF)
128
2.89 (REF)
103
1
102
1
5.87 (REF) 17.52 0.18 19.86 0.10 23.20 0.20 1.600 0.150
YYWWL XXXXXKNV
Code Name
LUCENT
8.13 (REF)
0.800 0.150 DETAIL A
38 65
39
64
DETAIL A
11.43 0.18
2.80 (REF)
3.30 (REF) 0.20 0.06 2.89 (REF) 0.50 (TYP) 8.13 (REF) 0.000 TO 0.100
0.38 (REF)
(8.13)2 x 0.305 HEAT SINK
5-8416(F)r.2
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
Outline Diagram (continued)
Board Installation Recommendations
0.705 0.193 0.100 0.100 0.012 0.320 0.311 o0.032 0.060
0.050 0.019685 TYP
0.160 0.941 0.320 0.270
0.050 0.160 0.270
HEAT SINK GROUND PATTERN
5-9862 (F)r.1
Figure 12. Heat Sink Ground Pattern
Thermal Considerations (MBIC 025 BiCMOS and MBIC 025 SiGe BiCMOS)
The TRCV012G5 and TRCV012G7 devices use a square heat sink on the bottom of the package for heat dissipation. This heat sink is planar with the lead surface which contacts the board. For optimum heat transfer, the heat sink should be soldered to the application board using the suggested footprint shown above. Depending on the application more heat sinking may be required. Note: Certain precautions must be taken when using solder. For installation using a constant temperature solder, temperatures of under 300 C may be employed for periods of time up to 5 seconds, maximum. For installation with a soldering iron (battery operated or non-switching only), the soldering tip temperature should not be greater than 300 C and the soldering time for each lead must not exceed 5 seconds. Table 19. Thermal Resistance Parameter Thermal resistance, junction to board Thermal resistance, junction to ambient Symbol JB JA Conditions No air flow, device soldered to board 100 lfpm, device soldered to board 300 lfpm, device soldered to board 500 lfpm, device soldered to board Unit (C/W) 11.5 18 15.6 14.6 Lucent Technologies Inc.
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Preliminary Data Sheet August 2000
TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Ordering Information
Device Code TRCV012G5: TRCV012G5 (BiCMOS) TRCV012G53XE1 (SiGe BiCMOS) TRCV012G7: TRCV012G7 (BiCMOS) TRCV012G73XE1 (SiGe BiCMOS) -- Package Temperature Comcode (Ordering Number) 108419953 108700675 108560343 108700683 --
128-pin QFP 128-pin QFP 128-pin QFP 128-pin QFP --
-40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C --
DS00-234HSPL Replaces DS00-154HSPL to Incorporate the Following Updates
1. Added a second technology, MBIC 025 SiGe BiCMOS, to the data sheet. 2. Page 8, REFCLKP/N pins, corrected definition. 3. Page 11, Table 5, updated C1, R1, and R2 values in Clock Recovery Loop Filter Component Values. 4. Page 19, Absolute Maximum Ratings, added maximum power supply value of 4.0 V. 5. Page 19, Handling Precautions, corrected ESD threshold value from TBD to 200 V. 6. Page 19, Table 8, corrected BiCMOS power dissipation from TBD to 3.43 W in Recommended Operating Conditions; added MBIC 025 SiGe BiCMOS power dissipation values. 7. Page 19, Table 8, added junction temperature in Recommended Operating Conditions. 8. Page 21, Table 12, corrected values in LVPECL Output Pin Characteristics. 9. Page 23, Table 17, updated minimum duty cycle from 40% to 48%, maximum duty cycle from 60% to 52%, and tDD1 minimum value from 2.5 ns to 2.9 ns in LVPECL Output Pin ac Timing Characteristics. 10. Page 26, added the section Board Installation Recommendations and Thermal Considerations (MBIC 025 BiCMOS and MBIC 025 SiGe BiCMOS). 11. Page 27, Ordering Information, added MBIC 025 SiGe BiCMOS comcodes.
Lucent Technologies Inc.
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TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet August 2000
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved
August 2000 DS00-234HSPL (Replaces DS00-154HSPL)

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