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| SDRAM 16Mb H-die(x16) CMOS SDRAM 16Mb H-die SDRAM Specification Revision 1.5 August 2004 Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) Revision History Revision 0.0 (May, 2003) - Target spec release. Revision 0.1 (October, 2003) - Modified tRDL from 1CLK to 2CLK. Revision 0.2 (October, 2003) - Deleted AC parameter notes 5. Revision 0.3 (October, 2003) - Modified tRDL & deleted speed 200MHz. Revision 1.0 (November, 2003) - Revision 1.0 spec. release. Revision 1.1 (December, 2003) - Corrected PKG dimension. Revision 1.2 (January, 2004) - Deleted -10(10ns) speed. - Modified load cap 50pF -> 30pF. - Modified DC current . Revision 1.3 (January, 2004) - Corrected typo Revision 1.4 (May, 2004) - Added Note 8. sentense of tRDL parameter. CMOS SDRAM Revision 1.5 (August, 2004) - Modified CLK cycle time(tcc) parameter in AC Characteristics. ( If you want use of CL=2 not CL=3, the maximum operating frequency is 100MHz regardless of its speed bin.) Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) 512K x 16Bit x 2 Banks SDRAM FEATURES * * * * 3.3V power supply LVTTL compatible with multiplexed address two banks operation MRS cycle with address key programs -. CAS Latency ( 2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 32ms refresh period (2K cycle) CMOS SDRAM * * * * * GENERAL DESCRIPTION The K4S161622H is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/ O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. K4S161622H-TC55 K4S161622H-TC60 K4S161622H-TC70 K4S161622H-TC80 MAX Freq. 183MHz 166MHz 143MHz 125MHz LVTTL 50pin TSOP(II) Interface Package Organization 1Mx16 Row Address A0~A10 Column Address A0-A7 Row & Column address configuration Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) Package Physical Dimension CMOS SDRAM 0~8 11.760.20 10.16 0.10 (0.50) (10.76) #50 #26 0.25 TYP #1 #25 0.125+0.075 -0.035 20.95 0.10 1.20MAX 1.00 0.10 0.10MAX [ 0.075MAX ] (0.875) 0.30 +0.10 -0.05 0.35 +0.10 -0.05 0.80TYP [0.800.08] 0.05MIN 50Pin TSOP(II) Package Dimension Rev. 1.5 August 2004 (0.50) 11.76 0.20 SDRAM 16Mb H-die(x16) FUNCTIONAL BLOCK DIAGRAM CMOS SDRAM I/O Control LWE LDQM Data Input Register Bank Select Refresh Counter Output Buffer Row Decoder Sense AMP 512K x 16 Row Buffer DQi Address Register CLK ADD 512K x 16 Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Timing Register Programming Register LWCBR LDQM CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) PIN CONFIGURATION (TOP VIEW) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS CMOS SDRAM 50PIN TSOP (II) (400mil x 825mil) (0.8 mm PIN PITCH) PIN FUNCTION DESCRIPTION Pin CLK CS Name System Clock Chip Select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. CKE Clock Enable A0 ~ A10/AP BA RAS CAS WE L(U)DQM DQ0 ~ 15 VDD/VSS VDDQ/VSSQ N.C/RFU Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection/ Reserved for Future Use Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 CMOS SDRAM Unit V V C W mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high votlage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. : 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2 2 2 3 Max 4 4 4 5 Unit pF pF pF pF Clock RAS, CAS, WE, CS, CKE, L(U)DQM Address DQ0 ~ DQ15 Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70C ) CMOS SDRAM Version Parameter Symbol Test Condition 55 Operating Current (One Bank Active) Precharge Standby Current in power-down mode ICC1 ICC2P ICC2PS ICC2N Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P ICC3PS ICC3N Burst Length =1 tRCtRC(min) Io = 0 mA CKEVIL(max), tCC = 10ns CKE & CLKVIL(max), tCC = CKEVIH(min), CSVIH(min), tCC = 10ns Input signals are changed one time during 30ns CKEVIH(min), CLKVIL(max), tCC = Input signals are stable CKEVIL(max), tCC = 10ns CKE & CLKVIL(max), tCC = CKEVIH(min), CSVIH(min), tCC = 10ns Input signals are changed one time during 30ns CKEVIH(min), CLKVIL(max), tCC = Input signals are stable Io = 0 mA Page Burst 2Banks Activated tCCD = 2CLKs tRCtRC(min) CKE0.2V 155 105 150 100 1 120 60 115 2 mA 2 15 mA 5 3 mA 3 25 mA 70 105 80 95 mA 2 Unit Note Active Standby Current in non power-down mode (One Bank Active) ICC3NS Operating Current (Burst Mode) Refresh Current Self Refresh Current 15 mA ICC4 ICC5 ICC6 140 90 130 90 mA mA mA 2 3 Note : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL. 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. K4S161622H-TC Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) AC OPERATING TEST CONDITIONS (VDD = 3.3V0.3V, TA = 0 to 70C) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V CMOS SDRAM Value 2.4 / 0.4 1.4 tr / tf = 1 / 1 1.4 See Fig. 2 Vtt=1.4V Unit V V ns V 1200 Output 870 30pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0=50 50 30pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS Latency=3 CAS Latency=2 Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col.address delay Last data in to burst stop Col. address to col. address delay Mode Register Set cycle time Number of valid output data tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) tMRS(min) CAS Latency=3 CAS Latency=2 Symbol Min CLK cycle time tCC 5.5 10 11 16.5 16.5 38.5 55 2 1 1 1 2 2 1 100 55 Max 1000 Min 6 10 12 18 18 42 60 100 60 Max 1000 Min 7 10 14 20 20 49 69 1 100 70 Max 1000 Min 8 10 16 20 20 48 70 100 ns ns ns ns us ns CLK CLK CLK CLK CLK ea 4 2,8 2 2 80 Max 1000 ns 1 Unit Note Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) (AC operating conditions unless otherwise noted) Parameter CAS Latency=3 CAS Latency=2 CLK to valid output delay Output data CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 tSH tSLZ tSHZ tSS tCL CAS Latency=3 CAS Latency=2 tOH tCH tSAC Symbol Min CLK cycle time tCC 5.5 10 2 2 3 2 3 1.5 2 1 1 5 6 5 6 55 Max 1000 Min 6 10 2.5 2.5 3 2.5 3 1.5 2 1 1 5.5 6 1.75 2 1 1 5.5 6 3 5.5 6 60 Max 1000 Min 7 10 2.5 3 5.5 6 -70 Max 1000 CMOS SDRAM -80 Min 8 10 2.5 3 6 6 ns ns 6 7 ns 5, 6 Max 1000 ns 5 Unit Note 3 - ns 7 2 1 1 - 6 6 ns ns ns ns 7 7 6 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following clock unit based AC conversion table 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. Parameters depend on programmed CAS latency. 6. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 7. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 8. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit L H H CKEn-1 CKEn CS RAS CAS WE DQM BA CMOS SDRAM A10/AP A9~ A0 Note H H X H L H X X L L L H L L H X L H L L H X H L L H H X H H X X OP CODE X 1, 2 3 3 X X X V V X Row Address L H Column Address 3 3 Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection Both Banks Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable L L 4 4, 5 4 4, 5 6 H H H X X X L L L H L H H L X V X X H X V X L H H X V X X H X V L L L X V X X H X V X X X V L H X Column Address V X L H X H L H L H L X X X X X X V X X 7 X H L L H H H H L X H L X H X H X H X (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A0 ~ A10/AP, BA : Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA : Bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A10/AP is "High" at row precharge, BA is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 1.5 August 2004 |
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