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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-13602-4E 16-bit Proprietary Microcontroller CMOS F2MC-16L MB90670/675 Series MB90671/672/673/T673/P673 (MB90670 Series) MB90676/677/678/T678/P678 (MB90675 Series) s DESCRIPTION The MB90670/675 series is a member of 16-bit proprietary single-chip microcontroller F2MC*1-16L family designed to be combined with an ASIC (Application Specific IC) core. The MB90670/675 series is a highperformance general-purpose 16-bit microcontroller for high-speed real-time processing in various industrial equipment, OA equipment, and process control. The instruction set of F2MC-16L CPU core inherits AT architecture of F2MC-8 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data (32-bit). The MB90670/675 series has peripheral resources of UART0, UART1(SCI), an 8/10-bit A/D converter, an 8/16-bit PPG timer, a 16-bit reload timer, a 24-bit free-run timer, an output compare (OCU), an input capture (ICU), DTP/external interrupt circuit, an I2C*2 interface (in MB90675 series only). Embedded peripheral resources performs data transmission with an intelligent I/O service function without the intervention of the CPU, enabling real-time control in various applications. *1: F2MC stands for FUJITSU Flexible Microcontroller. *2: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. s PACKAGE 80-pin Plastic LQFP 80-pin Plastic QFP 100-pin Plastic LQFP 100-pin Plastic QFP (FPT-80P-M05) (FPT-80P-M06) (FPT-100P-M05) (FPT-100P-M06) MB90670/675 Series s FEATURES * Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at Vcc of 5.0 V) * CPU addressing space of 16 Mbytes Internal addressing of 24-bit External accessing can be performed by selecting 8/16-bit bus width (external bus mode) * Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) High code efficiency Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Enhanced execution speed 4-byte instruction queue * Enhanced interrupt function 8 levels, 32 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) * Low-power consumption (standby) mode Sleep mode (mode in which CPU operating clock is stopped) Timebase timer mode (mode in which other than oscillation and timebase timer are stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware standby mode * Process CMOS technology * I/O port MB90670 series: Maximum of 65 ports MB90675 series: Maximum of 84 ports * Timer Timebase timer/watchdog timer: 1 channel 8/16-bit PPG timer: 8-bit x 2 channels or 16-bit x 1 channel 16-bit reload timer: 2 channels 24-bit free-run timer: 1 channel * Input capture (ICU) Generates an interrupt request by latching a 24-bit free-run timer counter value upon detection of an edge input to the pin. * Output compare (OCU) Generates an interrupt request and reverse the output level upon detection of a match between the 24-bit freerun timer counter value and the compare setting value. * I2C interface (in MB90675 series only) Serial I/O port for supporting Inter IC BUS (Continued) 2 MB90670/675 Series (Continued) * UART0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used. * UART1 (SCI) With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized serial transmission (I/O extended serial) can be selectively used. * DTP/external interrupt circuit (4 channels) A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. * Wake-up interrupt Receives external interrupt requests and generates an interrupt request upon an "L" level input. * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8-bit or 10-bit resolution can be selectively used. Starting by an external trigger input. 3 MB90670/675 Series s PRODUCT LINEUP * MB90670 series Part number Item MB90671 MB90672 Mask ROM products MB90673 MB90T673 External ROM product MB90P673 One-time PROM product 48 Kbytes Classification ROM size RAM size 16 Kbytes 640 bytes 32 Kbytes 1.64 Kbytes 48 Kbytes External ROM 2 Kbytes CPU functions Number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 s (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output): 57 General-purpose I/O ports (N-ch open-drain output): 8 Total: 65 Clock synchronized transmission (500 Kbps to 2 Mbps) Clock asynchronized transmission (4800 Kbps to 500 kbps) Transmission can be performed by bi-directional serial transmission or by master/ slave connection. Clock synchronized transmission (500 Kbps to 2 Mbps) Clock asynchronized transmission (2400 Kbps to 62500 bps) Transmission can be performed by bi-directional serial transmission or by master/ slave connection. Conversion precision: 10-bit or 8-bit selectable Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 2 8-bit or 16-bit PPG operation A pulse wave of given intervals and given duty ratios can be output. Pulse cycle: 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 2 16-bit reload timer operation Interval: 125 ns to 131 ms (at machine clock of 16 MHz) External event count can be performed. Number of channel :1 Overflow interrupts or intermediate bit interrupts may be generated. Number of channels: 8 Pin input factor: A match signal of compare register Ports UART0 UART1 (SCI) 8/10-bit A/D converter 8/16-bit PPG timer 16-bit reload timer 24-bit free-run timer Output compare unit (OCU) (Continued) 4 MB90670/675 Series (Continued) Part number Item Input capture unit (ICU) Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of inputs: 4 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Number of inputs: 8 Started by an "L" level input. An interrupt generation module for switching tasks used in real-time operating systems. None 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by CMOS 2.7 V to 5.5 V MB90671 MB90672 MB90673 MB90T673 MB90P673 DTP/external interrupt circuit Wake-up interrupt Delayed interrupt generation module I2C interface Timebase timer Watchdog timer Low-power consumption (standby) mode Process Operating voltage* * : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") 5 MB90670/675 Series * MB90675 series Part number Item Classification ROM size RAM size 32 Kbytes 1.64 Kbytes MB90676 MB90677 MB90678 MB90T678 MB90P678 MB90V670 Evaluation product -- 4 Kbytes Mask ROM products 48 Kbytes 2 Kbytes 64 Kbytes One-time External ROM PROM product product None 3 Kbytes 64 Kbytes CPU functions The number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: 340 8 bits, 16 bits 1 byte to 7 bytes 1 bit, 8 bits, 16 bits 62.5 ns (at machine clock of 16 MHz) 1.5 s (at machine clock of 16 MHz, minimum value) Ports General-purpose I/O ports (CMOS output): 74 General-purpose I/O ports (N-ch open-drain output): 10 Total: 84 Clock synchronized transmission (500 Kbps to 2 Mbps) Clock asynchronized transmission (4800 Kbps to 500 Kbps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Clock synchronized transmission (500 Kbps to 2 Mbps) Clock asynchronized transmission (2400 Kbps to 62500 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Conversion precision: 10-bit or 8-bit can be selectively used. Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 2 PPG operation of 8-bit or 16-bit Pulse of given intervals and given duty ratios can be output Pulse interval 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 2 16-bit reload timer operation Interval: 125 ns to 131 ms (at machine clock of 16 MHz) External event count can be performed. Number of channel :1 Overflow interrupts or intermediate bit interrupts may be generated. Number of channels: 8 Pin input factor: a match signal of compare register UART0 UART1 (SCI) 8/10-bit A/D converter 8/16-bit PPG timer 16-bit reload timer 24-bit free-run timer Output compare (OCU) (Continued) 6 MB90670/675 Series (Continued) Part number Item Input capture (ICU) DTP/external interrupt circuit Wake-up interrupt Delayed interrupt generation module I2C interface Timebase timer Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of inputs: 4 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Number of inputs: 8 Started by an "L" level input. An interrupt generation module for switching tasks used in real-time operating systems. Serial I/O port for supporting Inter IC BUS 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by CMOS 2.7 V to 5.5 V MB90676 MB90677 MB90678 MB90T678 MB90P678 MB90V670 Watchdog timer Low-power consumption (stand-by) mode Process Power supply voltage for operation* * : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") Assurance for the MB90V670 is given only for operation with a tool at a power voltage of 2.7 V to 5.5 V, an operating temperature of 0C to 70C, and an operating frequency of 1.5 MHz to 16 MHz. s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-80P-M05 FPT-80P-M06 FPT-100P-M05 FPT-100P-M06 : Available x x x : Not available x x MB90671 MB90672 MB90673 MB90T673 MB90P673 MB90676 MB90677 MB90678 MB90T678 x x MB90P678 x x MB90V670 x x x x Note: For more information about each package, see section "s Package Dimensions." 7 MB90670/675 Series s DIFFERENCES AMONG PRODUCTS 1. Memory Size In evaluation with an evaluation product, note the difference between the evaluation chip and the chip actually used. The following items must be taken into consideration. * The MB90V670 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V670, images from FF4400H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.) * In the MB90678/MB90P678, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. 2. Mask Options Functions selected by optional settings and methods for setting the options are dependent on the product types. Refer to "s Mask Options" for detailed information. Note that mask option is fixed in MB90V670 series. 8 MB90670/675 Series s PIN ASSIGNMENT (Top view) P20/A16 P21/A17 P22/A18 P23/A19 P24/TIN0 P25/TIN1 P26/TOT0 P27/TOT1 VSS P30/ALE P31/RD P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P17/AD15/WI7 P16/AD14/WI6 P15/AD13/WI5 P14/AD12/WI4 P13/AD11/WI3 P12/AD10/WI2 P11/AD09/WI1 P10/AD08/WI0 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 RST P80/PPG1 P77/DOT7 P76/DOT6 P75/DOT5 P74/DOT4 P73/DOT3 P72/DOT2 P71/DOT1 P70/DOT0 P67/ASR3 P66/ASR2 P65/ASR1 P64/ASR0 P63/INT3 P62/INT2 P61/INT1 P60/INT0 HST MD2 P43/SIN1 P44/SOT1 P45/SCK1 P46/PPG0 P47/ATG AVCC AVRH AVRL AVSS P50/AN0 P51/AN1 VSS P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 MD0 MD1 (FPT-80P-M05) 9 MB90670/675 Series (Top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P15/AD13/WI5 P14/AD12/WI4 P13/AD11/WI3 P12/AD10/WI2 P11/AD09/WI1 P10/AD08/WI0 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 P16/AD14/WI6 P17/AD15/WI7 P20/A16 P21/A17 P22/A18 P23/A19 P24/TIN0 P25/TIN1 P26/TOT0 P27/TOT1 VSS P30/ALE P31/RD P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 X0 VSS RST P80/PPG1 P77/DOT7 P76/DOT6 P75/DOT5 P74/DOT4 P73/DOT3 P72/DOT2 P71/DOT1 P70/DOT0 P67/ASR3 P66/ASR2 P65/ASR1 P64/ASR0 P63/INT3 P62/INT2 P61/INT1 P60/INT0 HST MD2 MD1 MD0 10 P45/SCK1 P46/PPG0 P47/ATG AVCC AVRH AVRL AVSS P50/AN0 P51/AN1 VSS P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 (FPT-80P-M06) MB90670/675 Series (Top view) P21/A17 P20/A16 P17/AD15/WI7 P16/AD14/WI6 P15/AD13/WI5 P14/AD12/WI4 P13/AD11/WI3 P12/AD10/WI2 P11/AD09/WI1 P10/AD08/WI0 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS PB2 PB1 PB 0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P22/A18 P23/A19 P24/TIN0 P25/TIN1 P26/TOT0 P27/TOT1 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/PPG0 P47/ATG P80/PPG1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RST PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 P77/DOT7 P76/DOT6 P75/DOT5 P74/DOT4 P73/DOT3 P72/DOT2 P71/DOT1 P70/DOT0 P67/ASR3 P66/ASR2 P65/ASR1 P64/ASR0 P63/INT3 P62/INT2 P61/INT1 P60/INT0 P81 P82 P83 P84 P85 P86 AVCC AVRH AVRL AVSS P50/AN0 P51/AN1 VSS P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P90/SDA P91/SCL MD0 MD1 MD2 HST (FPT-100P-M05) 11 MB90670/675 Series (Top view) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15/WI7 P16/AD14/WI6 P15/AD13/WI5 P14/AD12/WI4 P13/AD11/WI3 P12/AD10/WI2 P11/AD09/WI1 P10/AD08/WI0 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS P20/A16 P21/A17 P22/A18 P23/A19 P24/TIN0 P25/TIN1 P26/TOT0 P27/TOT1 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/PPG0 P47/ATG P80/PPG1 P81 P82 P83 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB2 PB1 PB0 RST PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 P77/DOT7 P76/DOT6 P75/DOT5 P74/DOT4 P73/DOT3 P72/DOT2 P71/DOT1 P70/DOT0 P67/ASR3 P66/ASR2 P65/ASR1 P64/ASR0 P63/INT3 P62/INT2 P61/INT1 P60/INT0 HST MD2 12 P84 P85 P86 AVCC AVRH AVRL AVSS P50/AN0 P51/AN1 VSS P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P90/SDA P91/SCL MD0 MD1 (FPT-100P-M06) MB90670/675 Series s PIN DESCRIPTION Pin no. LQFP -80*1 62 63 QFP -80*2 64 65 LQFP -100*3 80 81 QFP -100*4 82 83 Pin name X0 X1 Circuit type Function A Crystal oscillator pins (Oscillation) F (CMOS) Input pins for selecting operation modes Connect directly to VCC or VSS. 39 to 41 41 to 43 47 to 49 49 to 51 MD0 to MD2 60 42 62 44 75 50 77 52 RST HST H External reset request input (CMOS/H) G Hardware standby input pin (CMOS/H) B (CMOS) General-purpose I/O port This function is valid in the single-chip mode. I/O pins for the lower 8-bit of the external address data bus This function is valid in the mode where the external bus is valid. B (CMOS) General-purpose I/O port This function is valid in the single-chip mode. I/O pins for the upper 8-bit of the external address data bus This function is valid in the mode where the external bus is valid. I/O pins for wake-up interrupts This function is valid in the single-chip mode. Because the input of the DTP/external interrupt circuit is used as required when the DTP/external interrupt circuit is enabled, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. B (CMOS) General-purpose I/O port This function becomes valid in the single-chip mode or the external address output control register is set to select a port. Output pins for the external address bus of A16 to A19 This function is valid in the mode where the external bus is valid and the upper address control register is set to select an address. 65 to 72 67 to 74 83 to 90 85 to 92 P00 to P07 AD00 to AD07 73 to 78, 75 to 80, 91 to 96, 93 to 98, P10 to P15, 79, 1, 97, 99, P16, 80 2 98 100 P17 AD08 to AD13, AD14, AD15 WI0 to WI5, WI6, WI7 1, 2, 3, 4 3, 4, 5, 6 99, 100, 1, 2 1, 2, 3, 4 P20, P21, P22, P23 A16, A17, A18, A19 *1: *2: *3: *4: FPT-80P-M05 FPT-80P-M06 FPT-100P-M05 FPT-100P-M06 (Continued) 13 MB90670/675 Series Pin no. LQFP -80*1 5, 6 QFP -80*2 7, 8 LQFP -100*3 3, 4 QFP -100*4 5, 6 Pin name P24, P25 TIN0, TIN1 Circuit type Function E General-purpose I/O port (CMOS/H) This function is always valid. Event input pins of 16-bit reload timer 0 and 1 Because this input is used as required when the 16-bit reload timer is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. E General-purpose I/O port (CMOS/H) This function is valid when outputs from 16-bit reload timer 0 and 1 are disabled. Output pins for 16-bit reload timer 0 and 1 This function is valid when output from 16-bit reload timer 0 and 1 are enabled. B (CMOS) General-purpose I/O port This function is valid in the single-chip mode. Address latch enable output pin This function is valid in the mode where the external bus is valid. B (CMOS) General-purpose I/O port This function is valid in the single-chip mode. Read strobe output pin for the data bus This function is valid in the mode where the external bus is valid. B (CMOS) General-purpose I/O port This function is valid in the single-chip mode or WRL/WR pin output is disabled. Write strobe output pin for the data bus This function is valid when WRL/WR pin output is enabled in the mode where external bus is valid. WRL is used for holding the lower 8-bit for write strobe in 16-bit access operations, while WR is used for holding 8-bit data for write strobe in 8-bit access operations. B (CMOS) General-purpose I/O port This function is valid in the single-chip mode, in the external bus 8-bit mode, or WRH pin output is disabled. Write strobe output pin for the upper 8-bit of the data bus This function is valid when the external bus 16-bit mode is selected in the mode where the external bus is valid, and WRH output pin is enabled. 7, 8 9, 10 5, 6 7, 8 P26, P27 TOT0, TOT1 10 12 7 9 P30 ALE 11 13 8 10 P31 RD 12 14 10 12 P32 WRL WR 13 15 11 13 P33 WRH *1: *2: *3: *4: FPT-80P-M05 FPT-80P-M06 FPT-100P-M05 FPT-100P-M06 (Continued) 14 MB90670/675 Series Pin no. LQFP -80*1 14 QFP -80*2 16 LQFP -100*3 12 QFP -100*4 14 Pin name P34 Circuit type B (CMOS) Function General-purpose I/O port This function is valid when both the single-chip mode and the hold function are disabled. Hold request input pin This function is valid in the mode where the external bus is valid or when the hold function is enabled. HRQ 15 17 13 15 P35 B (CMOS) General-purpose I/O port This function is valid when both the single-chip mode and the hold function are disabled. Hold acknowledge output pin This function is valid in the mode where the external bus is valid or when the hold function is enabled. HAK 16 18 14 16 P36 B (CMOS) General-purpose I/O port This function is valid when both the single-chip mode and the external ready function are disabled. Ready input pin This function is valid when the external ready function is enabled in the mode where the external bus is valid. RDY 17 19 15 17 P37 B (CMOS) General-purpose I/O port This function is valid in the single-chip mode or when the CLK output is disabled. CLK output pin This function is valid when CLK output is disabled in the mode where the external bus is valid. CLK 18 20 16 18 P40 SIN0 E General-purpose I/O port (CMOS/H) This function is always valid. Serial data input pin of UART0 Because this input is used as required when UART0 is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. E General-purpose I/O port (CMOS/H) This function is valid when serial data output from UART0 is disabled. Serial data output pin of UART0 This function is valid when serial data output from UART0 is enabled. 19 21 17 19 P41 SOT0 *1: *2: *3: *4: FPT-80P-M05 FPT-80P-M06 FPT-100P-M05 FPT-100P-M06 (Continued) 15 MB90670/675 Series Pin no. LQFP -80*1 20 QFP -80*2 22 LQFP -100*3 18 QFP -100*4 20 Pin name P42 Circuit type Function E General-purpose I/O port (CMOS/H) This function is valid when clock output from UART0 is disabled. Clock I/O pin of UART0 This function is valid when clock output from UART0 is enabled. Because this input is used as required when UART0 is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. E General-purpose I/O port (CMOS/H) This function is always valid. Serial data input pin of UART1 (SCI) Because this input is used as required when UART1 (SCI) is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. E General-purpose I/O port (CMOS/H) This function is valid when serial data output from UART1 (SCI) is disabled. Serial data output pin of UART1 (SCI) This function is valid when serial data output from UART1 (SCI) is enabled. E General-purpose I/O port (CMOS/H) This function is valid when clock output from UART1 (SCI) is disabled. Clock I/O pin of UART1 (SCI) This function is valid when clock output from UART1 (SCI) is enabled. Because this input is used as required when UART1 (SCI) is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. E General-purpose I/O port (CMOS/H) This function is valid when waveform output from 8/16-bit PPG timer 0 is disabled. Output pin of 8/16-bit PPG timer 0 This function is valid when waveform output from 8/16-bit PPG timer 0 is enabled. SCK0 21 23 19 21 P43 SIN1 22 24 20 22 P44 SOT1 23 25 22 24 P45 SCK1 24 26 23 25 P46 PPG0 *1: *2: *3: *4: FPT-80P-M05 FPT-80P-M06 FPT-100P-M05 FPT-100P-M06 (Continued) 16 MB90670/675 Series Pin no. LQFP -80*1 25 QFP -80*2 27 LQFP -100*3 24 QFP -100*4 26 Pin name P47 ATG Circuit type Function E General-purpose I/O port (CMOS/H) This function is always valid. Trigger input pin of the 8/10-bit A/D converter Because this input is used as requited when the 8/10-bit A/D converter is performing input operations, and it is necessary to stop outputs by other functions unless such outputs are made intentionally. C I/O port of an open-drain type (CMOS/H) The input function is valid when the analog input enable register is set to select a port. 30, 32, 36, 38, 31, 33, 37, 39, 33, 35, 38, 40, 34, 36, 39, 41, 35 to 38 37 to 40 41 to 44 43 to 46 P50, P51, P52, P53, P54 to P57 AN0, AN1, AN2, AN3, AN4 to AN7 Analog input pins of the 8/10-bit A/D converter This function is valid when the analog input enable register is set to select AD. 43 to 46 45 to 48 51 to 54 53 to 56 P60 to P63 INT0 to INT3 E General-purpose I/O port (CMOS/H) This function is always valid. Request input pins of the DTP/external interrupt circuit Because this input is used as required when the DTP/external interrupt circuit is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made intentionally. E General-purpose I/O port (CMOS/H) This function is always valid. Sample data input pins for ICU0 to ICU3 Because this input is used as required when the input capture (ICU) is performing input operations, and it is necessary to stop outputs from other functions unless such outputs are made intentionally. E General-purpose I/O port (CMOS/H) This function is valid when waveform output from the output compare (OCU) is disabled. Waveform output pins of OCU0 and OCU1 This function is valid when waveform output from the output compare (OCU) is enabled and output from the port is selected. 47 to 50 49 to 52 55 to 58 57 to 60 P64 to P67 ASR0 to ASR3 51 to 58 53 to 60 59 to 66 61 to 68 P70 to P77 DOT0 to DOT7 *1: *2: *3: *4: FPT-80P-M05 FPT-80P-M06 FPT-100P-M05 FPT-100P-M06 (Continued) 17 MB90670/675 Series (Continued) Pin no. LQFP -80*1 59 QFP -80*2 61 LQFP -100*3 25 QFP -100*4 27 Pin name P80 Circuit type Function E General-purpose I/O port (CMOS/H) This function is valid when waveform output from 8/16-bit PPG timer 1 is disabled. Output pin of 8/16-bit PPG timer 1 This function is valid when waveform output from 8/16-bit PPG timer 1 is enabled. E General-purpose I/O port (CMOS/H) This function is always valid. D I/O port of an open-drain type (NMOS/H) This function is always valid. I/O pin of the I2C interface This function is valid when operation of the I2C interface is enabled. Hold the port output in the high-impedance status (PDR = 1) when the I2C interface is in operation. D I/O port of an open-drain type (NMOS/H) This function is always valid. Clock I/O pin of the I2C interface This function is valid when operation of the I2C interface is enabled. Hold the port output in the high-impedance status (PDR = 1) when the I2C interface is in operation. E General-purpose I/O port (CMOS/H) This function is always valid. E General-purpose I/O port (CMOS/H) This function is always valid. Power supply Power supply Power supply Power supply Power supply Power supply Power supply to the digital circuit Ground level of the digital circuit PPG1 -- -- 26 to 31 28 to 33 P81 to P86 45 47 P90 SDA -- -- 46 48 P91 SCL -- -- -- -- 64 9, 32, 61 26 -- -- 66 11, 34, 63 28 67 to 74 69 to 76 PA0 to PA7 76 to 78 78 to 80 PB0 to PB2 21, 82 9, 40, 79 32 23, 84 11, 42, 81 34 VCC VSS AVCC Power supply to the analog circuit Make sure to turn on/turn off this power supply with a voltage exceeding AVCC applied to VCC. Reference voltage input to the analog circuit Make sure to turn on/turn off this power supply with a voltage exceeding AVRH applied to AVCC. Reference voltage input to the analog circuit Ground level of the analog circuit 27 29 33 35 AVRH 28 29 *1: *2: *3: *4: 30 31 34 35 36 37 AVRL AVSS FPT-80P-M05 FPT-80P-M06 FPT-100P-M05 FPT-100P-M06 18 MB90670/675 Series s I/O CIRCUIT TYPE Type A X1 P-ch X0 N-ch Clock input Circuit Remarks * External clock frequency 3 MHz to 32 MHz * Oscillation feedback resistor approx. 1M Standby control signal B R P-ch N-ch Digital output * CMOS level input/output (with standby control) * Pull-up option selectable (with standby control) * No pull-up resistor in the MB90V670 Digital output Digital input Standby control signal C * N-ch open-drain output * CMOS level hystheresis input (with A/D control) Digital output A/D input Digital input A/D disable D * NMOS open-drain output * CMOS level hysteresis input (with standby control) P-ch Digital output N-ch Digital input Standby control signal (Continued) 19 MB90670/675 Series (Continued) Type E R P-ch N-ch Digital output Circuit Remarks * CMOS level output * CMOS level hysteresis input (with standby control) * Pull-up option selectable (with standby control) * No pull-up resistor in the MB90V670 Digital output Digital input Standby control signal F R P-ch N-ch R Digital input * CMOS level input/output (without standby control) * Pull-up/pull-down option selectable (without stand-by control) * In mask ROM versions, MD2 pin is fixed to pull-down resistor, and optionally selectable the resistor in other pins. * The MB90V670 has no pull-up/pull-down resistors. G * CMOS level hysteresis input (without standby control) P-ch N-ch Digital input H R P-ch N-ch * CMOS level hysteresis input (without standby control) * Pull-up option selectable (without standby control) * No pull-up resistor in the MB90V670 Digital input 20 MB90670/675 Series s HANDLING DEVICES 1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up). In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS. When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating. In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH) and analog input voltages not exceed the digital voltage (VCC). 2. Connection of Unused Pins Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up or a pull-down resistor. 3. Notes on Using External Clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. * Using external clock X0 Open X1 MB90670/675 series 4. Power Supply Pins In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device. 5. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. 21 MB90670/675 Series 6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 7. Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS. 8. "MOV @AL, AH", "MOVW @AL, AH" Instructions When the above instruction is performed to I/O space, an unnecessary writing operation (#FF, #FFFF) may be performed in the internal bus. Use the compiler function for inserting an NOP instruction before the above instructions to avoid the writing operation. Accessing RAM space with the above instruction does not cause any problem. 9. Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers, turning on the power again. 22 MB90670/675 Series s PROGRAMMING TO THE ONE-TIME PROM ON THE MB90P673/P678 The MB90P673 and MB90P678 has a PROM mode for emulation operation of the MBM27C1000/1000A, to which writing codes by a general-purpose ROM writer can be done via a dedicated adapter. Please note that the device is not compatible with the electronic signature (device ID code) mode. 1. Writing Sequence The memory map for the PROM mode is shown as follows. Write option data to the option setting area according by referring to "7. PROM Option Bit Map". Normal operation mode FFFFFFH Program area (PROM) Address*2 010000H ROM image 004000H 0002CH 000000H 00000H Option setting area Address*1 1FFFFFH Program area (PROM) PROM mode Type MB90P673 MB90P678 Address*1 14000H 10000H Address*2 FF4000H FF0000H Number of bytes 48 Kbytes 64 Kbytes Note: The ROM image size for bank 00 is 48 Kbytes (ROM image for between FF4000H to FFFFFFH). Write data to the one-time PROM microcontrollers according to the following sequence. (1) Set the PROM programer to select the MBM27C1000/1000A. (2) Load the program data to the ROM programer address *1 to 1FFFFH. To select a PROM option, load the option data from 00000H to 0002CH referring to "7. PROM Option Bit Map". (3) Set the chip to the adapter socket and load the socket to the ROM programer. Make sure that the device and adapter socket are properly oriented. (4) Program from 00000H to 1FFFFH. Notes: * In mask-ROM products, there is no PROM mode and it is impossible to read data by a ROM programer. * Contact sales personnel when purchasing a ROM programer. 2. Program Mode In the MB90P673/P678, all the bits are set to "1" upon shipping from FUJITSU or erasing operation. To write data, set desired bit selectively to "0". However it is impossible to write electronically to the bits. 23 MB90670/675 Series 3. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening precedure for a product with a blanked One-time PROM microcomputer program. Program, verify Aging +150C, 48 Hrs. Data verification Assembly 4. Programming Yield All bits cannnot be programmed at Fujitsu shipping test to a blanked One-time PROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannnot be assured at all times. 5. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer Part no. Package Compatible socket adapter Sun Hayato Co., Ltd. Recommended programmer manufacturer and programmer name 1890A MB90P673PF MB90P673PFV MB90P678PF MB90P678PFV QFP-80 ROM-80QF32DP-16L -- LQFP-80 ROM-80SQF32DP-16L -- QFP-100 ROM-100QF32DP-16L -- LQFP-100 ROM-100SQF32DP-16L Recommended Minato Electronics Inc. 1891 -- -- -- Recommended 1930 -- -- -- Recommended UNISITE -- -- -- Recommended Data I/O Co., Ltd. 3900 -- -- -- Recommended 2900 -- -- -- Recommended Inquiry: San Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Minato Electronics Inc.: TEL: USA (1)-916-348-6066 JAPAN (81)-45-591-5611 Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444 EUROPE (49)-8-985-8580 24 MB90670/675 Series 6. Pin Assignment for EPROM Mode * MBM27C1000/1000A pin compatible MBM27C1000/1000A Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name VPP OE A15 A12 A07 Refer to pin assignments. A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 GND MB90P673/MB90P678 Pin no. Pin name MD2 P32 P17 P14 P27 P26 P25 P24 P23 P22 P21 P20 P00 P01 P02 VSS MBM27C1000/1000A Pin no. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin name VCC PGM N.C. A14 A13 A08 A09 A11 A16 A10 CE D07 D06 D05 D04 D03 Refer to pin assignments. MB90P673/MB90P678 Pin no. Pin name VCC P33 -- P16 P15 P10 P11 P13 P30 P12 P31 P07 P06 P05 P04 P03 * Pin assignments for products not compatible with MBM27C1000/1000A Pin no. Pin name MD0 MD1 X0 Refer to pin assignments. X1 AVCC AVRH P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P86 P90 P91 PA0 to PA7 PB0 to PB2 processing Connect a pull-up resistor of 4.7 k. OPEN * Power supply, GND connected pin Type Power supply Pin no. Refer to pin assignments. Pin name HST VCC P34 P35 P36 RST AVRL AVSS VSS GND Refer to pin assignments. Connect a pull-up resistor having a resistance of approximately 1 M to each pin. Note: Only MB90675 series has P81 to P86, P90, P91, PA0 to PA7, PB0 to PB2 pins. 25 MB90670/675 Series 7. PROM Option Bit Map Address 00000H P07 Pull-up 1: No 0: Yes P17 Pull-up 1: No 0: Yes P27 Pull-up 1: No 0: Yes P37 Pull-up 1: No 0: Yes P47 Pull-up 1: No 0: Yes P67 Pull-up 1: No 0: Yes P77 Pull-up 1: No 0: Yes Vacancy 00024H PA5 Pull-up 1: No 0: Yes Vacancy 0002CH bit 7 Vacancy bit 6 RST Pull-up 1: No 0: Yes P06 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P26 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P46 Pull-up 1: No 0: Yes P66 Pull-up 1: No 0: Yes P76 Pull-up 1: No 0: Yes P86 Pull-up 1: No 0: Yes PA4 Pull-up 1: No 0: Yes Vacancy bit 5 Vacancy bit 4 MD1 Pull-up 1: No 0: Yes P04 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P24 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes P64 Pull-up 1: No 0: Yes P74 Pull-up 1: No 0: Yes P84 Pull-up 1: No 0: Yes PA2 Pull-up 1: No 0: Yes PB2 Pull-up 1: No 0: Yes bit 3 MD1 Pull-down 1: No 0: Yes P03 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P23 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P73 Pull-up 1: No 0: Yes P83 Pull-up 1: No 0: Yes PA1 Pull-up 1: No 0: Yes PB1 Pull-up 1: No 0: Yes bit 2 MD0 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P22 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P72 Pull-up 1: No 0: Yes P82 Pull-up 1: No 0: Yes PA0 Pull-up 1: No 0: Yes PB0 Pull-up 1: No 0: Yes bit 1 MD0 Pull-down 1: No 0: Yes P01 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P21 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P71 Pull-up 1: No 0: Yes P81 Pull-up 1: No 0: Yes Vacancy bit 0 Vacancy 00004H P05 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P25 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes P65 Pull-up 1: No 0: Yes P75 Pull-up 1: No 0: Yes P85 Pull-up 1: No 0: Yes PA3 Pull-up 1: No 0: Yes Vacancy P00 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P20 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes P70 Pull-up 1: No 0: Yes P80 Pull-up 1: No 0: Yes Vacancy 00008H 0000CH 00010H 00014H 0001CH 00020H 00028H PA7 Pull-up 1: No 0: Yes PA6 Pull-up 1: No 0: Yes Notes: * Data "1" must be programed to the reserved bits and address other than listed above. * Only MB90P678 has pull-up options for P81 to P86, PA0 to PA7, and PB0 to PB2 pins. * Data "1" must be programed for the MB90P673. 26 MB90670/675 Series s BLOCK DIAGRAM F2MC-16L CPU Interrupt controller Port 5 X0 X1 RST HST P10/AD08/WI0 to P17/AD15/WI7 8 Clock control block (including timebase timer) 8/10-bit A/D converter Wake-up interrupt Port 0, 1 Port 4 P00/AD00 to P07/AD07 8 16 Internal data bus UART0 8 8 P50/AN0 to P57/AN7 AVCC AVRH AVRL AVSS P47/ATG 8 P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 P45/SCK1 4 P20/A16 to P23/A19 P30/ALE P31/RD P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK External bus interface 2 10 UART1 (SCI) 16-bit PPG timer 8-bit PPG timer 0 P46/PPG0 Port 2, 3 P24/TIN0 P26/TOT0 16-bit reload timer 0 8-bit PPG timer 1 6 Port 8 Port 6 P80/PPG1 P81 to P86 P25/TIN1 P27/TOT1 16-bit reload timer 1 DTP/external interrupt circuit 0 to 3 Input capture (ICU) 4 4 P60/INT0 to P63/INT3 Port 7 4 4 4 Output compare (unit 0) P64/ASR0 to P67/ASR3 P70/DOT0 to P77/DOT7 8 24-bit free-run timer 4 Output compare (unit 1) Port A, B * Port 9* 8 3 PA0 to PA7 PB0 to PB2 P90/SDA P91/SCL Other pins VCC,VSS, MD0 to MD2 2 I2C interface * RAM ROM * : Not included in the MB90670 series. 27 MB90670/675 Series s MEMORY MAP FFFFFFH Single-chip mode ROM area Address#1 100000H External area 010000H ROM area (image of bank FF) ROM area (image of bank FF) External area Internal ROM external bus mode ROM area External ROM external bus mode *1 Address #2 004000H 002000H Address #3 External area RAM Register 000100H 0000C0H 000000H Peripheral RAM Register External area Peripheral RAM Register External area Peripheral Part number MB90671 MB90672 MB90673 MB90T673 MB90P673 MB90676 MB90677 MB90678 MB90T678 MB90P678 : Internal access memory : Enternal access memory : Inhibited area Address #1*2 FFC000H FF8000H FF4000H -- FF4000H FF8000H FF4000H FF0000H -- FF0000H Address #2 *2 00C000H 008000H 004000H -- 004000H 008000H 004000H 004000H -- 004000H Address #3 *2 000380H 000780H 000900H 000900H 000900H 000780H 000900H 000D00H 000D00H 000D00H *1: The same external memory is accessed for bank 0F, 1F, 2F through FF. *2: Addresses #1, #2 and #3 are unique to the product type. Notes: * The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the ROM without stating "far". However, the ROM area of the MB90678/P678 exceeds 48 Kbytes, and for this reason, the image from FF4000H to FFFFFFH is reflected on bank 00 and image from FF0000H to FF3FFFH bank FF only. * In the MB90670/675 series, the upper 4-bit of the address are not output to the external bus. For this reason, the maximum area accessible is 1 Mbyte. The same address is accessed through different banks in different images. For example, accessing "A00000H" and "B00000H" accesses the same address on the external bus. * To prevent the memory or I/O from being accessed through images, and the data from being destroyed, it is recommended to limit number of banks to a maximum of 16 so that the banks are mapped without interfering each other. Caution must be also taken when masking the upper address with the external address output control register (HACR). 28 MB90670/675 Series s F2MC-16L CPU PROGRAMMING MODEL (1) Dedicated Registers AH AL : Accumlator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating a user stack address. : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. : Processor status (PS) The 16-bit register indicating the system status. : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. DPR : Direct page register (DPR) The 8-bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) The 8-bit register indicating the program space. : Data bank register (DTB) The 8-bit register indicating the data space. : User stack bank register (USB) The 8-bit register indicating the user stack space. : System stack bank register (SSB) The 8-bit register indicating the system stack space. : Additional data bank register (ADB) The 8-bit register indicating the additional space. USP SSP PS PC PCB DTB USB SSB ADB 8-bit 16-bit 32-bit 29 MB90670/675 Series (2) General-purpose Registers Maximum of 32 banks R7 R5 R3 R1 RW3 R6 R4 R2 R0 RW7 RL3 RW6 RW5 RL2 RW4 RL1 RW2 RW1 RL0 000180 H + (RP x 10 H ) RW0 16-bit (3) Processor Status (PS) ILM RP CCR bit 5 bit 4 S 1 T X bit 3 bit 2 N X Z X bit 1 V X bit 0 C X bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 PS Initial value -- : Unused X : Indeterminate ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 -- -- I 0 30 MB90670/675 Series s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH to 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH to 00001EH 00001FH EICR DDRA DDRB EIFR DDR0 DDR1 DDR2 DDR3 DDR4 ADER DDR6 DDR7 DDR8 Abbreviated register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port B data register Read/ write R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W (Vacancy)*3 Wake-up interrupt flag register Port 0 data direction register Port 1 data direction register Port 2 data direction register Port 3 data direction register Port 4 data direction register Analog input enable register Port 6 data direction register Port 7 data direction register Port 8 data direction register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 3 Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8* 5 Initial value XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B 11111111B XXXXXXXX B XXXXXXXX B - XXXXXXX B ------11B XXXXXXXX B - - - - - XXX B Port 9*5 Port A*5 Port B* 5 Wake-up interrupt Port 0 Port 1 Port 2 Port 3 Port 4 Port 5, analog input Port 6 Port 7 Port 8*5 -------0B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 00000000B 00000000B -0000000B (Vacancy)* Port A data direction register Port B data direction register R/W R/W Port A*5 Port B*5 00000000B -----000B (Vacancy)*3 Wake-up interrupt enable register W Wake-up interrupt 00000000B (Continued) 31 MB90670/675 Series Address 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH Abbreviated register name UMC0 USR0 UIDR0/ UODR0 URD0 SMR1 SCR1 SIDR1/ SODR1 SSR1 ENIR EIRR ELVR Register name Mode control register 0 Status register 0 Input data register 0/ output data register 0 Rate and data register 0 Mode register 1 Control register 1 Input data register 1/ output data register 1 Status register 1 DTP/interrupt enable register DTP/interrupt factor register Request level setting register Read/ write R/W! R/W! R/W R/W R/W R/W! R/W R/W! R/W R/W R/W 3 Resource name Initial value 00000100B 00010000B UART0 XXXXXXXX B 00000000B 00000000B 00000100B XXXXXXXX B 00001-00B ----0000B UART1 (SCI) DTP/external interrupt circuit ----0000B 00000000B (Vacancy)* ADCS ADCR PPGC0 PPGC1 A/D convertor control status register A/D convertor data register PPG0 operating mode control register PPG1 operating mode control register R/W! 8/10-bit A/D converter R/W!*4 R/W! R/W! 8/16-bit PPG timer 0 8/16-bit PPG timer 1 00000000B 00000000B XXXXXXXX B 0 0 0 0 0 0XXB 0-000001B 00000000B (Vacancy)*3 PRLL0 PRLH0 PRLL1 PRLH1 TMCSR0 TMR0/ TMRLR0 TMCSR1 TMR1/ TMRLR1 PPG0 reload register PPG1 reload register Timer control status register 0 16-bit timer register 0/ 16-bit reload register 0 Timer control status register 1 16-bit timer register 1/ 16-bit reload register 1 R/W R/W R/W R/W R/W! 16-bit reload timer 0 R/W R/W! 16-bit reload timer 1 R/W 8/16-bit PPG timer 0 8/16-bit PPG timer 1 XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B 00000000B ----0000B XXXXXXXX B XXXXXXXX B 00000000B ----0000B XXXXXXXX B XXXXXXXX B (Continued) 32 MB90670/675 Series Address 000040H 000041H 000042H 000043H 000044H 000045H to 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H Abbreviated register name IBSR IBCR ICCR IADR IDAR Register name I2C bus status register I C bus control register I2C bus clock control register I2C bus address register I C bus data register 2 2 Read/ write R R/W R/W R/W R/W (Vacancy)*3 Resource name Initial value 00000000B 00000000B I2C interface*6 - - 0 XXXXX B - XXXXXXX B XXXXXXXX B TCCR ICC TCRL TCRH CCR00 CCR01 CCR10 CCR11 ICDR0L ICDR0H ICDR1L ICDR1H ICDR2L Free-run timer control register ICU control register Free-run timer lower data register Free-run timer upper data register OCU control register 00 OCU control register 01 OCU control register 10 OCU control register 11 ICU lower data register 0 ICU upper data register 0 ICU lower data register 1 ICU upper data register 1 ICU lower data register 2 R/W! R/W R 24-bit free-run timer Input capture (ICU) 11000000B --111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11110000B 24-bit free-run timer R R/W R/W R/W R/W R R R R R Input capture (ICU) Output compare (OCU) (unit 0) ----0000B ----0000B 00000000B 11110000B Output compare (OCU) (unit 1) ----0000B ----0000B 00000000B XXXXXXXX B XXXXXXXX B XXXXXXXX B 00000000B XXXXXXXX B XXXXXXXX B XXXXXXXX B 00000000B XXXXXXXX B XXXXXXXX B (Continued) 33 MB90670/675 Series Address 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH Abbreviated register name ICDR2H ICDR3L ICDR3H CPR00L CPR00H CPR01L CPR01H CPR02L CPR02H CPR03L CPR03H CPR04L CPR04H CPR05L CPR05H CPR06L CPR06H Register name ICU upper data register 2 ICU lower data register 3 ICU upper data register 3 OCU compare lower data register 0 OCU compare upper data register 0 OCU compare lower data register 1 OCU compare upper data register 1 OCU compare lower data register 2 OCU compare upper data register 2 OCU compare lower data register 3 OCU compare upper data register 3 OCU compare lower data register 4 OCU compare upper data register 4 OCU compare lower data register 5 OCU compare upper data register 5 OCU compare lower data register 6 OCU compare upper data register 6 Read/ write R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXX B 00000000B XXXXXXXX B XXXXXXXX B XXXXXXXX B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B Input capture (ICU) Output compare (OCU) (unit 0) 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B Output compare (OCU) (unit 1) 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 34 MB90670/675 Series Address 00008CH 00008DH 00008EH 00008FH 000090H to 00009EH 00009FH Abbreviated register name CPR07L CPR07H Register name OCU compare lower data register 7 OCU compare upper data register 7 Read/ write R/W R/W Resource name Output compare (OCU) (unit 1) Initial value 00000000B 00000000B 00000000B 00000000B (System reservation area)*1 Delayed interrupt factor generation/ cancellation register Low-power consumption mode control register Clock selection register Delayed interrupt generation module Low-power consumption (stand-by) mode Low-power consumption (stand-by) mode DIRR R/W -------0B 0000A0H LPMCR R/W! 00011000B 0000A1H 0000A2H to 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH to 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H CKSCR R/W! 11111100B (Vacancy)*3 ARSR HACR EPCR WDTC TBTC Automatic ready function select register Upper address control register Bus control signal select register Watchdog timer control register Timebase timer control register W W W R/W! R/W! External bus pin External bus pin External bus pin Watchdog timer Timebase timer 0011--00B ----0000B 0000 * 00-B XXXXX1 1 1 B 1--00100B (Vacancy)*3 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! Interrupt controller 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B (Continued) 35 MB90670/675 Series (Continued) Address 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH Abbreviated register name ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Register name Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Read/ write R/W! R/W! R/W! R/W! R/W! R/W! Interrupt controller Resource name Initial value 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B (External area)*2 36 MB90670/675 Series Descriptions for read/write R/W: Readable and writable R: Read only W: Write only R/W!: Bits for reading operation only or writing operation only are included. Refer to the register lists for specific resource for detailed information. Descriptions for initial value 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". * : The initial value of this bit is "1" or "0" (decided by levels on pins of MD0 through MD2). X : The initial value of this bit is indeterminate. - : This bit is not used. The initial value is indeterminate. *1: Access prohibited. *2: This area is the only external access area having an address of 0000FFH or lower. An access operation to this area is handled as that to external I/O area. *3: The area corresponding to the "(Vacancy)" on the I/O map is reserved, and accessing operation to this area is handled as that to internal area. No access signal to external devices are generated. *4: Only bit 15 is writable. Reading bit 10 through bit 15 returns "0" as a reading result. *5: In the MB90670 series, P81 through P86, P90, P91, PA0 through PA7, PB0 through PB2 are not present. For this reason, bits corresponding to these pins are not used. *6: The MB90670 series does not have the I2C interface. For this reason, this area is "(Vacancy)" in the MB90670 series. Note: For bits that is only allowed to program, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed. 37 MB90670/675 Series s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt source Reset INT9 instruction Exception DTP/external interrupt circuit Channel 0 DTP/external interrupt circuit Channel 1 DTP/external interrupt circuit Channel 2 DTP/external interrupt circuit Channel 3 Output compare Channel 0 Output compare Channel 1 Output compare Channel 2 Output compare Channel 3 Output compare Channel 4 Output compare Channel 5 Output compare Channel 6 Output compare Channel 7 24-bit free-run timer Overflow 24-bit free-run timer Intermediate bit Input capture Channel 0 Input capture Channel 1 Input capture Channel 2 Input capture Channel 3 16-bit reload timer/ 8/16-bit PPG timer 0 16-bit reload timer/ 8/16-bit PPG timer 1 8/10-bit A/D converter measurement complete Wake-up interrupt Timebase timer interval interrupt x x EI2OS support x x x Interrupt vector Number # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 33 # 34 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 21H 22H Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H ICR00 FFFFCCH FFFFC8H ICR01 FFFFC4H FFFFC0H ICR02 FFFFBCH FFFFB8H ICR03 FFFFB4H FFFFB0H ICR04 FFFFACH FFFFA8H ICR05 FFFFA4H FFFFA0H ICR06 FFFF9CH FFFF98H ICR07 FFFF94H FFFF90H ICR08 FFFF8CH FFFF88H ICR09 FFFF84H FFFF80H FFFF78H FFFF74H ICR10 ICR11 0000BAH 0000BBH*2 0000B9H*2, *3 0000B8H*2 0000B7H*2 0000B6H*2 0000B5H*2 0000B4H*2 0000B3H*2 0000B2H*2 0000B1H*2 0000B0H*2 Interrupt control register ICR -- -- -- Address -- -- -- Priority*4 High Low (Continued) 38 MB90670/675 Series (Continued) Interrupt source UART1 (SCI) transmission complete UART0 transmission complete UART1 (SCI) reception complete I2C interface*1 UART0 reception complete Delayed interrupt generation module : Can be used x : Can not be used : Can be used. With EI2OS stop function. : Can be used if interrupt request using ICR are not commonly used. *1: In MB90670 series, this interrupt vector is not used because the series does not have the I2C interface. *2: * Interrupt levels for peripherals that commonly use the ICR register are in the same level. * When the extended intelligent I/O service (EI2OS) is specified in a peripheral device commonly using the ICR register, only one of the functions can be used. * When the extended intelligent I/O service (EI2OS) is specified for one of the peripheral functions, interrupts can not be used on the other function. *3: Only 16-bit reload timer conforms to the extended intelligent I/O service (EI2OS). Because the 8/16-bit PPG timer does not conform to the extended intelligent I/O service (EI2OS), disable interrupts of the 8/16-bit PPG timer when using the extended intelligent I/O service (EI2OS) in the 16-bit reload timer. *4: The level shows priority of same level of interrupt invoked simultaneously. x x EI2OS support Interrupt vector Number # 35 # 36 # 37 # 38 # 39 # 42 23H 24H 25H 26H 27H 2AH Address FFFF70H ICR12 FFFF6CH FFFF68H FFFF64H FFFF60H FFFF54H ICR13 ICR14 ICR15 0000BDH*2 0000BEH 0000BFH Low 0000BCH*2 Interrupt control register ICR Address High Priority*4 39 MB90670/675 Series s PERIPHERALS 1. I/O Port (1) Input/output Port Port 0 to 4, 6, 8, A, and B are general-purpose I/O ports having a combined function as an external bus pin and a resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. In the external bus mode, the ports are configured as external bus pins, and part of pins for port 3 can be configured as general-purpose I/O port by setting the bus control signal select register (ECSR). Each pin corresponding to upper 4-bit of the port 2 can be switched between a resource and a port bitwise. Only MB90675 series has port A and port B. * Operation as output port The pin is configured as an output port by setting the corresponding bit of the DDR register to "1". Writing data to PDR register when the port is configured as output, the data is retained in the output latch in the PDR and directly output to the pin. The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR register. Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR register for output, however, values of bits configured by the DDR register as inputs are changed because input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR register as output after writing output data to the PDR register when configuring the bit used as input as outputs. * Operation as input port The pin is configured as an input by setting the corresponding bit of the DDR register to "0". When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance status. When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs are unaffected. Reading the PDR register reads out the pin level ("0" or "1"). * Block diagram PDR (port data register) PDR read Internal data bus Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) DDR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode N-ch Pin P-ch 40 MB90670/675 Series (2) N-ch Open-drain Port Port 5 and port 9 are general-purpose I/O ports having a combined function as resource input/output. Each pin can be switched between resource and port bitwise. Only MB90675 series has port 9. * Operation as output port When a data is written into the PDR register, the data is latched to the output latch of PDR. When the output latch value is set to "0", the output transistor is turned on and the pin status is put into an "L" level output, while writing "1" turns off the transistor and put the pin in a high-impedance status. If the output pin is pulled-up, setting output latch value to "1" puts the pin in the pull-up status. Reading the PDR register returns the pin value (same as the output latch value in the PDR). Note: Execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value rather than the pin value, leaving output latch that is not manipulated unchanged. * Operation as input port Setting corresponding bit of the PDR register to "1" turns off the output transistor and the pin is put into a highimpedance status. Reading the PDR register returns the pin level ("0" or "1"). * Block diagram of port 5 ADER (analog input enable register) ADER read ADER latch ADER write Internal data bus PDR (port data register) To analog input PDR read RMW (read-modify-write instruction) Pin Output trigger Output latch PDR write Standby control (SPL=1) Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode * Block diagram of port 9 From resource output To resource input Internal data bus PDR (port data register) RMW (read-modifywrite instruction) Standby control (SPL=1) PDR read Output latch PDR write Output trigger Pin Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode 41 MB90670/675 Series (3) Output Port Port 7 is a general-purpose output port having a combined function as an output compare (OCU) output. Note that only OCU output can be output when the pin is configured as an output, and it is not used for outputting given data by writing to the data register. Each pin can be switched between an output compare output and a port bitwise. * Operation as output port (operation of OCU output) Setting the corresponding bit of the DDR register to "1" configures the pin as an output port. In this case, lower 4-bit of CCR01 and CCR register are output. When configured as an output, the output buffer is turned on and data retained in the output latch in the PDR of the output compare is output to the pin. Writing data to DOT bit of the OCU control register (CCR01, CCR11) corresponding to each pin writes data in synchronization to a match operation of the output compare and output to the pin. Reading the PDR register returns the pin level (same as the output latch value of the PDR). When output of output compare is enabled, an output value from the output compare can be read out. * Operation as input port Setting corresponding bit of the DDR register to "0" configures the pin as input port. When the pin is configured as an input port, the output buffer is turned off and the pin is put into a highimpedance status. Reading the PDR register returns the pin level ("0" or "1"). * Block diagram PDR (port data register) PDR read Internal data bus OCU control register OCU control register write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) DDR read N-ch Pin P-ch Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode 42 MB90670/675 Series (4) Register Configuration Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000000H (PDR1) P07 R/W Address 000001H bit 15 P17 R/W bit 14 P16 R/W bit 13 P15 R/W bit 12 P14 R/W bit 6 P06 R/W bit 11 P13 R/W bit 6 P26 R/W bit 11 P33 R/W bit 6 P46 R/W bit 11 P53 R/W bit 6 P66 R/W bit 11 P73 R/W bit 6 P86 R/W bit 11 -- R/W bit 6 PA6 R/W bit 11 -- R/W bit 5 P05 R/W bit 10 P12 R/W bit 5 P25 R/W bit 10 P32 R/W bit 5 P45 R/W bit 10 P52 R/W bit 5 P65 R/W bit 10 P72 R/W bit 5 P85 R/W bit 10 -- R/W bit 5 PA5 R/W bit 10 PB2 R/W bit 4 P04 R/W bit 9 P11 R/W bit 4 P24 R/W bit 9 P31 R/W bit 4 P44 R/W bit 9 P51 R/W bit 4 P64 R/W bit 9 P71 R/W bit 4 P84 R/W bit 9 P91 R/W bit 4 PA4 R/W bit 9 PB1 R/W bit 3 P03 R/W bit 8 P10 R/W bit 3 P23 R/W bit 8 P30 R/W bit 3 P43 R/W bit 8 P50 R/W bit 3 P63 R/W bit 8 P70 R/W bit 3 P83 R/W bit 8 P90 R/W bit 3 PA3 R/W bit 8 PB0 R/W bit 2 P02 R/W bit 1 P01 R/W bit 0 P00 R/W Port 1 data register (PDR1) Port 0 data register (PDR0) bit 7. . . . . . . . . . . . bit 0 (PDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000002H (PDR3) P27 R/W Address 000003H bit 15 P37 R/W bit 14 P36 R/W bit 13 P35 R/W bit 12 P34 R/W bit 2 P22 R/W bit 1 P21 R/W bit 0 P20 R/W Port 3 data register (PDR3) bit 0 P40 R/W Port 5 data register (PDR5) bit 0 P60 R/W Port 7 data register (PDR7) bit 0 P80 R/W Port 9 data register (PDR9) bit 0 PA0 R/W Port B data register (PDRB) Port A data register (PDRA) Port 8 data register (PDR8) Port 6 data register (PDR6) Port 4 data register (PDR4) Port 2 data register (PDR2) bit 7. . . . . . . . . . . . bit 0 (PDR2) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000004H (PDR5) P47 R/W Address 000005H bit 15 P57 R/W bit 14 P56 R/W bit 13 P55 R/W bit 12 P54 R/W bit 2 P42 R/W bit 1 P41 R/W bit 7. . . . . . . . . . . . bit 0 (PDR4) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000006H (PDR7) P67 R/W Address 000007H bit 15 P77 R/W bit 14 P76 R/W bit 13 P75 R/W bit 12 P74 R/W bit 2 P62 R/W bit 1 P61 R/W bit 7. . . . . . . . . . . . bit 0 (PDR6) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000008H (PDR9) -- R/W Address 000009H bit 15 -- R/W bit 14 -- R/W bit 13 -- R/W bit 12 -- R/W bit 2 P82 R/W bit 1 P81 R/W bit 7. . . . . . . . . . . . bit 0 (PDR8) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000AH (PDRB) PA7 R/W Address 00000BH bit 15 -- R/W bit 14 -- R/W bit 13 -- R/W bit 12 -- R/W bit 2 PA2 R/W bit 1 PA1 R/W bit 7. . . . . . . . . . . . bit 0 (PDRA) (Continued) 43 MB90670/675 Series (Continued) Address bit-15 . . . . . . . . . . . . bit 8 000010H (DDR1) bit 7 P07 R/W bit 6 P06 R/W bit 11 P13 R/W bit 6 P26 R/W bit 11 P33 R/W bit 6 P46 R/W bit 11 P53 bit 5 P05 R/W bit 10 P12 R/W bit 5 P25 R/W bit 10 P32 R/W bit 5 P45 R/W bit 10 P52 bit 4 P04 R/W bit 9 P11 R/W bit 4 P24 R/W bit 9 P31 R/W bit 4 P44 R/W bit 9 P51 bit 3 P03 R/W bit 8 P10 R/W bit 3 P23 R/W bit 8 P30 R/W bit 3 P43 R/W bit 8 P50 bit 2 P02 R/W bit 1 P01 R/W bit 0 P00 R/W Port 1 data direction register (DDR1) Port 0 data direction register (DDR0) Address 000011H bit 15 P17 R/W bit 14 P16 R/W bit 13 P15 R/W bit 12 P14 R/W bit 7. . . . . . . . . . . . bit 0 (DDR0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000012H (DDR3) P27 R/W Address 000013H bit 15 P37 R/W bit 14 P36 R/W bit 13 P35 R/W bit 12 P34 R/W bit 2 P22 R/W bit 1 P21 R/W bit 0 P20 R/W Port 3 data direction register (DDR3) bit 0 P40 R/W Analog input enable register (ADER) bit 0 P60 R/W Port 7 data direction register (DDR7) bit 0 P80 R/W bit 0 PA0 R/W Port B data direction register (DDRB) Port A data direction register (DDRA) Port 8 data direction register (DDR8) Port 6 data direction register (DDR6) Port 4 data direction register (DDR4) Port 2 data direction register (DDR2) bit 7. . . . . . . . . . . . bit 0 (DDR2) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000014H (ADER) P47 R/W Address 000015H bit 15 P57 bit 14 P56 bit 13 P55 bit 12 P54 bit 2 P42 R/W bit 1 P41 R/W bit 7. . . . . . . . . . . . bit 0 (DDR4) R/W R/W R/W R/W R/W R/W R/W R/W . . . . . . . . . . . . bit 8 bit 7 Address bit 15 bit 6 bit 5 bit 4 bit 3 bit 2 000016H (DDR7) P67 R/W Address 000017H bit 15 P77 bit 14 P76 bit 13 P75 bit 12 P74 P66 R/W bit 11 P73 P65 R/W bit 10 P72 P64 R/W bit 9 P71 P63 R/W bit 8 P70 P62 R/W bit 1 P61 R/W bit 7. . . . . . . . . . . . bit 0 (DDR6) R/W R/W R/W R/W R/W R/W R/W R/W . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Address bit 15 000018H (Vacancy) -- P86 R/W bit 6 PA6 R/W bit 11 -- R/W P85 R/W bit 5 PA5 R/W bit 10 PB2 R/W P84 R/W bit 4 PA4 R/W bit 9 PB1 R/W P83 R/W bit 3 PA3 R/W bit 8 PB0 R/W P82 R/W bit 2 PA2 R/W bit 1 P81 R/W bit 1 PA1 R/W R/W Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001AH (DDRB) PA7 R/W Address 00001BH bit 15 -- R/W bit 14 -- R/W bit 13 -- R/W bit 12 -- R/W bit 7 . . . . . . . . . . . . bit 0 (DDRA) Note: Only MB90675 series has P81 through P86, P90, PA0 through PA7, and PB0 through PB2, and MB90670 series does not have such pins. 44 MB90670/675 Series 2. Timebase Timer The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK. The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc. (1) Register Configuration * Timebase timer control register (TBTC) bit 7 . . . . . . . . . . . .bit 0 (WDTC) Address 0000A9H bit 15 RESV R/W bit 14 -- -- bit 13 -- -- bit 12 TBIE R/W bit 11 TBOF R/W bit 10 TBR W bit 9 TBC1 R/W bit 8 TBC0 R/W Initial value 1--00100B R/W: Readable and writable W : Read only -- : Unused (2) Block Diagram To PPG timer Timebase timer counter Divided-by-2 of HCLK x 21 x 22 x 23 To watchdog timer ... ... x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF To oscillation stabilization time selector of clock control block Power-on reset Start stop mode CKSCR : MCS = 10*1 Counter clear circuit Interval timer selector Set TBOF Clear TBOF Timebase timer control register (TBTC) Timebase timer interrupt signal #34(22H)*2 -- -- -- TBIE TBOF TBR TBC1 TBC0 OF : Overflow HCLK: Oscillation clock : Switch machine clock from oscillation clock to PLL clock *1 : Interrupt number *2 45 MB90670/675 Series 3. Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when the counter is not cleared for a preset period of time. (1) Register Configuration * Watchdog timer control register (WDTC) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A8H (TBTC) bit 6 bit 5 bit 4 bit 3 SRST R bit 2 WTE W bit 1 WT1 W bit 0 WT0 W PONR STBR WRST ERST R R R R Initial value XXXXX1 1 1 B R : Read only W : Write only X : Indeterminate (2) Block Diagram Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0 2 Watchdog timer CLR and start Overflow Start sleep mode Start hold status Start stop mode Counter clear control circuit Count clock selector CLR 2-bit counter CLR Watchdog reset generation circuit To internal reset generation circuit Clear (Timebase timer counter) Divided-by-2 of HCLK x 21 x 2 2 ... 4 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK: Oscillation clock 46 MB90670/675 Series 4. 8/16-bit PPG Timer The 8/16-bit PPG timer is 2-channel reload timer module for outputting pulse having given frequencies/duty ratios. The two modules performs the following operation by combining functions. * 8-bit PPG output 2-channel independent operation mode This is a mode for operating independent 2-channel 8-bit PPG timer, in which PPG0 and PPG1 pins correspond to outputs from PPG0 and PPG1 respectively. * 16-bit PPG output operation mode In this mode, PPG0 and PPG1 are combined to be operated as a 1-channel 8/16-bit PPG timer operating as a 16-bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same output pulses from PPG0 and PPG1 pins. * 8 + 8-bit PPG output operation mode In this mode, PPG0 is operated as an 8-bit prescaler, in which an underflow output of PPG0 is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1 respectively. The module can also be used as a D/A converter with an external add-on circuit. (1) Register Configuration * PPG0 operating mode control register (PPGC0) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000030H (PPGC1) PEN0 R/W Address 000031H bit 15 PEN1 R/W bit 14 PCS1 R/W bit 13 POE1 R/W bit 12 PIE1 R/W bit 6 -- -- bit 11 PUF1 R/W bit 5 POE0 R/W bit 10 MD1 R/W bit 4 PIE0 R/W bit 9 MD0 R/W bit 3 bit 2 bit 1 bit 0 PUF0 PCM1 PCM0 RESV R/W R/W R/W R/W Initial value 0 - 000001 B * PPG1 operating mode control register (PPGC 1) bit 8 bit 7 . . . . . . . . . . . . bit 0 RESV R/W (PPGC0) Initial value 00000001 B * PPG reload register (PRLL0,PRLH0,PRLL1,PRLH1) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 PRLH0:000035H (PRLH0,PRLH1 ) PRLH1:000037H R/W Address PRLL0:000034H PRLL1:000036H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B R/W R/W R/W R/W R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PRLL0,PRLL1) Initial value XXXXXXXX B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable and writable -- : Unused X : Indeterminate 47 MB90670/675 Series (2) Block Diagram * Block diagram of 8/16-bit PPG timer 0 Data bus for "H" digits Data bus for "L" digits PPG0 reload register PPG0 operating mode control register (PPGC0) PRLH0 PRLL0 PEN0 -- POE0 PIE0 PUF0 PCM1 PCM0 RESV Temporary buffer (PRLBH0) R S 2 Q Interrupt request #29 (1DH)* Mode control signal Reload selector (L/H selector) Count value reload Select signal Clear Pulse selector Underflow PPG1 underflow PPG0 underflow (to PPG1) Down counter (PCNT0) CLK Reverse PPG0 output latch PPG output control circuit Pin P46/PPG0 Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (4/) Peripheral clock (1/) Count clock selector 2 Select signal * : Interrupt number HCLK : Oscillation clock : Machine clock frequency 48 MB90670/675 Series * Block diagram of 8/16-bit PPG timer 1 Data bus for "H" digits Data bus for "L" digits PPG1 operating mode control register (PPGC1) PPG1 reload register Operating mode control signal PRLH1 PRLL1 PEN1 PCS1 POE1 PIE1 PUF1 MD1 2 MD0 RESV Temporary buffer (PRLBH0) R S Q Interrupt request #30 (1EH)* reload selector (L/H selector) Count value reload Underflow Reverse Select signal Clear PPG1 output latch PPG output control circuit MD0 Down counter (PCNT1) PPG1 underflow (to PPG0) CLK Pin P80/PPG1 PPG0 underflow Timebase timer output (512/HCLK) Peripheral clock (1/) Count clock selector Select signal * : Interrupt number HCLK : Oscillation clock : Machine clock frequency 49 MB90670/675 Series 5. 16-bit Reload Timer The 16-bit reload timer has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used. For this timer, an "underflow" is defined as the counter value of "0000H" to "FFFFH". According to this definition, an underflow occurs after [reload register setting value + 1] counts. In operating the counter, the reload mode for repeating counting operation after reloading a counter setting value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent I/O service (EI2OS). The MB90670/675 series has 2 channels of 16-bit reload timers. (1) Register Configuration * Timer control status register upper digits (TMCSR0,TMCSR1 : H) Address TMCSR0:000039H TMCSR1:00003DH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 CSL1 R/W bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 (TMCSR : L) Initial value - - - - 0000 B CSL0 MOD2 MOD1 R/W R/W R/W * Timer control status register lower digits (TMCSR0,TMCSR1 : L) Address TMCSR0:000038H TMCSR1:00003CH bit 15. . . . . . . . . . . . .bit 8 bit 7 (TMCSR : H) bit 6 bit 5 bit 4 RELD R/W bit 3 INTE R/W bit 2 UF R/W bit 1 CNTE R/W bit 0 TRG R/W Initial value 00000000 B MOD1 OUTE OUTL R/W R/W R/W * 16-bit timer register 0, 1 (TMR0,TMR1) Address 00003AH 00003BH 00003EH 00003FH bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R R R R R R R R R R R R R R R R * 16-bit reload register 0, 1 (TMRL0,TMRL1) Address 00003AH 00003BH 00003EH 00003FH bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB W W W W W W W W W W W W W W W W R/W : Readable and writable R : Read only W : Write only -- : Unused X : Indeterminate 50 MB90670/675 Series (2) Block Diagram Internal data bus TMRLR0*1 16-bit timer register (down counter) UF CLK Count clock generation circuit 3 Gate input Valid clock decision circuit CLK Internal clock Pin Input control circuit External clock P24/TIN0*1 Prescaler Clear To UART0, 1*1 -- -- -- -- CSL1CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Interrupt request signal #29 (1DH)*2 <#30 (1EH)> Timer control status register (TMCSR0)*1 *1: The timer has ch.0 and ch.1, and listed in the parenthesis <> are for ch.1. *2: Interrupt number : Machine clock frequency 51 MB90670/675 Series 6. 24-bit Free-run Timer The 24-bit free-run timer is a 24-bit up counter for counting up in synchronization to divided-by-3 or divided-by4 of the machine clock, in which an interrupt factor can be selected from the overflow interrupt and four types of timer intermediate bit interrupt to be operated as an interval timer. The free-run timer can be used to generating reference timing signals for the input capture (ICU) and output compare (OCU). (1) Register Configuration * Free-run timer control register upper digits (TCCR : H) Address 000051H bit 15 -- -- bit 14 -- -- bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 PR0 R/W bit 7 . . . . . . . . . . . . . bit 0 (TCCR : L) Initial value - - 111111 B RESV RESV RESV RESV RESV R/W R/W R/W R/W R/W * Free-run timer control register lower digits (TCCR : L) Address 000050H bit 15. . . . . . . . . . . . .bit 8 bit 7 (TCCR : H) STP W bit 6 CLR W bit 5 IVF R/W bit 4 IVFE R/W bit 3 TIM R/W bit 2 TIME R/W bit 1 TIS1 R/W bit 0 TIS0 R/W Initial value 00000000B 00000000B Initial value 11000000B * Free-run timer upper data register (TCRH) Address 000056H 000057H bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -- R -- R -- R -- R -- R -- R -- R -- T23 T22 T21 T20 T19 T18 T17 T16 R R R R R R R R R * Free-run timer lower data register (TCRL) Address 000054H 000055H bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 T15 T14 T13 T12 T11 T10 R R R R R R T9 R T8 R T7 R T6 R T5 R T4 R T3 R T2 R T1 R T0 R Initial value 00000000B 00000000B R/W : Readable and writable R : Read only W : Write only -- : Unused 52 MB90670/675 Series (2) Block Diagram Internal data bus 24-bit counter (TCR) Output buffer 8 16 T16 to T23 T0 to T15 To output compare (OCU) To input capture (ICU) TCRH Upper 8-bit counter Carry TCRL Lower 16-bit counter Carry Prescaler 4 Count clock selector /3 /4 Select signal Intermediate bit interrupt control circuit Carry detection Pause Overfolw -- -- RESV RESV RESV RESV RESV PR0 STP CLR IVF IVFE TIM TIME TIS1 TIS0 Intermediate bit interrupt request signal #24 (18H)* Overflow interrupt request signal #23 (17H)* Free-run timer control register (TCCR) * : Interrupt number : Machine clock frequency 53 MB90670/675 Series 7. Input Capture (ICU) The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of current counter value of the 24-bit free-run timer to the ICU data register (ICDR) upon an input of a trigger edge to the external pin. There are four sets (four channels) of the input capture external pins and ICU data registers (ICDR), enabling measurements of maximum of four events. * The input capture has four sets of external input pins (ASR0 to ASR3) and ICU registers (ICDR), enabling measurements of maximum of four events. * A trigger edge direction can be selected from rising/falling/both edges. * The input capture can be set to generate an interrupt request at the storage timing of the counter value of the 24-bit free-run timer to the ICU data register (ICDR). * The input compare conforms to the extended intelligent I/O service (EI2OS). * The input capture function is suited for measurements of intervals (frequencies) and pulse-widths. (1) Register Configuration * ICU control register upper digits (ICC : H) Address 000053H bit 15 IRE3 R/W bit 14 IRE2 R/W bit 13 IRE1 R/W bit 12 IRE0 R/W bit 11 IR3 R/W bit 10 IR2 R/W bit 9 IR1 R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 IR0 R/W (ICC : L) Initial value 00000000B * ICU control register lower digits (ICC : L) Address 000052H bit 15. . . . . . . . . . . . bit 8 (ICC : H) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 00000000B EG3B EG3A R/W R/W EG2B EG2A EG1B EG1A R/W R/W R/W R/W EG0B EG0A R/W R/W * ICU upper data register 0 to 3 (ICDR0H to ICDR3H) Address ICDR0H : 000063H ICDR1H : 000067H ICDR2H : 00006BH ICDR3H : 00006FH Address ICDR0H : 000062H ICDR1H : 000066H ICDR2H : 00006AH ICDR3H : 00006EH bit 15 -- R bit 14 -- R bit 13 -- R bit 12 -- R bit 11 -- R bit 10 -- R bit 9 -- R bit 8 -- R Initial value 00000000B bit 7 D23 R bit 6 D22 R bit 5 D21 R bit 4 D20 R bit 3 D19 R bit 2 D18 R bit 1 D17 R bit 0 D16 R Initial value XXXXXXXXB * ICU lower data register 0 to 3 (ICDR0L to ICDR3L) Address ICDR0L : 000061H ICDR1L : 000065H ICDR2L : 000069H ICDR3L : 00006DH Address ICDR0L : 000060H ICDR1L : 000064H ICDR2L : 000068H ICDR3L : 00006CH R/W : Readable and writable R : Read only -- : Unused X : Indeterminate bit 15 D15 R bit 14 D14 R bit 13 D13 R bit 12 D12 R bit 11 D11 R bit 10 D10 R bit 9 D9 R bit 8 D8 R Initial value XXXXXXXXB bit 7 D7 R bit 6 D6 R bit 5 D5 R bit 4 D4 R bit 3 D3 R bit 2 D2 R bit 1 D1 R bit 0 D0 R Initial value XXXXXXXXB 54 MB90670/675 Series (2) Block Diagram Internal data bus Latch signal Output latch Edge detection circuit P61/ASR0 Pin P65/ASR1 Pin P66/ASR2 Pin 2 P67/ASR3 Pin 2 ICU control register (ICC) IRE3 IRE2 IRE1 IRE0 IR3 IR2 IR1 IR0 EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A #25 (19H)* #26 (1AH)* #27 (1BH)* #28 (1CH)* *: Interrupt number ICDR3H ICDR3L 24 2 24 ICDR2H ICDR2L ICDR1H ICDR1L 24-bit free-run timer Data latch signal ICDR0H 2 24 ICDR0L ICU data register (ICDR) 24 Input capature interrupt request signal 55 MB90670/675 Series 8. Output Compare (OCU) The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare data registers, a comparator and a control register. An interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the OCU compare data register setting value and the counter value of the 24-bit free-run timer. The DOT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the DOT bit. (1) Register Configuration * OCU control register 00 upper digits (CCR00 : H) Address 000059H bit 15 -- -- Address 000058H bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 7 RESV R/W bit 11 MD3 R/W bit 6 bit 10 MD2 R/W bit 5 bit 9 MD1 R/W bit 4 RESV R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 MD0 R/W bit 3 CPE3 R/W bit 2 bit 1 bit 0 CPE0 R/W Initial value 11110000B (CCR00 : L) Initial value - - - - 0000 B * OCU control register 00 lower digits (CCR00 : L) bit 15. . . . . . . . . . . . bit 8 (CCR00 : H) RESV RESV R/W R/W CPE2 CPE1 R/W R/W * OCU control register 01 upper digits (CCR01 : H) Address 00005BH bit 15 ICE3 R/W bit 14 ICE2 R/W bit 13 ICE1 R/W bit 12 ICE0 R/W bit 11 IC3 R/W bit 10 IC2 R/W bit 9 IC1 R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 IC0 R/W (CCR01 : L) Initial value 00000000B * OCU control register 01 lower digits (CCR01 : L) Address 00005AH bit 15. . . . . . . . . . . . bit 8 (CCR01 : H) bit 7 -- -- R/W : Readable and writable -- : Unused bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 DOT3 R/W bit 2 bit 1 bit 0 DOT0 R/W Initial value - - - - 0000 B DOT2 DOT1 R/W R/W (Continued) 56 MB90670/675 Series (Continued) * OCU compare upper data register 0 to 7 (CPR00H to CPR07H) Address CPR00H : 000073H CPR01H : 000077H CPR02H : 00007BH CPR03H : 00007FH CPR04H : 000083H CPR05H : 000087H CPR06H : 00008BH CPR07H : 00008FH bit 15 -- R/W bit 14 -- R/W bit 13 -- R/W bit 12 -- R/W bit 11 -- R/W bit 10 -- R/W bit 9 -- R/W bit 8 -- R/W Initial value 00000000B Address CPR00H : 000072H CPR01H : 000076H CPR02H : 00007AH CPR03H : 00007EH CPR04H : 000082H CPR05H : 000086H CPR06H : 00008AH CPR07H : 00008EH bit 7 D23 R/W bit 6 D22 R/W bit 5 D21 R/W bit 4 D20 R/W bit 3 D19 R/W bit 2 D18 R/W bit 1 D17 R/W bit 0 D16 R/W Initial value 00000000B * OCU compare lower data register 0 to 7 (CPR00L to CPR07L) Address CPR00L : 000071H CPR01L : 000075H CPR02L : 000079H CPR03L : 00007DH CPR04L : 000081H CPR05L : 000085H CPR06L : 000089H CPR07L : 00008DH bit 15 D15 R/W bit 14 D14 R/W bit 13 D13 R/W bit 12 D12 R/W bit 11 D11 R/W bit 10 D10 R/W bit 9 D9 R/W bit 8 D8 R/W Initial value 00000000B Address CPR00L : 000070H CPR01L : 000074H CPR02L : 000078H CPR03L : 00007CH CPR04L : 000080H CPR05L : 000084H CPR06L : 000088H CPR07L : 00008CH bit 7 D7 R/W bit 6 D6 R/W bit 5 D5 R/W bit 4 D4 R/W bit 3 D3 R/W bit 2 D2 R/W bit 1 D1 R/W bit 0 D0 R/W Initial value 00000000B R/W : Readable and writable -- : Unused 57 MB90670/675 Series (2) Block Diagram of Output Compare (OCU) * Overall block diagram Free-run timer data 4 23 Output compare unit MATCH0 to MATCH3 T1 to T23 4 16 ICOMP0 to ICOMP3 RB15 to RB0 Output compare unit 00 to 03 (unit 0) DOT0 to DOT3 EXT0 to EXT3 MATCH4 to MATCH7 T1 to T23 Interrupt request (ICOMP0 to ICOMP3) Internal data bus 4 4 OPEN Pin P70/DOT0 to P73/DOT3 4 ICOMP4 to ICOMP7 16 RB15 to RB0 Output compare unit 04 to 07 (unit 1) DOT4 to DOT7 EXT0 to EXT3 Interrupt request (ICOMP4 to ICOMP7) 4 Pin P74/DOT4 to P77/DOT7 58 MB90670/675 Series * Block diagram of unit 0 OCU control register 00 (CCR00) -- -- -- -- MD3 MD2 MD1 MD0 RESV RESV RESV RESV CPE3 CPE2 CPE1 CPE0 4 Compare circuit General-purpose port/ compare pin switching T1 T0 2 Match operation enabled 4 Output control circuit MATCH0 to MATCH3 (to unit 1) 24-bit free-run timer bit 23 to bit 2 Compare control 4 Compare control block Match signal 4 Clock selector 4 P73/DOT3 Pin Data latch Internal data bus CPR00H CPR00L P72/DOT2 Pin CPR01H CPR01L Output latch P71/DOT1 Pin P70/DOT0 CPR02H CPR02L CPR03H OCU compare data register 0 to 3 CPR03L Pin ICE3 ICE2 ICE1 ICE0 IC3 IC2 IC1 IC0 -- -- -- -- DOT3 DOT2 DOT1 DOT0 OCU control register 01 (CCR01) #15 (0FH)* #16 (10H)* #17 (11H)* #18 (12H)* * : Interrupt number Output compare interrupt request signal 59 MB90670/675 Series * Block diagram of unit 1 OCU control register10 (CCR10) -- -- -- -- MD3 MD2 MD1 MD0 SEL3 SEL2 SEL1 SEL0 CPE3 CPE2 CPE1 CPE0 4 4 4 General-purpose port/compare pin switching MATCH0 to MATCH3 4 (from unit 0) Compare circuit 24-bit free-run timer bit 23 to bit 2 Compare control 4 Match signal 4 Data latch P77/DOT7 Pin CPR04H CPR04L P76/DOT6 Pin CPR05H CPR05L Output latch P75/DOT5 Pin P74/DOT4 CPR07H OCU compare data register 4 to 7 CPR07L Pin T1 T0 Match operation enabled 2 Clock selector Output control circuit Factor selector 4 Compare control block Internal data bus 4 CPR06H CPR06L ICE3 ICE2 ICE1 ICE0 IC3 IC2 IC1 IC0 -- -- -- -- DOT3 DOT2 DOT1 DOT0 OCU control register 11 (CCR11) #19 (13H)* #20 (14H)* #21 (15H)* #22 (16H)* Output compare interrupt request signal * : Interrupt number 60 MB90670/675 Series 9. I2C Interface (Included Only in MB90675 Series) The I2C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I2C bus and has the following features. * * * * * * * Master/slave transmission/reception Arbitration function Clock synchronization function Slave address/general call address detection function Transmission direction detection function Repeated generation function start condition and detection function Bus error detection function (1) Register Configuration * I2C bus status register (IBSR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000040H (IBCR) BB R bit 6 RSC R bit 5 AL R bit 4 LRB R bit 3 TRX R bit 2 AAS R bit 1 GCA R bit 0 FBT R Initial value 00000000B * I2C bus control register (IBCR) Address 000041H bit 15 BER R/W bit 14 BEIE R/W bit 13 SCC R/W bit 12 MSS R/W bit 11 ACK R/W bit 10 GCAA R/W bit 9 INTE R/W bit 8 INT R/W bit 7 . . . . . . . . . . . . bit 0 (IBSR) Initial value 00000000B * I2C bus clock control register (ICCR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000042H (IADR) -- -- bit 6 -- -- bit 5 EN R/W bit 4 CS4 R/W bit 3 CS3 R/W bit 2 CS2 R/W bit 1 CS1 R/W bit 0 CS0 R/W Initial value --0XXXXXB * I2C address register (IADR) Address 000043H (IADR) bit 15 -- -- bit 14 A6 R/W bit 13 A5 R/W bit 12 A4 R/W bit 11 A3 R/W bit 10 A2 R/W bit 9 A1 R/W bit 8 A0 R/W bit 7 . . . . . . . . . . . . bit 0 (ICCR) Initial value -XXXXXXXB Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000044H (Reserved area) D7 (IDAR) R/W R/W: Readable and writable R : Read only -- : Uunsed X : Indeterminate bit 6 D6 R/W bit 5 D5 R/W bit 4 D4 R/W bit 3 D3 R/W bit 2 D2 R/W bit 1 D1 R/W bit 0 D0 R/W Initial value XXXXXXXXB 61 MB90670/675 Series (2) Block Diagram Internal data bus I2C bus control register (IBCR) I2C bus status register (IBSR) BB RSC AL LRB TRX AAS GCA FBT Transmission enable flag Transmit/receive Detection of first byte Interrupt request signal #38 (26H)* SDA line CCL line I2C enable Pin IDAR register Arbitration lost detection circuit P91/SCL Pin P90/SDA Repeat start General call BER BEIE SCC MSS ACK GCAA INTE INT GC-ACK enable Interrupt enable ACK enable Master Error Start Bus busy Last bit Number of interrupt request generated Start stop condition generation circuit Start stop condition detection circuit Slave address comparison circuit IADR register Clock control block Sync Clock divider 1 4 (1/5 to 1/8) Count clock selector 1 Clock divider 2 8 Count clock selector 2 Shift clock generation circuit I2C enable -- -- EN CS4 CS3 CS2 CS1 CS0 I2C bus clock control register (ICCR) : Machine clock frequency * : Interrupt number 62 Slave MB90670/675 Series 10. UART0 UART0 is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). In addition to the normal duplex communication function (normal mode), UART0 has a master/slave type communication function (multi-processor mode). * Data buffer: Full-duplex double buffer * Transfer mode: Clock synchronized (with start and stop bit) Clock asynchronized (start-stop synchronization system) * Baud rate: With dedicated baud rate generator, selectable from 12 types External clock input possible Internal clock (a clock supplied from 16-bit reload timer can be used.) * Data length: 7 bits to 9 bits selective (with a parity bit) 6 bits to 8 bits selective (without a parity bit) * Signal format: NRZ (Non Return to Zero) system * Reception error detection: Framing error Overrun error Parity error (not available in multi-processor mode) * Interrupt request: Receive interrupt (reception complete, receive error detection) Receive interrupt (transmission complete) Transmit/receive conforms to extended intelligent I/O service (EI2OS) * Master/slave type communication function (multi-processor mode): 1 (master) to n (slave) communication possible (1) Register Configuration * Status register 0 (USR0) Address 000021H bit 15 bit 14 bit 13 PE R/W bit 12 TDRE R/W bit 11 RIE R/W bit 10 TIE R/W bit 9 RBF R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 TBF R/W (UMC0) Initial value 00100000B RDRF ORFE R/W R/W * Mode control register 0 (UMC0) Address 000020H bit 15. . . . . . . . . . . . bit 8 bit 7 (USR0) PEN R/W bit 6 SBL R/W bit 11 RC0 R/W bit 5 MC1 R/W bit 10 BCH0 R/W bit 4 MC0 R/W bit 9 P R/W bit 3 SMDE R/W bit 2 RFC R/W bit 1 SCKE R/W bit 0 SOE R/W Initial value 00000000B Initial value 00000100B * Rate and data register 0 (URD0) Address 000023H bit 15 BCH R/W bit 14 RC3 R/W bit 13 RC2 R/W bit 12 RC1 R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 D8 R/W (UIDR0/UODR0) * Input data register 0 (UIDR0) Address 000022H . bit 15. . . . bit 9 bit 8 (URD0) D8 R bit 7 D7 R bit 7 D7 W bit 6 D6 R bit 6 D6 W bit 5 D5 R bit 5 D5 W bit 4 D4 R bit 4 D4 W bit 3 D3 R bit 3 D3 W bit 2 D2 R bit 2 D2 W bit 1 D1 R bit 1 D1 W bit 0 D0 R bit 0 D0 W Initial value XXXXXXXXB Initial value XXXXXXXXB * Output data register 0 (UODR) Address 000022H . bit 15. . . . bit 9 bit 8 (URD0) D8 W R/W : Readable and writable R : Read only W : Write only X : Indeterminate 63 MB90670/675 Series (2) Block Diagram Control bus Receive interrupt signal #39 (27H)* Transmit interrupt signal #36 (24H)* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin P42/SOT0 Dedicated baud rate generator 16-bit reload timer 0 Pin P42/SCK0 Clock selector Transmit clock Receive clock Receive control circuit Start bit detection circuit Receive bit counter Receive parity counter Pin P40/SIN0 Shift register for reception Reception complete Shift register for transmission UIDR0 Receive condition decision circuit UODR0 Start transmission To EI2OS reception error generation signal (to CPU) Internal data bus UMC0 register PEN SBL MC1 MC0 SMDE RFC SCKE SOE USR0 register RDRF ORFE PE TDRE RIE TIE RBF TBF URD0 register BCH RC3 RC2 RC1 RC0 BCH0 P D8 * : Interrupt number 64 MB90670/675 Series 11. UART1 (SCI) UART1 (SCI) is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). In addition to the normal duplex communication function (normal mode), UART1 has a master-slave type communication function (multiprocessor mode). * Data buffer: Full-duplex double buffer * Transfer mode: Clock synchronized (no start or stop bit) Clock asynchronized (start-stop synchronization system) * Baud rate: With dedicated baud rate generator, selectable from 8 types External clock input possible Internal clock (a internal clock supplied from 16-bit reload timer can be used.) * Data length: 7 bits (for asynchronous normal mode only) 8 bits * Signal format: NRZ (Non Return to Zero) system * Reception error detection: Framing error Overrun error Parity error (not available in multi-processor mode) * Interrupt request: Receive interrupt (receptioncomplete, receive error detection) Receive interrupt (transmission complete) Transmit/receive conforms to extended intelligent I/O service (EI2OS) * Master/slave type communication function (multi-processor mode):1 (master) to n (slave) communication possible (supported only for master station) (1) Register Configuration * Control register 1 (SCR1) Address 000025H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 PEN R/W P R/W SBL R/W CL R/W A/D R/W R/W R/W bit 4 CS1 R/W bit 8 bit 7 ............ bit 0 (SMR1) R/W bit 3 bit 2 bit 1 R/W bit 0 R/W Initial value 00001-00B Initial value 00000000B Initial value 00000100B REC RXE TXE * Mode register 1 (SMR1) Address bit 15 ............ bit 8 bit 7 000024H (SCR1) R/W bit 6 bit 5 R/W R/W MD1 MD0 CS2 CS0 BCH SCKE SOE R/W R/W bit 8 bit 7 ............ bit 0 TIE R/W bit 3 D3 R bit 3 D3 W bit 2 D2 R bit 2 D2 W bit 1 D1 R bit 1 D1 W bit 0 D0 R bit 0 D0 W Initial value XXXXXXXXB Initial value XXXXXXXXB (SIDR1/SODR1) * Status register 1 (SSR1) Address 000027H PE R bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 ORE FRE RDRF TDRE R R R R -- -- RIE R/W bit 4 D4 R bit 4 D4 W * Input data register 1 (SIDR1) Address bit 15 ............ bit 8 bit 7 000026H (SSR1) D7 R bit 6 bit 5 D6 R D5 R * Output data register 1 (SODR1) 000026H (SSR1) Address bit 15 ............ bit 8 bit 7 D7 W R/W : R: W: --: X: Readable and writable Read only Write only Unused Indeterminate bit 6 bit 5 D6 W D5 W 65 MB90670/675 Series (2) Block Diagram Control bus Receive interrupt signal #37 (25H)* Transmit interrupt signal #35 (23H)* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin P44/SOT1 Dedicated baud rate generator 16-bit reload timer 1 Pin P45/SCK1 Clock selector Transmit clock Receive clock Receive control circuit Start bit detection circuit Receive bit counter Receive parity counter Pin P43/SIN1 Shift register for reception Reception complete Shift register for transmission SIDR1 Receive condition decision circuit SODR1 Start transmission To EI2OS reception error generation signal (to CPU) Internal data bus SMR1 register MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE SCR1 register PEN P SBL CL A/D REC RXE TXE SSR1 register PE ORE FRE RDRF TDRE RIE TIE *: Interrupt number 66 MB90670/675 Series 12. DTP/External Interrupt Circuit The DTP (Data Transfer Peripheral)/external interrupt circuit is located between peripheral equipment connected externally and the F2MC-16L CPU and transmits interrupt requests or data transfer requests generated by peripheral equipment to the CPU, generates external interrupt request and starts the extended intelligent I/O service (EI2OS). (1) Register Configuration * DTP/interrupt factor register (EIRR) Address bit 15 000029H -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 ER3 R/W bit 10 ER2 R/W bit 9 ER1 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 ER0 R/W (ENIR) Initial value - - - - 0000 B * DTP/interrupt enable register (ENIR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000028H (EIRR) -- -- bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 EN3 R/W bit 2 EN2 R/W bit 1 EN1 R/W bit 0 EN0 R/W Initial value - - - - 0000 B * Request level setting register (ELVR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00002AH (Vacancy) LB3 R/W R/W : Readable and writable -- : Unused bit 6 LA3 R/W bit 5 LB2 R/W bit 4 LA2 R/W bit 3 LB1 R/W bit 2 LA1 R/W bit 1 LB0 R/W bit 0 LA0 R/W Initial value 00000000B 67 MB90670/675 Series (2) Block Diagram Request level setting register (ELVR) LB3 LA3 2 Pin 2 P60/INT0 Level edge selector 3 Level edge selector 1 LB2 LA2 2 LB1 LA1 LB0 2 LA0 Pin P61/INT1 Level edge selector 2 Level edge selector 0 Internal data bus Pin P62/INT2 Pin P63/INT3 DTP/interrupt factor register (EIRR) -- -- -- -- ER3 ER2 DTP/external interrupt input detection circuit ER1 ER0 Interrupt request signal #14 (0EH)* #13 (0DH)* #14 (0CH)* DTP/interrupt enable register (ENIR) -- -- -- -- EN3 EN2 EN1 EN0 #11 (0BH)* *: Interrupt signal 68 MB90670/675 Series 13. Wake-up Interrupt Wake-up interrupts transmits interrupt request ("L" level) generated by peripheral device located between external peripheral devices and the F2MC-16L CPU to the CPU and invokes interrupt processing. The interrupt does not conform to the extended intelligent I/O service (EI2OS). (1) Register Configuration * Wake-up interrupt flag register (EIFR) Address 00000FH bit 15 -- -- Address 00001FH bit 15 EN7 R/W bit 14 -- -- bit 14 EN6 R/W bit 13 -- -- bit 13 EN5 R/W bit 12 -- -- bit 12 EN4 R/W bit 11 -- -- bit 11 EN3 R/W bit 10 -- -- bit 10 EN2 R/W bit 9 -- -- bit 9 EN1 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 WIF R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 EN0 R/W (Vacancy) (Vacancy) Initial value - - - - - - -0B * Wake-up interrupt enable register (EICR) Initial value 00000000B R/W : Readable and writable -- : Unused (2) Block Diagram Internal data bus Wake-up interrupt enable register (EICR) EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 Wake-up interrupt flag register (EIFR) -- -- -- -- -- -- -- WIF Interrupt request detection circuit P10/AD08/WI0 P11/AD09/WI1 P12/AD10/WI2 P13/AD11/WI3 P14/AD12/WI4 P15/AD13/WI5 P16/AD14/WI6 P17/AD15/WI7 Pin Pin Pin Pin Pin Pin Pin Pin Wake-up interrupt request #33 (21H)* *: Interrupt number 69 MB90670/675 Series 14. Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks for development on a realtime operating system (REALOS software). The module can be used to generate hardware interrupt requests to the CPU with software and cancel the interrupt requests. This module does not conform to the extended intelligent I/O service (EI2OS). (1) Register Configuration * Delayed interrupt factor generation/cancellation register (DIRR) Address 00009FH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 R0 R/W (Reserved area) Initial value - - - - - - -0B R/W : Readable and writable -- : Unused (2) Block Diagram Internal data bus -- -- -- -- -- -- -- R0 S factor R latch Delayed interrupt factor generation/ cancellation register (DIRR) *: Interrupt signal Interrupt request signal #42 (2AH)* 70 MB90670/675 Series 15. 8/10-bit A/D Converter The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input voltage) to digital values (A/D conversion) and has the following features. * * * * * Minimum conversion time: 6.13 s (at machine clock of 16 MHz, including sampling time) Minimum sampling time: 3.75 s (at machine clock of 16 MHz) Conversion method: RC successive approximation method with a sample and hold circuit. Resolution: 10-bit or 8-bit selective Analog input pins: Selectable from eight channels by software One-shot conversion mode:Stops conversion after completing a conversion for a stopped channel (one channel only) or for successive channels (maximum of eight channels can be specified) Continuous conversion mode:Continues conversions for a specified channel (one channel only) or for successive channels (maximum of eight channels can be specified) Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next activation. * Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the end of A/D conversion. * When interrupts are enabled, there is no loss of data even in continuous operations because the conversion data protection function is in effect. * Starting factors for conversion: Selected from software activation, 16-bit reload timer 1 output (rising edge), and external trigger (falling edge). (1) Register Configuration * A/D control status register upper digits (ADCS: H) Address 00002DH bit 15 BUSY R/W bit 14 INT R/W bit 13 INTE R/W bit 12 PAUS R/W bit 11 STS1 R/W bit 10 STS0 R/W bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (ADCS: L) Initial value 00000000B STRT RESV W R/W * A/D control status register lower digits (ADCS: L) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00002CH (ADCS: H) MD1 R/W bit 6 MD0 R/W bit 5 ANS2 R/W bit 4 ANS1 R/W bit 3 ANS0 R/W bit 2 ANE2 R/W bit 1 ANE1 R/W bit 0 ANE0 R/W Initial value 00000000B * A/D data register (ADCR) Address 00002EH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 S10 -- -- -- -- -- -- -- -- -- D9 R D8 R D7 R D6 R D5 R D4 R D3 R D2 R D1 R D0 R Initial value XXXXXXXXB 0000000XB R/W -- R/W : R: W: --: X: Readable and writable Read only Write only Unused Indeterminate 71 MB90670/675 Series (2) Block Diagram A/D control status register (ADCS) Interrupt request signal #31 (1FH)* BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 6 2 P47/ATG TO Clock selector Decoder Comparator P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 Sample hold circuit Analog channel selector AVR AVCC AVSS D/A converter Control circuit A/D data register S10 (ADCR) -- -- -- -- -- D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 : Machine clock frequency TO : 16-bit reload timer channel 1 output * : Interrupt number 72 Internal data bus MB90670/675 Series 16. Low-power Consumption (Standby) Mode The F2MC-16L has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation clock (HCLK). Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the oscillation clock (HCLK). The PLL multiplication circuits stops in the mainclock mode. * CPU intermittent operation mode The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU intermittently while external bus and peripheral functions are operated at a high-speed. * Hardware stand-by mode The hardware standby mode is a mode for reducing power consumption by stopping clock supply (sleep mode) to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). Of these modes, modes other than the PLL clock mode are power consumption modes. (1) Register Configuration * Clock select register (CKSCR) Address 0000A1H bit 15 RESV R/W bit 14 MCM R bit 13 WS1 R/W bit 12 WS0 R/W bit 11 RESV R/W bit 6 SLP W bit 10 MCS R/W bit 5 SPL R/W bit 9 CS1 W bit 4 RST W bit 8 bit 7 . . . . . . . . . . . . bit 0 CS0 R/W bit 3 RESV R/W bit 2 CG1 R/W bit 1 CG0 R/W bit 0 RESV R/W (LPMCR) Initial value 11111100 B * Low-power consumption mode control register (LPMCR) Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A0H (CKSCR) STP W R/W : Readable and writable R : Read only W : Write only Initial value 00011000 B 73 MB90670/675 Series (2) Block Diagram Low-power consumption mode control register (LPMCR) STP SLP SPL RST RESV CG1 CG0 RESV Pin high-impedance control circuit Internal reset generation circuit CPU intermittent operation selector Pin Hi-z control RST Pin Internal reset Select intermittent cycle CPU clock control circuit CPU clock Cancellation of reset 2 Cancellation of interrupt RST Standby control circuit Stop and sleep signal HST Pin Machine clock Stop signal Peripheral clock control circuit Peripheral clock Clock generation block Clock selector Cancellation of oscillation stabilization time 2 2 Oscillation stabilization time selector PLL multiplication circuit RESV MCM WS1 WS0 RESV MCS CS1 CS0 System clock generation circuit X0 Pin Clock selection register (CKSCR) Divided -by-2 Main clock Divided -by-2048 Divided -by-4 Divided -by-4 Divided -by-8 Timebase timer X1 Pin 74 MB90670/675 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage AVCC AVRH, AVRL Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total average output current Power consumption Operating temperature Storage temperature *1: *2: *3: *4: *5: VI VO IOL IOLAV IOLAV IOH IOHAV IOHAV PD TA Tstg Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VCC + 0.3 15 4 100 50 -15 -4 -100 -50 400 +85 +150 Unit V V V V V mA mA mA mA mA mA mA mA mW C C *5 *5 *3 *4 *1 *1 *2 *2 *3 *4 Remarks "L" level total maximum output current IOL "H" level total maximum output current IOH AVCC, AVRH, and AVRL shall never exceed VCC. AVRL shall never exceed AVRH. VI and VO shall never exceed VCC + 0.3 V. The maximum output current is a peak value for a corresponding pin. Average output current is an average current value observed for a 100 ms period for a corresponding pin. Total average current is an average current value observed for a 100 ms period for all corresponding pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 75 MB90670/675 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage Operating temperature VCC TA Value Min. 2.7 2.0 -40 Max. 5.5 5.5 +85 Unit V V C Remarks Normal operation Retains status at the time of operation stop WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 76 MB90670/675 Series 3. DC Characteristics (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. 0.7 VCC -- VCC + 0.3 V MB90670 series Parameter Symbol VIH Pin name Pins other than VIHS and VIHM Hysteresis input pins P24 to P27, P40 to P47, P60 to P67, P70 to P77, P80, HST, RST VIHS "H" level input voltage VIHS 0.8 VCC -- VCC + 0.3 V Hysteresis input pins P24 to P27, P40 to P47, P60 to P67, P70 to P77, P80 to P86, HST, RST, P90, P91, PA0 to PA7, PB0 to PB2 0.8 VCC -- VCC + 0.3 V MB90675 series VIHM VIL MD pin input Pins other than VILS and VILM Hysteresis input pins P24 to P27, P40 to P47, P60 to P67, P70 to P77, P80, HST, RST -- VCC - 0.3 VSS - 0.3 -- -- VCC + 0.3 0.3 VCC V V MB90670 series VILS "L" level input voltage VILS VSS - 0.3 -- 0.2 VCC V Hysteresis input pins P24 to P27, P40 to P47, P60 to P67, P70 to P77, P80 to P86, HST, RST, P90, P91, PA0 to PA7, PB0 to PB2 VSS - 0.3 -- 0.2 VCC V MB90675 series VILM "H" level output voltage "L" level output voltage VOH VOH VOL VOL MD pin input Other than P50 to P57 Other than P50 to P57 All output pins All output pins P50 to P57, P90, P91*1 Other than P50 to P57, P90 and P91 -- -- VCC = 4.5 V IOH = -4.0 mA VCC = 2.7 V IOH = -1.6 mA VCC = 4.5 V IOL = 4.0 mA VCC = 2.7 V IOL = 2.0 mA -- VSS - 0.3 VCC - 0.5 VCC - 0.3 -- -- -- -- -- -- -- VSS + 0.3 -- -- 0.4 0.4 V V V V V Open-drain output Ileak leakage current Input leakage current Pull-up resistance IIL R R -- 0.1 10 A VCC = 5.5 V VSS < VI < VCC VCC = 5.0 V VCC = 3.0 V -10 25 40 -- 45 95 10 100 200 A k k (Continued) 77 MB90670/675 Series (Continued) Parameter Symbol Pull-down resistance R R ICC Pin name -- -- -- (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Typ. Max. VCC = 5.0 V VCC = 3.0 V Internal operation at 16 MHz VCC at 5.0 V Internal operation at 16 MHz VCC at 5.0 V Internal operation at 8 MHz VCC at 3.0 V Internal operation at 8 MHz VCC at 3.0 V 25 40 -- 50 100 50 200 400 70 k k mA Normal operation*2 ICCS -- -- 10 30 mA In sleep mode*2 Power supply current ICC -- -- 12 20 mA Normal operation*2 ICCS -- -- 2.5 10 mA In sleep mode*2 In stop mode and hardware standby mode*2 ICCH -- TA = +25C -- 0.1 10 A Input CIN capacitance Other than AVCC, AVSS, VCC, VSS -- -- 10 -- pF *1: Only MB90675 series has P90 and P91 pins. *2: The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. 78 MB90670/675 Series 4. AC Characteristics (1) Reset Input Timing, Hardware Standby Input Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRSTL tHSTL RST HST -- 16 tCP* 16 tCP* -- -- ns ns Parameter Reset input time Hardware standby input time * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC * Measurement conditions for AC ratings Pin CL CL is a load capacitance connected to a pin under test. CLK, ALE: CL = 30 pF Address data bus (AD15 to AD00), RD, WR: CL = 80 pF 79 MB90670/675 Series (2) Specification for Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Max. -- 30 ms * Due to repeated 1 -- ms operations Parameter Power supply rising time Power supply cut-off time Symbol Pin name Condition tR tOFF VCC VCC -- * : VCC must be kept lower than 0.2 V before power-on. Notes: * The above ratings are values for causing a power-on reset. * When HST is set to "L" level, apply power according to this table to cause a power-on reset irrespective of whether or not a power-on reset is required. * For built-in resources in the device, re-apply power to the resources to cause a power-on reset. * There are internal registers which can be initialized only by a power-on reset. Apply power according to this rating to ensure initialization of the registers. tR VCC 2.7 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. 0.2 V Main power supply voltage VCC Sub power supply voltage VSS RAM data retained It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. 80 MB90670/675 Series (3) Clock Timing * Operation at 5.0 V 10% Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Typ. Max. FC X0, X1 3 -- 32 MHz X0, X1 31.25 -- 333 ns tC Recommended PWH, X0 10 -- -- ns duty ratio of PWL 30% to 70% tCR, X0 -- -- 5 ns tCF -- -- -- P37/CLK 1.5 62.5 -- -- -- -- 16 666 3 MHz ns % * Internal operating clock fCP frequency Internal operating clock cycle tCP time Frequency fluctuation rate f locked * : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + + f = | | x 100 (%) fO Center frequency fO - - The PLL frequency deviation changes periodically from the preset frequency "(about CLK x (1CYC to 50 CYC)", thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals). 81 MB90670/675 Series * Operation at VCC = 2.7 V (minimum value) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol Pin name Condition FC tC PWH, PWL tCR, tCF X0, X1 X0, X1 X0 X0 -- -- P37/CLK (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Typ. Max. 3 -- 16 MHz 62.5 -- 333 ns Recommended 20 -- -- ns duty ratio of 30% to 70% -- 1.5 125 -- -- -- -- -- 5 8 666 3 ns MHz ns % * -- Internal operating clock fCP frequency Internal operating clock cycle tCP time Frequency fluctuation rate f locked * : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + + f = | | x 100 (%) fO Center frequency fO - - The PLL frequency deviation changes periodically from the preset frequency "(about CLK x (1CYC to 50 CYC)", thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals). 82 MB90670/675 Series * Clock timing tC 0.8 VCC 0.8 VCC 0.2 VCC PWH tCF PWL tCR 0.8 VCC 0.2 VCC * PLL operation guarantee range (V) Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC 5.5 4.5 3.3 2.7 Normal operation range PLL operation guarantee range 1.5 3 8 Internal clock fCP 16 (MHz) Relationship between clock frequency, internal operating clock frequency, and power supply voltage (MHz) Multiplied-by-4 Multiplied-by-3 Multipliedby-2 Multiplied-by-1 Not multiplied Internal clock fCP 34 8 16 Oscillation clock FC 24 32 (MHz) Note: The operation guarantee range on the lower voltage is 2.7 V for the evaluation chips. The AC ratings are measured for the following measurement reference voltages. * Input signal waveform Hystheresis input pin 0.8 VCC 0.2 VCC Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC * Output signal waveform Output pin 2.4 V 0.8 V 83 MB90670/675 Series (4) Recommended Resonator Manufacturers * Sample application of piezoelectric resonator (FAR family) X0 R X1 FAR*1 C1*2 C2*2 *1: Fujitsu Acoustic Resonator FAR part number (built-in capacitor type) FAR-C4 C-2000FAR-C4 FAR-C4 FAR-C4 FAR-C4 FAR-C4 FAR-C4 A-4000B-4000B-4000B-8000B-12000B-1600020 01 02 00 02 02 02 Frequency (MHz) 2.00 4.00 4.00 4.00 8.00 12.00 16.00 20.00 24.00 Dumping resistor 510 -- -- -- -- -- -- -- -- Initial deviation of FAR frequency (TA = +25C) 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% Temperature characteristics of FAR frequency (TA = -20C to +60C) 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% Loading capacitors*2 Built-in Built-in Built-in Built-in Built-in Built-in Built-in Built-in Built-in FAR-C4 B-20000-L14B FAR-C4 B-24000-L14A Inquiry: FUJITSU LIMITED 84 MB90670/675 Series * Sample application of ceramic resonator X0 R * X1 C1 C2 * Mask ROM product Resonator manufacturer Resonator KBR-2.0MS PBRC-2.00A KBR-4.0MSA KBR-4.0MKS PBRC4.00A PBRC4.00B KBR-6.0MSA KBR-6.0MKS PBRC6.00A PBRC6.00B KBR-8.0M PBRC8.00A PBRC8.00B KBR-10.0M PBRC10.00B KBR-12.0M PBRC-12.00B CSA2.00MG040 CST2.00MG040 CSA4.00MG040 CST4.00MGW040 CSA6.00MG CST6.00MGW CSA8.00MTZ CST8.00MTW Frequency (MHz) 2.00 2.00 4.00 4.00 4.00 4.00 6.00 6.00 6.00 6.00 8.00 8.00 8.00 10.00 10.00 12.00 12.00 2.00 2.00 4.00 4.00 6.00 6.00 8.00 8.00 C1 (pF) 150 150 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 33 Built-in 33 Built-in 33 Built-in 100 Built-in 100 Built-in 30 Built-in 30 Built-in C2 (pF) 150 150 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 33 Built-in 33 Built-in 33 Built-in 100 Built-in 100 Built-in 30 Built-in 30 Built-in R Not required Not required 680 680 680 680 Not required Not required Not required Not required 560 Not required Not required 330 680 330 680 Not required Not required Not required Not required Not required Not required Not required Not required Kyocera Corporation Murata Mfg. Co., Ltd. (Continued) 85 MB90670/675 Series (Continued) Resonator manufacturer Resonator Frequency (MHz) 10.00 10.00 12.00 12.00 16.00 16.00 20.00 24.00 24.00 32.00 32.00 4.00 C1 (pF) 30 Built-in 30 Built-in 15 Built-in 10 5 Built-in 5 Built-in Built-in C2 (pF) 30 Built-in 30 Built-in 15 Built-in 10 5 Built-in 5 Built-in Built-in R Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required CSA10.0MTZ CST10.0MTW CSA12.0MTZ CST12.0MTW CSA16.00MXZ040 Murata CST16.00MXW0C3 Mfg. Co., Ltd. CSA20.00MXZ040 CSA24.00MXZ040 CST24.00MXW0H1 CSA32.00MXZ040 CST32.00MXW040 TDK Corporation FCR4.0MC5 * One-time product Resonator manufacturer Resonator CSTCS4.00MG0C5 CST8.00MTW Murata CSACS8.00MT Mfg. Co., Ltd. CSA10.0MTZ CST10.0MTW TDK Corporation FCR4.0MC5 Frequency (MHz) 4.0 8.00 8.00 10.00 10.00 4.00 C1 (pF) Built-in Built-in 30 30 Built-in Built-in C2 (pF) Built-in Built-in 30 30 Built-in Built-in R Not required Not required Not required Not required Not required Not required Inquiry: Kyocera Corporation * AVX Corporation North American Sales Headquarters: TEL 1-803-448-9411 * AVX Limited European Sales Headquarters: TEL 44-1252-770000 * AVX/Kyocera H.K. Ltd. Asian Sales Headquarters: TEL 852-363-3303 Murata Mfg. Co., Ltd. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233 TDK Corporation * TDK Corporation of America Chicago Regional Office: TEL 1-708-803-6100 * TDK Electronics Europe GmbH Components Division: TEL 49-2102-9450 * TDK Singapore (PTE) Ltd.: TEL 65-273-5022 * TDK Hongkong Co., Ltd.: TEL 852-736-2238 * Korea Branch, TDK Corporation: TEL 82-2-554-6633 86 MB90670/675 Series (5) Clock Output Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tCYC CLK 1 tCP* -- ns -- CLK 1 tCP*/2 - 20 1 tCP*/2 + 20 ns tCHCL Parameter Cycle time CLK CLK * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timing". tCYC tCHCL 2.4 V 0.8 V 2.4 V CLK 87 MB90670/675 Series (6) Bus Read Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Pin name Condition Min. Max. ALE ALE VCC = 5.0 V 10% 1 tCP*/2 - 20 VCC = 3.0 V 10% 1 tCP*/2 - 35 -- -- -- -- -- -- ns ns ns ns ns ns Parameter ALE pulse width Effective address ALE time ALE address effective time Symbol tLHLL tLHLL tAVLL tAVLL tLLAX AD15 to AD00 VCC = 5.0 V 10% 1 tCP*/2 - 25 AD15 to AD00 VCC = 3.0 V 10% 1 tCP*/2 - 40 AD15 to AD00 -- AD15 to AD00 AD15 to AD00 VCC = 5.0 V 10% AD15 to AD00 VCC = 3.0 V 10% RD -- AD15 to AD00 VCC = 5.0 V 10% AD15 to AD00 VCC = 3.0 V 10% AD15 to AD00 RD, ALE RD, A19 to A16 CLK, A19 to A16 RD, CLK -- 1 tCP* - 15 -- -- 3 tCP*/2 - 20 -- -- 0 1 tCP*/2 - 15 1 tCP*/2 - 10 1 tCP*/2 - 20 1 tCP*/2 - 20 1 tCP*/2 - 15 Effective address RD tAVRL time Effective address read data time RD pulse width RD read data time RD data hold time RD ALE time RD address disappear time Effective address CLK time RD CLK time tAVDV tAVDV tRLRH tRLDV tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH 5 tCP*/2 - 60 ns 5 tCP*/2 - 80 ns -- ns 3 tCP*/2 - 60 ns 3 tCP*/2 - 80 ns -- -- -- -- -- ns ns ns ns ns * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timing". 88 MB90670/675 Series tAVCH 2.4 V CLK tRLCH 2.4 V tRHLH ALE RD 0.8 V tAVRL AD19 to AD16 2.4 V 0.8 V tAVDV AD15 to AD00 2.4 V 0.8 V Address 2.4 V 0.8 V 0.7 VCC 0.3 VCC Read data tRLDV 2.4 V tRHAX 2.4 V 0.8 V tRHDX 0.7 VCC 0.3 VCC 2.4 V tLHLL tAVLL 2.4 V 0.8 V tLLAX tRLRH 2.4 V 89 MB90670/675 Series (7) Bus Write Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Pin name Condition Min. Max. A19 to A00 WR AD15 to AD00 AD15 to AD00 VCC = 5.0 V 10% AD15 to AD00 VCC = 3.0 V 10% A19 to A00 WRL, ALE WRH, CLK -- -- 1 tCP - 15 3 tCP*/2 - 20 3 tCP*/2 - 20 20 30 1 tCP*/2 - 10 1 tCP*/2 - 15 1 tCP*/2 - 20 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns Parameter Symbol Effective address WR tAVWL time WR pulse width tWLWH tWHDX tWHDX tWHAX tWHLH tWLCH Write data WR time tDVWH WR data hold time WR address disappear time WR ALE time WR CLK time * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timing". tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL WRL, WRH 2.4 V 0.8 V tWHAX 2.4 V 0.8 V tDVWH 2.4 V AD15 to AD00 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V tWHDX 2.4 V Write data 0.8 V tWLWH A19 to A16 Address 90 MB90670/675 Series (8) Ready Input Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tRYHS RDY VCC = 5.0 V 10% 45 -- ns RDY VCC = 3.0 V 10% 70 -- ns tRYHS tRYHH RDY -- 0 -- ns Parameter RDY setup time RDY hold time Note: Use the auto-ready function when the setup time for the rising of the RDY signal is not sufficient. 2.4 V CLK ALE 2.4 V RD/WR tRYHS RDY (WAIT inserted) 0.2 VCC tRYHS 0.2 VCC RDY (WAIT inserted) 0.8 VCC 0.8 VCC tRYHH (9) Hold Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. HAK HAK -- 30 1 tCP* 1 tCP* 2 tCP* ns ns Parameter Symbol Pins in floating status tXHAL HAK time HAK pin valid time tHAHV * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timing". Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. HAK 0.8 V tXHAL Pins 2.4 V 0.8 V tHAHV 2.4 V 0.8 V 2.4 V High impedance 91 MB90670/675 Series (10) UART0 Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Parameter Min. Max. Serial clock cycle time tSCYC -- -- 8 tCP* -- ns tSLOV -- VCC = 5.0 V 10% - 80 80 ns Internal shift SCK SOT delay time tSLOV -- VCC = 3.0 V 10% - 120 120 ns clock mode tIVSH -- VCC = 5.0 V 10% 100 -- ns CL = 80 pF Valid SIN SCK -- VCC = 3.0 V 10% 200 -- ns + 1 TTL for an tIVSH output pin SCK valid SIN hold tSHIX -- 1 tCP* -- ns time Serial clock "H" pulse tSHSL -- -- 4 tCP* -- ns width Serial clock "L" pulse tSLSH -- 4 tCP* -- ns width External shift tSLOV -- VCC = 5.0 V 10% -- 150 ns clock mode SCK SOT delay time tSLOV -- VCC = 3.0 V 10% -- 200 ns CL = 80 pF + 1 TTL for an -- VCC = 5.0 V 10% 60 -- ns output pin tIVSH Valid SIN SCK tIVSH -- VCC = 3.0 V 10% 120 -- ns tSHIX -- VCC = 5.0 V 10% 60 -- ns SCK valid SIN hold time -- VCC = 3.0 V 10% 120 -- ns tSHIX * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timing". Notes: * These are AC ratings in the CLK synchronous mode. * CL is the load capacitor connected to pins while testing. 92 MB90670/675 Series * Internal shift clock mode SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tSCYC 2.4 V 0.8 V tIVSH 2.4 VCC 0.8 VCC tSHIX 2.4 VCC 0.8 VCC SIN * External shift clock mode SCK 0.2 VCC tIVSH SOT tSLSH 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 2.4 V 0.2 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN 93 MB90670/675 Series (11) UART1 Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Parameter Min. Max. Serial clock cycle time tSCYC -- -- 8 tCP* -- ns tSLOV -- VCC = 5.0 V 10% - 80 80 ns Internal shift SCK SOT delay time tSLOV -- VCC = 3.0 V 10% - 120 120 ns clock mode tIVSH -- VCC = 5.0 V 10% 100 -- ns CL = 80 pF Valid SIN SCK -- VCC = 3.0 V 10% 200 -- ns + 1 TTL for an tIVSH output pin SCK valid SIN hold tSHIX -- 1 tCP* -- ns time Serial clock "H" pulse tSHSL -- -- 4 tCP* -- ns width Serial clock "L" pulse tSLSH -- 4 tCP* -- ns width External shift tSLOV -- VCC = 5.0 V 10% -- 150 ns clock mode SCK SOT delay time tSLOV -- VCC = 3.0 V 10% -- 200 ns CL = 80 pF + 1 TTL for an -- VCC = 5.0 V 10% 60 -- ns output pin tIVSH Valid SIN SCK tIVSH -- VCC = 3.0 V 10% 120 -- ns tSHIX -- VCC = 5.0 V 10% 60 -- ns SCK valid SIN hold time -- VCC = 3.0 V 10% 120 -- ns tSHIX * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timing". Notes: * These are AC ratings in the CLK synchronous mode. * CL is the load capacitor connected to pins while testing. 94 MB90670/675 Series * Internal shift clock mode SCK 0.8 V tSLOV SOT 2.4 V 0.2 V tSCYC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN * External shift clock mode SCK 0.2 VCC tSLOV SOT tSLSH 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC SIN 95 MB90670/675 Series (12) Timer Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min. Max. TIN0, TON1 -- 4 tCP* -- ns Parameter Input pulse width Symbol tTIWH, tTIWL * : For tCP (internal operating clock cycle time), refer to "(3) Clock Timing". 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC TIN tTIWH tTIWL (13) Timer Output Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. tTO TOT0, TOT1 VCC = 5.0 V 10% 30 -- ns TOT0, TOT1 VCC = 3.0 V 10% 80 -- ns tTO Parameter CLK TOUT transition time 2.4 V CLK TOUT 2.4 V 0.8 V tTO 96 MB90670/675 Series (14) I2C Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Condition Unit Remarks Min. Max. -- 0 100 kHz fSCL -- 4.7 -- s The first clock pulse is generated after this period. Parameter SCL clock frequency Bus free time between tBUS stop and start conditions Hold time (re-transmission) start LOW status hold time of SCL clock HIGH status hold time of SCL clock Setup time for conditions for starting re-transmission Data hold time Data setup time Rising time of SDA and SCL signals Falling time of SDA and SCL signals Setup time for stop conditions tHDSTA -- 4.0 -- s tLOW tHIGH tSUSTA tHDDAT tSUDAT tR tF tSUSTO -- -- -- -- -- -- -- -- -- 4.7 4.0 4.7 0 250 -- -- 4.0 -- -- -- -- -- 1000 300 -- s s s s ns ns ns s Note: Only MB90675 series has I2C. SDA tBUS 0.8 VCC 0.2 VCC tLOW tR tF tHDSTA 0.8 VCC 0.2 VCC tHDSTA tHDDAT tSUDAT tHIGH fSCL tSUSTA tSUSTO SCL 97 MB90670/675 Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH - AVRL, TA = -40C to +85C) Value Symbol Pin name Condition Unit Parameter Min. Typ. Max. Resolution -- -- -- -- 10 bit Total error -- -- -- -- 3.0 LSB Linearity error -- -- -- -- 2.0 LSB Differential linearity error -- -- -- -- 1.5 LSB -- AN0 to AVRL AVRL AVRL Zero transition voltage VOT - 1.5 LSB + 0.5 LSB + 2.5 LSB mV AN7 AN0 to AVRH AVRH AVRH Full-scale transition voltage VFST - 4.5 LSB - 1.5 LSB + 0.5 LSB mV AN7 VCC = 5.0 V 10% at machine clock of 6.125 -- -- s -- -- 16 MHz Conversion time VCC = 3.0 V 10% at machine clock of 12.25 -- -- s -- -- 8 MHz AN0 to Analog port input current IAIN -- 0.1 10 A AN7 AN0 to Analog input voltage VAIN AVRL -- AVRH V AN7 -- AVRL V -- AVRH -- AVCC - 2.7 Reference voltage AVRH -- AVRL 0 -- V - 2.7 IA AVCC -- 3 -- mA Supply current when CPU stopped and A/D Power supply current converter not in AVCC IAH -- -- 5 A operation (VCC = AVCC = AVRH = 5.0 V) IR AVRH -- -- 200 -- A Supply current when CPU Reference voltage supply stopped and A/D current converter not in IRH -- -- 5 A AVRH operation (VCC = AVCC = AVRH = 5.0 V) AN0 to Offset between channels -- -- -- -- 4 LSB AN7 98 MB90670/675 Series 6. A/D Converter Glossary Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF 3FE 3FD Actual conversion characteristics 0.5 LSB' {1 LSB x (N - 1) + 0.5 LSB} Digital output 004 003 002 001 VNT (Mesured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB' AVRL Analog input AVRH VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB' 1 LSB' = (Theoretical value) AVRH - AVRL 1024 [V] Total error for digital output N = [LSB] VOT' (Theoretical value) = AVRL + 0.5 LSB' [V] VFST' (Theoretical value) = AVRH - 1.5 LSB' [V] VNT: Voltage at a transition of digital output from (N - 1) to N (Continued) 99 MB90670/675 Series (Continued) Linearity error 3FF 3FE 3FD Actual conversion characteristics {1 LSB x (N - 1) + VOT'} N+1 VFST (Mesured value) VNT 004 003 002 001 Theoretical characteristics VOT (Mesured value) AVRL Analog input AVRH AVRL N-2 Actual conversion characteristics Differential linearity error Theoretical characteristics Actual conversion characteristics Digital output Digital output N N-1 V(N + 1)T (Mesured value) VNT (Mesured value) Actual conversion characteristics Analog input V(N + 1)T - VNT 1 LSB' AVRH Linearity error of VNT - {1 LSB x (N - 1) + VOT} [LSB] digital output N = 1 LSB' 1 LSB = AVRH - AVRL 1022 [V] Differential linearity error = of digital output N - 1 LSB [LSB] VOT: Voltage at transition of digital output from "000H" to "001H" VFST: Voltage at transition of digital output from "3FEH" to "3FFH" 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 7 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling time for analog voltages may not be sufficient (sampling time = 3.75 s @machine clock of 16 MHz). * Block diagram of analog input circuit model Sample hold circuit Analog input C0 Comparator RON1 RON2 RON3 RON4 C1 RON1: Approx. 1.5 k(VCC = 5.0 V) RON2: Approx. 0.5 k (VCC = 5.0 V) RON3: Approx. 0.5 k(VCC = 5.0 V) C0: Approx. 60 pF RON4: Approx. 0.5 k (VCC = 5.0 V) C1: Approx. 4 pF Note: Listed values must be considered as standards. * Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 100 MB90670/675 Series s EXAMPLE CHARACTERISTICS (1) "H" Level Output Voltage (2) "L" Level Output Voltage VOH (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 TA = +25C VOH vs. IOH VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VOL (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 TA = +25C VOL vs. IOL VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V -2 -4 -6 -8 IOH (mA) 2 4 6 8 IOL (mA) (3) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input) (4) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input) VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 VIN vs. VCC TA = +25C VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 VIN vs. VCC TA = +25C VIHS VILS 3 4 5 6 VCC (V) 3 4 5 6 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level 101 MB90670/675 Series (5) Power Supply Current (fCP = Internal Operating Clock Frequency) ICC vs. VCC ICCS vs. VCC TA = +25C ICC (mA) 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 3.0 4.0 ICCS (mA) 15 fCP = 16 MHz 14 TA = +25C 13 12 fCP = 12.5 MHz 11 10 9 8 fCP = 8 MHz 7 6 fCP = 4 MHz 5 4 3 2 1 0 5.0 6.0 3.0 VCC (V) fCP = 16 MHz fCP = 12.5 MHz fCP = 8 MHz fCP = 4 MHz 4.0 5.0 6.0 VCC (V) IA (mA) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 IA vs. AVCC TA = +25C fCP = 16 MHz IA (mA) 0.30 IR vs. AVR TA = +25C fCP = 16 MHz 0.20 0.10 0 4.0 5.0 6.0 AVCC (V) 3.0 4.0 5.0 6.0 AVR (V) (6) Pull-up Resistance R (k) 1000 R vs. VCC TA = +25C 100 10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC (V) 102 MB90670/675 Series s INSTRUCTIONS (340 INSTRUCTIONS) Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction. # ~ RG B Operation LH AH I S T N Z V C RMW Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. 103 MB90670/675 Series Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL:AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b (Continued) 104 MB90670/675 Series (Continued) Symbol rel ear eam rlst Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension * Meaning -- @RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 0 0 2 2 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address Note: The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions. 105 MB90670/675 Series Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing Listed in tables of instructions 1 2 1 1 2 2 0 0 00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F Note: "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles (b) byte Operand (c) word (d) long Number Number Number Number Number Number of of of of cycles access of cycles access of cycles access +0 +0 +0 +1 +1 +1 1 1 1 1 1 1 +0 +0 +2 +1 +4 +4 1 1 2 1 2 2 +0 +0 +4 +2 +8 +8 2 2 4 2 4 4 Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 -- Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations. 106 MB90670/675 Series Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 # ~ Transfer Instructions (Byte) [41 Instructions] R G 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) LA HH Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X - - - - - - - - - - - - - - - - - Z Z - - * * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 3 2 A, dir 4 3 A, addr16 2 2 A, Ri 2 2 A, ear 2+ 3+ (a) A, eam 3 2 A, io 2 2 A, #imm8 3 2 A, @A 5 A,@RWi+disp8 2 10 A, @RLi+disp8 3 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 2 2+ 5+ (a) 7 2 2+ 9+ (a) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 0 2x (b) byte ((A)) (AH) 0 2x (b) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 107 MB90670/675 Series Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 dir, A addr16, A SP A , RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16 # Transfer Instructions (Word/Long Word) [38 Instructions] ~ R G 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 word (A) ((RWi) +disp8) word (A) ((RLi) +disp8) word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi) +disp8) (A) word ((RLi) +disp8) (A) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3 2 4 3 1 1 2 1 2 2 2+ 3+ (a) 3 2 3 2 2 3 5 2 10 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 MOVW AL, AH /MOVW @A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam 4 2 2+ 5+ (a) 7 2 2+ 9+ (a) 0 2 0 2x (c) word ((A)) (AH) 0 4 2 2x (c) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) 0 (d) 0 0 (d) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A 2 4 2 2+ 5+ (a) 0 5 3 0 2 4 2 2+ 5+ (a) 0 - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * - - - - - - - - - - - - - - - Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 108 MB90670/675 Series Table 9 Mnemonic ADD A,#imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A SUB A, #imm8 SUB A, dir SUB A, ear SUB A, eam SUB ear, A SUB eam, A SUBC A SUBC A, ear SUBC A, eam SUBDC A ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL #imm32 SUBL SUBL SUBL #imm32 A, ear A, eam A, A, ear A, eam A, Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 R G B Operation LA HH Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - - - * - - - - byte (A) (A) +imm8 0 0 (b) byte (A) (A) +(dir) 0 byte (A) (A) +(ear) 0 1 (b) byte (A) (A) +(eam) 0 byte (ear) (ear) + (A) 0 2 0 2x (b) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) 0 0 byte (A) (A) + (ear) + (C) 0 1 (b) byte (A) (A) + (eam) + (C) 0 byte (A) (AH) + (AL) + (C) 0 0 (decimal) 0 0 (b) byte (A) (A) -imm8 0 byte (A) (A) - (dir) 0 1 (b) byte (A) (A) - (ear) 0 byte (A) (A) - (eam) 0 2 0 2x (b) byte (ear) (ear) - (A) byte (eam) (eam) - (A) 0 0 byte (A) (AH) - (AL) - (C) 0 1 (b) byte (A) (A) - (ear) - (C) 0 byte (A) (A) - (eam) - (C) 0 0 byte (A) (AH) - (AL) - (C) (decimal) word (A) (AH) + (AL) 0 0 word (A) (A) +(ear) 0 1 (c) word (A) (A) +(eam) 0 word (A) (A) +imm16 0 0 word (ear) (ear) + (A) 0 2 0 2x (c) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) 0 1 (c) word (A) (A) + (eam) + (C) 0 word (A) (AH) - (AL) 0 0 word (A) (A) - (ear) 0 1 (c) word (A) (A) - (eam) 0 word (A) (A) -imm16 0 0 word (ear) (ear) - (A) 0 2 0 2x (c) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) 0 1 (c) word (A) (A) - (eam) - (C) 0 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - * - - 2 6 2 2+ 7+ (a) 0 0 4 5 2 6 2 2+ 7+ (a) 0 0 4 5 0 (d) 0 0 (d) 0 long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 109 MB90670/675 Series Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ R G B Operation LA HH - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - S - - - - - - - - - - - - T - - - - - - - - - - - - N * * * * * * * * * * * * Z * * * * * * * * * * * * V * * * * * * * * * * * * C - - - - - - - - - - - - RM W - * - * - * - * - * - * byte (ear) (ear) +1 0 2 2 2 2+ 5+ (a) 0 2x (b) byte (eam) (eam) +1 byte (ear) (ear) -1 0 2 3 2 2+ 5+ (a) 0 2x (b) byte (eam) (eam) -1 2 3 2 0 word (ear) (ear) +1 2+ 5+ (a) 0 2x (c) word (eam) (eam) +1 2 3 2 0 word (ear) (ear) -1 2+ 5+ (a) 0 2x (c) word (eam) (eam) -1 long (ear) (ear) +1 0 4 7 2 2+ 9+ (a) 0 2x (d) long (eam) (eam) +1 long (ear) (ear) -1 0 4 7 2 2+ 9+ (a) 0 2x (d) long (eam) (eam) -1 DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 A, ear A, eam A, #imm32 # Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ R G 0 1 0 0 0 1 0 0 B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32 LA HH - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V * * * * * * * * * * * C * * * * * * * * * * * RM W - - - - - - - - - - - 1 1 2 2 2+ 3+ (a) 2 2 1 1 2 2 2+ 3+ (a) 2 3 2 6 2 2+ 7+ (a) 0 5 3 0 Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 110 MB90670/675 Series Table 12 Mnemonic DIVU DIVU ear DIVU eam A A, A, 2 *4 1 0 0 1 0 0 1 0 2+ *5 1 *8 2 *9 2+ *10 1 *11 2 *12 2+ *13 # 1 2 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] ~ *1 *2 R G 0 1 0 B Operation LA HH - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N - - - - - - - - - - - Z - - - - - - - - - - - V * * * * * - - - - - - C * * * * * - - - - - - RM W - - - - - - - - - - - 2+ *3 DIVUW A, ear DIVUW A, eam MULU MULU ear MULU eam A A, A, 0 word (AH) /byte (AL) Quotient byte (AL) Remainder 0 byte (AH) word (A)/byte (ear) *6 Quotient byte (A) Remainder byte (ear) 0 word (A)/byte (eam) Quotient byte (A) Remainder *7 byte (eam) long (A)/word (ear) Quotient word (A) Remainder 0 word (ear) 0 long (A)/word (eam) (b) Quotient word (A) Remainder word (eam) 0 0 byte (AH) *byte (AL) word (A) (c) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A) MULUW A MULUW A, ear MULUW A, eam *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 111 MB90670/675 Series Table 13 Logical 1 Instructions (Byte/Word) [39 Instructions] Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ R G B Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - * 2 2 3 2 2+ 4+ (a) 3 2 2+ 5+ (a) 2 2 3 2 2+ 4+ (a) 3 2 2+ 5+ (a) 2 2 3 2 2+ 4+ (a) 3 2 2+ 5+ (a) 0 0 0 1 (b) 0 0 2 0 2x (b) 0 0 0 1 (b) 0 0 2 0 2x (b) 0 0 0 1 (b) 0 0 2 0 2x (b) byte (A) not (A) 0 0 2 1 byte (ear) not (ear) 0 2 3 2 2+ 5+ (a) 0 2x (b) byte (eam) not (eam) 0 0 0 0 0 1 (c) 0 0 2 0 2x (c) 0 0 0 0 0 1 (c) 0 0 2 0 2x (c) 0 0 0 0 0 1 (c) 0 0 2 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) 2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A 2+ 5+ (a) eam, A 2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A 2+ 5+ (a) eam, A 2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A 2+ 5+ (a) eam, A NOTW A NOTW ear NOTW eam word (A) not (A) 0 0 2 1 word (ear) not (ear) 0 2 3 2 2+ 5+ (a) 0 2x (c) word (eam) not (eam) Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 112 MB90670/675 Series Table 14 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # ~ Logical 2 Instructions (Long Word) [6 Instructions] R G B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LA HH - - - - - - - - - - - - I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V R R R R R R C RM W - - - - - - - - - - - - 2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0 XORL A, ea XORL A, eam Table 15 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2 Sign Inversion Instructions (Byte/Word) [6 Instructions] R G 0 B 0 Operation byte (A) 0 - (A) LA HH X - - - - - - - - - - - I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V * * * * * * C RM W * * * * * * - - * - - * byte (ear) 0 - (ear) 0 2 3 2 2+ 5+ (a) 0 2x (b) byte (eam) 0 - (eam) 1 2 0 0 word (A) 0 - (A) NEGW A NEGW ear NEGW eam word (ear) 0 - (ear) 0 2 3 2 2+ 5+ (a) 0 2x (c) word (eam) 0 - (eam) Table 16 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 Normalize Instruction (Long Word) [1 Instruction] B 0 Operation long (A) Shift until first digit is "1" byte (R0) Current shift count LA HH - - I - S - T - N - Z * V - C - RM W - *1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 113 MB90670/675 Series Table 17 Mnemonic RORCA ROLC A RORCear RORCeam ROLC ear ROLC eam ASR A, R0 LSR A, R0 LSL A, R0 # 2 2 ~ 2 2 R G 0 0 Shift Instructions (Byte/Word/Long Word) [18 Instructions] B 0 0 Operation byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Arithmetic right shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0) LA HH - - - - - - - - - - - - - - - - - - I - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - * * - * * * * * * * * * * * * * * * * * * - - - - - - - - - * * * * * * * * * - - - * - * - - - 3 2 2+ 5+ 2 (a) 2+ 3 5+ 2 (a) 2 2 *1 *1 *1 0 2 0 2x (b) 0 2 0 2x (b) 1 1 1 0 0 0 ASRWA LSRWA/SHRW A LSLW A/SHLW A ASRWA, R0 LSRWA, R0 LSLW A, R0 1 1 1 2 2 2 2 2 2 *1 *1 *1 0 0 0 1 1 1 0 0 0 0 0 0 - - - - - - - - - - - - - - - - - - - - - - - - ** *R -* * * - * * * * * * * * * - - - - - - * * * * * * - - - - - - ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 *2 *2 *2 1 1 1 0 0 0 - - - - - - - - - - - - * * - * * * * * * - - - * * * - - - *1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 114 MB90670/675 Series Table 18 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 ~ *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15 (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15 (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23 LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @A addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6 (c) 1 0 2x (c) (c) 0 0 2x (c) 2 2x (c) 0 *2 CALLP @eam *6 CALLP addr24 *7 2+ 11+ (a) 4 10 0 2x (c) *1: *2: *3: *4: *5: *6: *7: 4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 115 MB90670/675 Series Table 19 Mnemonic CBNE A, #imm8, rel CWBNEA, #imm16, rel CBNE ear, #imm8, rel CBNE eam, #imm8, rel*9 CWBNEear, #imm16, rel CWBNEeam, #imm16, rel*9 DBNZ ear, rel DBNZ eam, rel 3 *5 3+ *6 DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24 2 3 4 1 1 2 #local8 1 UNLINK RET *7 RETP *8 1 1 5 4 6 0 0 0 (c) (c) (d) 20 16 17 20 15 6 0 0 0 0 0 0 2 2 # ~ RG 0 0 1 0 1 0 2 2 B 0 0 0 (b) 0 (c) Branch 2 Instructions [19 Instructions] Operation Branch when byte (A) imm8 Branch when word (A) imm16 LA HH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - R R R R * - S - - - - - - - - - - S S S S * - T - - - - - - - - - - - - - - * - N * * * * * * * * * * - - - - * - Z * * * * * * * * * * - - - - * - V * * * * * * * * * * - - - - * - C RM W * * * * * * - - - - - - - - * - - - - - - - - * - * - - - - - - 3 *1 4 *1 4 4+ 5 5+ *2 *3 *4 *3 3 *5 3+ *6 Branch when byte (ear) imm8 Branch when byte (eam) 0 imm8 Branch when word (ear) 2x (b) imm16 Branch when word (eam) imm16 0 Branch when byte (ear) = 2x (c) (ear) - 1, and (ear) 0 Branch when byte (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) Branch when word (ear) = 6x (c) (ear) - 1, and (ear) 0 8x (c) Branch when word (eam) = 6x (c) (eam) - 1, and (eam) 0 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt - - - - - - - - - - - - - - - - - - - - - - - - - - - - At constant entry, save old - frame pointer to stack, set - new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine *1: *2: *3: *4: *5: *6: *7: *8: *9: 5 when branching, 4 when not branching 13 when branching, 12 when not branching 7 + (a) when branching, 6 + (a) when not branching 8 when branching, 7 when not branching 7 when branching, 6 when not branching 8 + (a) when branching, 7 + (a) when not branching Retrieve (word) from stack Retrieve (long word) from stack In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 116 MB90670/675 Series Table 20 Mnemonic PUSHWA PUSHWAH PUSHWPS PUSHWrlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [28 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2 RG 0 0 0 *5 0 0 0 *5 B (c) (c) (c) *4 (c) (c) (c) *4 Operation word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) LA HH - - - - - - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - - I - - - - - - * - * * * - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AND CCR, #imm8 OR CCR, #imm8 MOV RP, #imm8 MOV ILM, #imm8 word (A) ((SP)), (SP) (SP) 0 6x (c) +2 word (AH) ((SP)), (SP) 0 0 (SP) +2 0 0 word (PS) ((SP)), (SP) (SP) +2 0 0 (rlst) ((SP)), (SP) (SP) 0 0 +2n 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Context switch instruction 2 3 2+ 2+ (a) 2 MOVEA RWi, ear 1 MOVEA RWi, eam 2+ 1+ (a) MOVEA A, ear 2 MOVEA A, eam 3 3 3 ADDSP #imm8 2 ADDSP #imm16 *1 2 1 MOV A, brgl 1 MOV brg2, A 1 1 1 1 NOP 1 1 ADB 1 1 DTB 1 1 PCB 1 1 SPB 1 NCC CMR - - byte (CCR) (CCR) and imm8 - byte (CCR) (CCR) or imm8 - byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank - - Z - - - - - - - - *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) 117 MB90670/675 Series *5: Pop count or push count. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 21 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC rel BBC BBS BBS rel BBS dir:bp, rel addr16:bp, io:bp, rel dir:bp, rel addr16:bp, io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4 RG 0 0 0 Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LA HH Z Z Z - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - S T N Z V C RM W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - - 0 2x (b) bit (dir:bp) b (A) 0 2x (b) bit (addr16:bp) b (A) 0 2x (b) bit (io:bp) b (A) 0 2x (b) bit (dir:bp) b 1 0 2x (b) bit (addr16:bp) b 1 0 2x (b) bit (io:bp) b 1 0 2x (b) bit (dir:bp) b 0 0 2x (b) bit (addr16:bp) b 0 0 2x (b) bit (io:bp) b 0 0 0 0 0 0 0 (b) (b) (b) (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5: 0 2x (b) Branch when (addr16:bp) b = 1, - bit = 1 - 0 *5 Wait until (io:bp) b = 1 - 0 *5 Wait until (io:bp) b = 0 8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 118 MB90670/675 Series Table 22 Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 R G 0 0 0 0 0 0 B 0 0 0 0 0 0 Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension LA HH - - X - Z - - * - X - Z I - - - - - - S - - - - - - T - - - - - - N - - * * R R Z - - * * * * V - - - - - - C RM W - - - - - - - - - - - - Table 23 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ *2 *2 *1 *1 R GB *5 *5 *5 *5 String Instructions [10 Instructions] Operation LA HH - - - - - - - - - - I - - - - - S - - - - - T - - - - - N - - * * * Z - - * * * V - - * * - C RM W - - * * - - - - - - 2 6m +6 *5 *3 Byte transfer @AH+ @AL+, counter *3 = RW0 Byte transfer @AH- @AL-, counter *4 = RW0 *4 Byte retrieval (@AH+) - AL, counter = *3 RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0 MOVSW/ MOVSWI MOVSWD SCWEQ/ SCWEQI SCWEQD FILSW/FILSWI 2 2 2 2 *2 *2 *1 *1 *8 *8 *8 *8 2 6m +6 *8 *6 Word transfer @AH+ @AL+, counter *6 = RW0 Word transfer @AH- @AL-, counter *7 = RW0 *7 Word retrieval (@AH+) - AL, counter = *6 RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0 - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * - - * * * - - * * - - - * * - - - - - - m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." 119 MB90670/675 Series s MASK OPTIONS * MB90670 series Part number No. Specifying procedure Pull-up resistors P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80, RST, MD1, MD0 Pull-down resistors MD1, MD0 MB90671 MB90672 MB90673 Specify when ordering masking MB90P673 Set with EPROM programmer MB90V670 Setting not possible 1 Specify by pin Specify by pin Without pull-up resistor 2 Specify by pin Specify by pin Without pull-up resistor * MB90675 series Part number No. Specifying procedure Pull-up resistors P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P86, P90, P91, PA0 to PA7, PB0 to PB2, RST, MD1, MD0 Pull-down resistors MD1, MD0 MB90676 MB90677 MB90678 Specify when ordering masking MB90P678 Set with EPROM programmer MB90V670 Setting not possible 1 Specify by pin Specify by pin Without pull-up resistor 2 Specify by pin Specify by pin Without pull-up resistor Notes: * The pull-up register configured as a port pin is switched-off in the stop mode and during the hardware standby. * In turning on power, option settings can not be made until clocks are supplied because 8 machine cycles are needed for option settings for the MB90P670/P675. 120 MB90670/675 Series s ORDERING INFORMATION Part number MB90671PFV MB90672PFV MB90673PFV MB90T673PFV MB90P673PFV MB90671PF MB90672PF MB90673PF MB90T673PF MB90P673PF MB90676PFV MB90677PFV MB90678PFV MB90T678PFV MB90P678PFV MB90676PF MB90677PF MB90678PF MB90T678PF MB90P678PF Package 80-pin Plastic LQFP (FPT-80P-M05) Remarks 80-pin Plastic QFP (FPT-80P-M06) 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) 121 MB90670/675 Series s PACKAGE DIMENSIONS 80-pin Plastic LQFP (FPT-80P-M05) 14.000.20(.551.008)SQ 60 12.000.10(.472.004)SQ 1.50 -0.10 +.008 .059 -.004 41 +0.20 (Mounting height) 61 40 9.50 (.374) REF INDEX 80 21 13.00 (.512) NOM LEAD No. 1 20 "A" 0.127 -0.02 +.002 .005 -.001 +0.05 Details of "A" part 0.500.08 (.0197.0031) 0.18 -0.03 +.003 .007 -.001 +0.08 0.100.10 (STAND OFF) (.004.004) 0.500.20(.020.008) 0.10(.004) 0 10 C 1995 FUJITSU LIMITED F80008S-2C-5 Dimensions in mm (inches) 80-pin Plastic QFP (FPT-80P-M06) 23.900.40(.941.016) 64 65 20.000.20(.787.008) 41 40 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 14.000.20 (.551.008) INDEX 80 25 17.900.40 (.705.016) 12.00(.472) REF 16.300.40 (.642.016) "A" LEAD No. 1 24 0.80(.0315)TYP 0.350.10 (.014.004) 0.16(.006) M 0.150.05(.006.002) Details of "A" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX Details of "B" part 0 10 0.800.20 (.031.008) C 1994 FUJITSU LIMITED F80010S-3C-2 Dimensions in mm (inches) 122 MB90670/675 Series 100-pin Plastic LQFP (FPT-100P-M05) 16.000.20(.630.008)SQ 75 14.000.10(.551.004)SQ 51 1.50 -0.10 +.008 .059 -.004 +0.20 (Mounting height) 76 50 12.00 (.472) REF INDEX 15.00 (.591) NOM Details of "A" part 0.15(.006) 100 26 0.15(.006) 0.15(.006)MAX LEAD No. 1 25 "B" +0.05 "A" 0.50(.0197)TYP 0.18 -0.03 +.003 .007 -.001 +0.08 0.40(.016)MAX 0.127 -0.02 +.002 .005 -.001 0.08(.003) M Details of "B" part 0.100.10 (STAND OFF) (.004.004) 0.10(.004) 0.500.20(.020.008) 0~10 C 1995 FUJITSU LIMITED F100007S-2C-3 Dimensions in mm (inches) 100-pin Plastic QFP (FPT-100P-M06) 23.900.40(.941.016) 80 81 3.35(.132)MAX (Mounting height) 51 50 20.000.20(.787.008) 0.05(.002)MIN (STAND OFF) 14.000.20 (.551.008) INDEX 100 31 17.900.40 (.705.016) 12.35(.486) REF 16.300.40 (.642.016) "A" LEAD No. 1 30 0.65(.0256)TYP 0.300.10 (.012.004) 0.13(.005) M 0.150.05(.006.002) Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX 0 10 0.800.20 (.031.008) Details of "B" part C 1994 FUJITSU LIMITED F100008-3C-2 Dimensions in mm (inches) 123 MB90670/675 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9811 (c) FUJITSU LIMITED Printed in Japan 124 |
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