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| N-Channel JFET Switch CORPORATION J111 - J113 / SST111 - SST113 FEATURES Low Cost Automated Insertion Package Low Insertion Loss No Offset or Error Voltage Generated By Closed Switch Purely Resistive High Isolation Resistance From Driver Fast Switching Short Sample and Hold Aperture Time * * * * * * APPLICATIONS Analog Switches Choppers Commutators * * * - PIN CONFIGURATION SOT-23 G TO-92 ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise specified) Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -35V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC Operating Temperature Range . . . . . . . . . . . -55oC to +135oC Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . 3.3mW/ oC NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D S G DS PRODUCT MARKING (SOT-23) SST111 SST112 SST113 111 112 113 ORDERING INFORMATION Part Package Temperature Range J111-113 Plastic SOT-23 -55oC to +135oC SST111-113 Plastic SOT-23 -55oC to +135oC For Sorted Chips in Carriers see 2N4391 series. 5001 ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified) SYMBOL IGSSR VGS(off) BVGSS IDSS ID(off) rDS(on) Cdg(off) Csg(off) Cdg(on) + Csg(on) td(on) tr td(off) tf PARAMETER Gate Reverse Current (Note 1) Gate Source Cutoff Voltage Gate Source Breakdown Voltage Drain Saturation Current (Note 2) Drain Cutoff Current (Note 1) Drain Source ON Resistance Drain Gate OFF Capacitance Source Gate OFF Capacitance Drain Gate Plus Source Gate ON Capacitance Turn On Delay Time Rise Time Turn Off Delay Time Fall Time o 111 112 113 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX -1 -1 -1 nA -3 -10 -1 -5 -0.5 -3 V -35 -35 -35 20 5 2 mA 1 1 1 nA 30 50 100 5 5 5 5 28 7 6 20 15 7 6 20 15 5 28 7 6 20 15 5 28 pF TEST CONDITIONS VDS = 0V, VGS = -15V VDS = 5V, ID = 1A VDS = 0V, IG = -1A VDS = 15V, VGS = 0V VDS = 5V, VGS = -10V VDS = 0.1V, VGS = 0V VDS = 0, VGS = -10V (Note 3) f = 1MHz VDS = VGS = 0 (Note 3) Switching Time Test Conditions (Note 3) J111 J112 J113 VDD 10V 10V 10V VGS(off) -12V -7V -5V RL 0.8k 1.6k 3.2k ns NOTES: 1. Approximately doubles for every 10 C increase in TA. 2. Pulse test duration 300s; duty cycle 3%. 3. For design reference only, not 100% tested. CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076 |
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