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3.3V 1:22 HIGH-PERFORMANCE, LOW VOLTAGE BUS CLOCK DRIVER
FEATURES
s 3.3V core supply, 1.8V output supply for reduced s s s s s s
ClockWorksTM SY89824L
DESCRIPTION
The SY89824L is a High Performance Bus Clock Driver with 22 differential HSTL (High Speed Transceiver Logic) output pairs. The part is designed for use in low voltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89824L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)--performance previously unachievable in a standard product having such a high number of outputs. The SY89824L is available in a single space saving package, enabling a lower overall cost solution.
power LVPECL and HSTL inputs 22 differential HSTL (low-voltage swing) output pairs HSTL outputs drive 50 to ground with no offset voltage Low part-to-part skew (200ps max.) Low pin-to-pin skew (50ps max.) Available in a 64-Pin EPAD HQFP
PIN CONFIGURATION
Q0 Q0 VCCO
VCCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Q1 Q1
Q2 Q2
Q3 Q3
Q4 Q4
Q5 Q5
Q6 Q6
VCCO NC NC VCCI HSTL_CLK HSTL_CLK CLK_SEL LVPECL_CLK LVPECL_CLK GND OE NC NC Q21 Q21 VCCO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42
VCCO Q7 Q7 Q8 Q8 Q9 Q9 Q10 Q10 Q11 Q11 Q12 Q12 Q13 Q13 VCCO
PIN NAMES
Pin HSTL_CLK, /HSTL_CLK LVPECL_CLK, /LVPECL_CLK CLK_SEL OE Q0-Q21, /Q0-/Q21 GND VCCI VCCO Function Differential HSTL Inputs Differential LVPECL Inputs Input CLK Select (LVTTL) Output Enable (LVTTL) Differential HSTL Outputs Ground VCC Core VCC Output
64-PIN HQFP
41 40 39 38 37 36 35 34 33
APPLICATIONS
s High-performance PCs s Workstations s Parallel processor-based systems s Other high-performance computing s Communications
VCCO
Q20 Q20
Q19 Q19
Q18 Q18
Q17 Q17
Q16 Q16
Q15 Q15
Q14 Q14
VCCO
LOGIC SYMBOL
CLK_SEL HSTL_CLK HSTL_CLK
0 22 22 Q0 - Q21 Q0 - Q21
LVPECL_CLK
1
LVPECL_CLK LEN Q OE D
Rev.: C
Amendment: /1
1
Issue Date: March 2000
Micrel
ClockWorksTM SY89824L
TRUTH TABLE
OE(1) 0 0 1 1 CLK_SEL 0 1 0 1 Q0-Q21 LOW LOW HSTL_CLK LVPECL_CLK /Q0-/Q21 HIGH HIGH /HSTL_CLK /LVPECL_CLK
SIGNAL GROUPS
Level HSTL HSTL LVPECL LVCMOS/LVTTL Direction Input Output Input Input Signal HSTL_CLK, /HSTL_CLK Q0-Q21, /Q0-/Q21 LVPECL_CLK, /LVPECL_CLK CLK_SEL, OE
NOTE: 1. The OE (output enable) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCCI/VCCO VIN IOUT Tstore Rating VCC Pin Potential to Ground Pin Input Voltage DC Output Current (Output HIGH) Storage Temperature Value -0.5 to +4.0 -0.5 to VCCI -50 -65 to +150 Unit V V mA C
NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Power Supply
TA = 0C Symbol VCCI VCCO ICCI VCC Core VCC Output ICC Core Parameter Min. 3.0 1.6 -- Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Min. 3.0 1.6 -- TA = +25C Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Min. 3.0 1.6 -- TA = +70C Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Unit V V mA
HSTL
TA = 0C Symbol VOH VOL VIH VIL VX IIH IIL Parameter Output HIGH Output LOW Voltage(1) Voltage(1) Min. 1.0 0 VX +0.1 -0.3 0.68 +20 -- Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Min. 1.0 0 VX +0.1 -0.3 0.68 +20 -- TA = +25C Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Min. 1.0 0 VX +0.1 -0.3 0.68 +20 -- TA = +70C Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Unit V V V V V A A
Input HIGH Voltage Input LOW Voltage Input Crossover Voltage Input HIGH Current Input LOW Current
NOTE: 1. Outputs loaded with 50 to ground.
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Micrel
ClockWorksTM SY89824L
DC ELECTRICAL CHARACTERISTICS
LVPECL
TA = 0C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. Max. TA = +25C Min. Max. TA = +70C Min. Max. Unit V V A A
VCCI - 1.165 VCCI - 0.880 VCCI - 1.165 VCCI - 0.880 VCCI - 1.165 VCCI - 0.880 VCCI - 1.810 VCCI - 1.475 VCCI - 1.810 VCCI - 1.475 VCCI - 1.810 VCCI - 1.475 -- 0.5 +150 -- -- 0.5 +150 -- -- 0.5 +150 --
LVCMOS/LVTTL
TA = 0C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. 2.0 -- +20 -- Typ. -- -- -- -- Max. -- 0.8 -250 -600 Min. 2.0 -- +20 -- TA = +25C Typ. -- -- -- -- Max. -- 0.8 -250 -600 Min. 2.0 -- +20 -- TA = +70C Typ. -- -- -- -- Max. -- 0.8 -250 -600 Unit V V A A
AC ELECTRICAL CHARACTERISTICS(1)
TA = 0C Symbol tPHL tPLH tskew tskpp VPP VCMR tS tH tr tf Parameter Propagation Delay(2) Min. -- -- -- 600 -1.5 1.0 0.5 300 Typ. 1.0 -- -- -- -- -- -- -- Max. -- 50 200 -- -0.4 -- -- 800 Min. -- -- -- 600 -1.5 1.0 0.5 300 TA = +25C Typ. 1.0 -- -- -- -- -- -- -- Max. -- 50 200 -- -0.4 -- -- 800 TA = +70C Min. -- -- -- 600 -1.5 1.0 0.5 300 Typ. 1.0 -- -- -- -- -- -- -- Max. -- 50 200 -- -0.4 -- -- 800 Unit ns ps ps mV V ns ns ps
Within-Device Skew(3) Part-to-Part Skew(4) Swing(5) Minimum Input LVPECL_CLK
Common Mode Range(6) LVPECL_CLK OE Set-Up Time(7) OE Hold Time Output Rise/Fall Time (20% - 80%)
NOTES: 1. Outputs loaded with 50 to ground. Airflow 300 LFPM. 2. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 4. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 5. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 6. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to PRODUCT ORDERING CODE VPP (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V - |VCMR (min)|. 7. OE set-up time is defined with respect to the rising edge of the clock. Ordering Package Operating OE HIGH to LOW transition ensures outputs remain disabled during Code Type Range the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. SY89824LHC H64-1 Commercial
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Micrel
ClockWorksTM SY89824L
64 LEAD EPAD-TQFP (DIE UP) (H64-1)
+0.05 -0.05 +0.002 -0.002
+0.05 -0.05 +0.012 -0.012
+0.03 -0.03 +0.012 -0.012
+0.15 -0.15 +0.006 -0.006
+0.05 -0.05 +0.002 -0.002
Rev. 02
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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