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M FEATURES 24LC024/24LC025 2K 2.5V I2CTM Serial EEPROM PACKAGE TYPES PDIP/SOIC A0 A1 A2 Vss 1 8 Vcc WP* SCL SDA * Single supply with operation from 2.5 to 5.5V * Low power CMOS technology - 1 mA active current typical - 10 A standby current typical at 5.5V * Organized as a single block of 128 bytes (256 x 8) * Hardware write protection for entire array (24LC024) * 2-wire serial interface bus, I2C compatible * 100kHz and 400kHz compatibility * Page-write buffer for up to 16 bytes * Self-timed write cycle (including auto-erase) * 3.5 ms typical write cycle time for page write * Address lines allow up to eight devices on bus * 10,000,000 erase/write cycles guaranteed * ESD protection > 4,000V * Data retention > 200 years * 8-pin PDIP, SOIC or TSSOP packages * Available for extended temperature ranges - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C 24LC024 24LC025 2 3 4 7 6 5 TSSOP A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP* SCL SDA DESCRIPTION The Microchip Technology Inc. 24LC024/24LC025 is a 2K bit Serial Electrically Erasable PROM with a voltage range of 2.5V to 5.5V. The device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. Low current design permits operation with typical standby and active currents of only 10 A and 1 mA respectively. The device has a page-write capability for up to 16 bytes of data. Functional address lines allow the connection of up to eight 24LC024/24LC025 devices on the same bus for up to 16K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (150 mil), and TSSOP packages. *WP pin available only on 24LC024. This pin has no internal connection on 24LC025 BLOCK DIAGRAM A0 A1 A2 WP* HV Generator 24LC024 25LC025 I/O Control Logic Memory Control Logic XDEC EEPROM Array SDA SCL VCC VSS Write Protect Circuitry YDEC SENSE AMP R/W CONTROL *WP pin available only on 24LC024. This pin has no internal connection on 24LC025 (c) 1997 Microchip Technology Inc. Preliminary DS21210A-page 1 24LC024/24LC025 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* TABLE 1-1: Name VSS SDA SCL VCC A0, A1, A2 WP NC PIN FUNCTION TABLE Function Ground Serial Data Serial Clock +2.5V to 5.5V Power Supply Chip Selects Hardware Write Protect (24LC024) No internal connection VCC ........................................................................ 7.0V All inputs and outputs w.r.t. VSS...... -0.6V to VCC +1.0V Storage temperature ...........................-65C to +150C Ambient temp. with power applied.......-65C to +125C Soldering temperature of leads (10 seconds) ...+300C ESD protection on all pins ...................................... 4 kV *Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: DC CHARACTERISTICS VCC = +2.5V to +5.5V Commercial (C): Industrial (I): Symbol VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Read ICC Write ICCS -10 -10 -- -- -- -- 0.05 VCC Min. 0.7 VCC 0.3 VCC -- 0.40 10 10 10 1 3 50 Tamb = 0 C to +70C Tamb = -40C to +85 C Max. Units V V V V A A pF mA mA A (Note) IOL = 3.0 mA, VCC = 4.5V IOL = 2.1 mA, VCC = 2.5V VIN = 0.1V to 5.5V, WP = Vss VOUT = 0.1V to 5.5V VCC = 5.0V (Note) Tamb = 25 C, f = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V VCC = 5.5V, SDA = SCL = VCC A0, A1, A2 = Vss Conditions All parameters apply across the specified operating ranges unless otherwise noted. Parameter SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Note: This parameter is periodically sampled and not 100% tested. DS21210A-page 2 Preliminary (c) 1997 Microchip Technology Inc. 24LC024/24LC025 TABLE 1-3: AC CHARACTERISTICS Tamb = 0 C to +70C Tamb = -40 C to +85 C Remarks All parameters apply across the specified operat- Vcc = 2.5V to 5.5V ing ranges unless otherwise noted. Commercial (C): Industrial (I): Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Vcc = 2.5V - 5.5V Vcc = 4.5V - 5.5V STD MODE FAST MODE Units Symbol Min. FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max. 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Min. -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max. 400 -- -- 300 300 -- -- -- -- -- 900 -- kHz ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2) Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance TOF TSP TWC -- -- -- 10M 250 50 10 -- 20 +0.1 CB -- -- 10M 250 50 10 -- ns ns (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3) ms Byte or Page mode cycles 25C, VCC = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. FIGURE 1-1: BUS TIMING DATA TF THIGH TR SCL TSU:STA TLOW THD:DAT TSU:DAT TSU:STO SDA IN THD:STA TSP TAA TBUF SDA OUT (c) 1997 Microchip Technology Inc. Preliminary DS21210A-page 3 24LC024/24LC025 2.0 2.1 PIN DESCRIPTIONS SDA Serial Data 3.0 FUNCTIONAL DESCRIPTION This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. The 24LC024/24LC025 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24LC024/24LC025 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 2.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 2.3 A0, A1, A2 The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24LC024/24LC025 devices may be connected to the same bus by using different chip select bit combinations. These inputs must be connected to either VCC or VSS. 2.4 WP (24LC024 only) This is the hardware write protect pin. It must be tied to VCC or VSS. If tied to Vcc, the hardware write protection is enabled. If the WP pin is tied to Vss the hardware write protection is disabled. Note that the WP pin is available only on the 24LC024. This pin is not internally connected on the 24LC025. 2.5 Noise Protection The 24LC024/24LC025 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. DS21210A-page 4 Preliminary (c) 1997 Microchip Technology Inc. 24LC024/24LC025 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 4-1). The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 4.1 Bus not Busy (A) 4.5 Acknowledge Both data and clock lines remain HIGH. 4.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24LC024/24LC025 does not generate any acknowledge bits if an internal programming cycle is in progress. 4.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 4-2). FIGURE 4-1: SCL (A) (B) DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS (C) (D) (C) (A) SDA START CONDITION ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. (c) 1997 Microchip Technology Inc. Preliminary DS21210A-page 5 24LC024/24LC025 5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Chip Select Bits 0 A2 A1 A0 R/W ACK A control byte is the first byte received following the start condition from the master device (Figure 5-1). The control byte consists of a four bit control code; for the 24LC024/24LC025 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24LC024/ 24LC025 devices on the same bus and are used to select which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1, and A0 pins for the device to respond. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. Following the start condition, the 24LC024/ 24LC025 monitors the SDA bus checking the control byte being transmitted. Upon receiving a 1010 code and appropriate chip select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC024/24LC025 will select a read or write operation. Control Code S 1 0 1 Slave Address Start Bit Acknowledge Bit 5.1 Contiguous Addressing Across Multiple Devices The chip select bits A2, A1, A0 can be used to expand the contiguous address space for up to 16K bits by adding up to eight 24LC024/24LC025 devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9, and A2 as address bit A10. It is not possible to sequentially read across device boundaries. DS21210A-page 6 Preliminary (c) 1997 Microchip Technology Inc. 24LC024/24LC025 6.0 6.1 WRITE OPERATIONS Byte Write 6.2 Page Write Following the start signal from the master, the device code(4 bits), the chip select bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC024/ 24LC025. After receiving another acknowledge signal from the 24LC024/24LC025 the master device will transmit the data word to be written into the addressed memory location. The 24LC024/24LC025 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LC024/24LC025 will not generate acknowledge signals (Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection (24LC024 only) has been enabled, the device will acknowledge the command but no data will be written. The write cycle time must be observed even if the write protection is enabled. The write control byte, word address and the first data byte are transmitted to the 24LC024/24LC025 in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 24LC024/24LC025 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address pointer bits are internally incremented by one. The higher order four bits of the word address remains constant. If the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. The write cycle time must be observed even if the write protection is enabled. 6.3 WRITE PROTECTION The WP pin (available on 24LC024 only) must be tied to VCC or VSS. If tied to VCC, the entire array will be write protected. If the WP pin is tied to VSS, then write operations to all address locations are allowed. FIGURE 6-1: BUS ACTIVITY MASTER SDA LINE BYTE WRITE S T A R T S A C K A C K A C K CONTROL BYTE WORD ADDRESS DATA S T O P P BUS ACTIVITY FIGURE 6-2: BUS ACTIVITY MASTER PAGE WRITE S T A R T CONTROL BYTE WORD ADDRESS (n) S T O P DATA n DATA n +1 DATA n + 15 SDA LINE BUS ACTIVITY S A C K A C K A C K A C K A C K P (c) 1997 Microchip Technology Inc. Preliminary DS21210A-page 7 24LC024/24LC025 7.0 ACKNOWLEDGE POLLING FIGURE 7-1: Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow diagram. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? YES Next Operation NO DS21210A-page 8 Preliminary (c) 1997 Microchip Technology Inc. 24LC024/24LC025 8.0 READ OPERATIONS Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24LC024/ 24LC025 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC024/24LC025 discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read. 8.1 Current Address Read The 24LC024/24LC025 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the 24LC024/24LC025 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC024/24LC025 discontinues transmission (Figure 8-1). 8.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24LC024/24LC025 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LC024/24LC025 to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads the 24LC024/24LC025 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 0FFh to address 000h. 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC024/24LC025 as part of a write operation. After the word address is sent, the master generates a start FIGURE 8-1: CURRENT ADDRESS READ S T BUS ACTIVITY A MASTER R T SDA LINE S BUS ACTIVITY CONTROL BYTE S T O P P A C K DATA N O A C K FIGURE 8-2: RANDOM READ S T BUS ACTIVITY A MASTER R T SDA LINE BUS ACTIVITY CONTROL BYTE WORD ADDRESS (n) S T A R T CONTROL BYTE S T O P S A C K A C K S A C K DATA (n) N O A C K P FIGURE 8-3: SEQUENTIAL READ CONTROL BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T O P P N O A C K A C K A C K A C K A C K (c) 1997 Microchip Technology Inc. Preliminary DS21210A-page 9 24LC024/24LC025 NOTES: DS21210A-page 10 Preliminary (c) 1997 Microchip Technology Inc. 24LC024/24LC025 24LC024/24LC025 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 24LC024/24LC025 -- /P P = Plastic DIP (300 mil Body), 8-lead Package: SN = Plastic SOIC (150 mil Body), 8-lead ST = TSSOP, 8-lead Temperature Range: Blank = 0C to +70C I = -40C to +85C 24LC024 24LC024T Device: 24LC025 24LC025T 2K I 2C Serial EEPROM with WP 2K I 2C Serial EEPROM with WP pin (Tape and Reel) 2K I 2C Serial EEPROM 2K I 2C Serial EEPROM (Tape and Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). (c) 1997 Microchip Technology Inc. Preliminary DS21210A-page 11 WORLDWIDE SALES & SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com ASIA/PACIFIC Hong Kong Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 EUROPE United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44-1628-851077 Fax: 44-1628-850259 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 India Microchip Technology India No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 Shanghai Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hongiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Singapore Microchip Technology Taiwan Singapore Branch 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122 5/8/97 Dayton Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338 Taiwan, R.O.C Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2-717-7175 Fax: 886-2-545-0139 New York Microchip Technology Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 All rights reserved. (c) 1997, Microchip Technology Incorporated, USA. 6/97 Printed on recycled paper. M Preliminary Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21210A-page 12 (c) 1997 Microchip Technology Inc. |
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