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FAST PRODUCTS
74F373 Octal transparent latch (3-State) 74F374 Octal D flip-flop (3-State)
Product specification IC15 Data Handbook 1994 Dec 05
Philips Semiconductors
Philips Semiconductors
Product specification
Latch/flip-flop
74F373 Octal transparent latch (3-State) 74F374 Octal D-type flip-flop (3-State)
FEATURES
74F373/74F374
* 8-bit transparent latch -- 74F373 * 8-bit positive edge triggered register -- 74F374 * 3-State outputs glitch free during power-up and power-down * Common 3-State output register * Independent register and 3-State buffer operation * SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) input is high. The latch remains transparent to the data input while E is high, and stores the data that is present one setup time before the high-to-low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is low, latched or transparent data appears at the output. When OE is high, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
The 74F374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. The register is fully edge triggered. The state of the D input, one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (OE) controls all eight 3-State buffers independent of the register operation. When OE is low, the data in the register appears at the outputs. When OE is high, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. TYPICAL PROPAGATION DELAY 4.5ns TYPICAL SUPPLY CURRENT (TOTAL) 35mA TYPICAL SUPPLY CURRENT (TOTAL) 55mA
TYPE 74F373
TYPE 74F374
TYPICAL fmax 165MHz
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C 20-pin plastic DIP 20-pin plastic SOL 20-pin plastic SSOP type II N74F373N, N74F374N N74F373D, N74F374D N74F373DB, N74374DB SOT146-1 SOT163-1 SOT399-1 PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0 - D7 E (74F373) OE CP (74F374) Q0 - Q7 Data inputs Enable input (active high) Output enable inputs (active low) Clock pulse input (active rising edge) 3-State outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 3.0mA/24mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state.
December 5, 1994
2
853-0369 14383
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
PIN CONFIGURATION - 74F373
OE 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10 20 VCC 19 Q7
PIN CONFIGURATION - 74F374
OE Q0 D0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
18 D7 D1 17 D6 16 Q6 Q2 15 Q5 D2 14 D5 D3 13 D4 12 Q4 GND 11 E Q3 Q1
SF00250
SF00253
LOGIC SYMBOL - 74F373
3 4 7 8 13 14 17 18
IEC/IEE SYMBOL - 74F374
3
4
7
8
13
14
17
18
D0 D1 D2 D3 D4 D5 D6 D7 11 1 E OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7 11 1 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 VCC = Pin 20 GND = Pin 10
5
6
9 12
15
16
19 VCC = Pin 20 GND = Pin 10
2
5
6
9 12
15
16
19
SF00251
SF00254
IEC/IEEE SYMBOL - 74F374 IEC/IEEE SYMBOL - 74F373
1 1 11 11 EN1 EN2 2 5 6 9 12 15 16 19 3 4 7 8 13 14 17 18 1 EN1 C2 2 5 6 9 12 15 16 19
2D
1
3 4 7 8 13 14 17 18
2D
SF00255
SF00252
December 5, 1994
3
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
LOGIC DIAGRAM FOR 74F373
D0 3 D E E 11 D1 4 D E D2 7 D E D3 8 D E D4 13 D E D5 14 D E D6 17 D E D7 18 D E
Q
Q
Q
Q
Q
Q
Q
Q
OE
1 2 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
VCC = Pin 20 GND = Pin 10
Q0
SF00256
LOGIC DIAGRAM FOR 74F374
D0 3 D CP Q CP 11 D1 4 D CP Q D2 7 D CP Q D3 8 D CP Q D4 13 D CP Q D5 14 D CP Q D6 17 D CP Q D7 18 D CP Q
OE VCC = Pin 20 GND = Pin 10
1 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
SF00257
FUNCTION TABLE FOR 74F373
INPUTS OE L L L L L H E H H L L Dn L H l h X X INTERNAL REGISTER L H L H NC NC OUTPUTS Q0 - Q7 L H L H NC Z Hold Disable outputs Latch and read register OPERATING MODE
Enable and read register
H H Dn Dn Z NOTES: H= High-voltage level h= High state must be present one setup time before the high-to-low enable transition L= Low-voltage level l= Low state must be present one setup time before the high-to-low enable transition NC= No change X= Don't care Z= High impedance "off" state = High-to-low enable transition
December 5, 1994
4
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
FUNCTION TABLE FOR 74F374
INPUTS OE L L L H CP Dn l h X X INTERNAL REGISTER L H NC NC OUTPUTS Q0 - Q7 L H NC Z Hold Disable outputs OPERATING MODE
Load and read register
H Dn Dn Z NOTES: H= High-voltage level h= High state must be present one setup time before the low-to-high clock transition L= Low-voltage level l= Low state must be present one setup time before the low-to-high clock transition NC= No change X= Don't care Z= High impedance "off" state = Low-to-high clock transition Not low-to-high clock transition =
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 48 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -3 24 +70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA
C
December 5, 1994
5
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VOH High-level High level output voltage VIH = MIN, IOH = MAX Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, high-level voltage applied Off-state output current, low-level voltage applied Short-circuit output current3 74F373 VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX VCC = MAX -60 35 10%VCC 5%VCC 10%VCC 5%VCC LIMITS MIN 2.4 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 50 -50 -150 60 TYP2 MAX UNIT V V V V V A A mA A A mA mA
VO OL VIK II IIH IIL IOZH IOZL IOS ICC
Supply current (total)
74F374 57 86 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay E to Qn Output enable time to high or low level Output disable time from high or low level Maximum clock frequency Propagation delay CP to Qn Output enable time to high or low level Output disable time from high or low level 74F374 74F373 Waveform 3 Waveform 2 Waveform 6 Waveform 7 Waveform 6 Waveform 7 Waveform 1 Waveform 1 Waveform 6 Waveform 7 Waveform 6 Waveform 7 3.0 2.0 5.0 3.0 2.0 2.0 2.0 2.0 150 3.5 3.5 2.0 2.0 2.0 2.0 TYP 5.3 3.7 9.0 4.0 5.0 5.6 4.5 3.8 165 5.0 5.0 9.0 5.3 5.3 4.3 7.5 7.5 11.0 7.5 6.0 5.5 MAX 7.0 5.0 11.5 7.0 11.0 7.5 6.5 5.0 VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 3.0 2.0 5.0 3.0 2.0 2.0 2.0 2.0 140 3.0 3.0 2.0 2.0 2.0 2.0 8.5 8.5 12.0 8.5 7.0 6.5 MAX 8.0 6.0 12.0 8.0 11.5 8.5 7.0 6.0 ns ns ns ns ns ns ns ns Tamb = 0C to +70C UNIT
December 5, 1994
6
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
AC SETUP REQUIREMENTS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu (H) tsu (L) th (H) th (L) tw (H) tsu (H) tsu (L) th (H) th (L) tw (H) tw (L) Setup time, high or low level Dn to E Hold time, high or low level Dn to E E Pulse width, high Setup time, high or low level Dn to CP Hold time, high or low level Dn to CP CP Pulse width, high or low 74F374 74F373 Waveform 4 Waveform 4 Waveform 1 Waveform 5 Waveform 5 Waveform 5 0 1.0 3.0 3.0 3.5 2.0 2.0 0 0 3.5 4.0 TYP MAX VCC = +5.0V 10% CL= 50pF, RL = 500 MIN 0 1.0 3.0 3.0 4.0 2.0 2.0 0 0 3.5 4.0 MAX ns ns ns ns ns ns Tamb = 0C to +70C UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax CP V M tw(H) tPLH Qn VM tw(L) tPHL VM VM VM
Dn
VM tPLH
VM tPHL
Qn
VM
VM
SF00260 SF00258
Waveform 3. Propagation delay for data to output
Waveform 1. Propagation delay for clock input to output, clock pulse widths, and maximum clock frequency
Dn
tw(H) E VM tPHL Qn VM VM VM tPLH VM E VM tsu(H) VM th(H) VM tsu(L) VM th(L)
VM
VM
SF00261
Waveform 4. Data setup time and hold times
SF00259
Waveform 2. Propagation delay for enable to output and enable pulse width
December 5, 1994
7
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn
VM tsu(H)
VM th(H)
VM tsu(L)
VM th(L)
OEn
VM tPZL
VM tPLZ VM VOL +0.3V
CP
VM
VM Qn, Qn
SF00262
Waveform 5. Data setup time and hold times
SF00264
Waveform 7. 3-State output enable time to low level and output disable time from low level
OEn
VM tPZH
VM tPHZ VM 0V VOH -0.3V
Qn, Qn
SF00263
Waveform 6. 3-State output enable time to high level and output disable time from high level
TEST CIRCUIT AND WAVEFORMS
SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open
PULSE GENERATOR VIN D.U.T. tTLH (tr ) RT CL RL POSITIVE PULSE 10% 90% VM tw tTHL (tf ) AMP (V) 90% VM 10% 0V VCC 7.0V 90% NEGATIVE PULSE VM 10% VOUT RL tTHL (tf ) tw VM 10% tTLH (tr ) 0V 90% AMP (V)
Test circuit for 3-state outputs DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input pulse definition INPUT PULSE REQUIREMENTS family amplitude 74F 3.0V VM 1.5V rep. rate 1MHz tw tTLH tTHL 2.5ns
SF00265
500ns 2.5ns
December 5, 1994
8
Philips Semiconductors
Product specification
Latch/flip-flop
74F373, 74F374
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1994 Dec 05
9
Philips Semiconductors
Product specification
Latch/flip-flop
74F373, 74F374
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1994 Dec 05
10
Philips Semiconductors
Product specification
Latch/flip-flop
74F373, 74F374
NOTES
1994 Dec 05
11
Philips Semiconductors FAST Products
Product specification
Latch/flip-flop
74F373, 74F374
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1994 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05119

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