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1 SPEC No. 1 E L 0 6 Xl 0 9 I S S U E: Aug. 10. 1995 To;
1
SPECIFICATIONS
Model
No.
LH1560F
%This specifications containsapages including the cover and appendix. If you have any objections,please contact us before issuing purchasing order.
CUSTOMERSACCEPTANCE DATE: BY: PRESENTED
Dept. General
Manager
REVIEWED BY:
PREPARED BY:
LOGIC TENRI SHARP
LH1560F
l Handle this document carefully for it contains material protected by international full or in part, of this material is prohibited copyright law. Any reproduction, without the express written permission of the company. OWhen using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the application areas. When using the products covered herein for the listed in Paragraph (2). even for the following application areas, Never use the to observe the precautions given in Paragraph (2). for the equipment listed in Paragraph (3). l Of-fice electronics *Instrumentation and measuring equipment *Machine tools *Audiovisual equipment *Home appliances *Communication equipment other than for trunk lines following equipment be sure products
(2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, automobiles, and other transportation equipment *Mainframe computers *Traffic control systems *Gas leak detectors and automatic cutoff devices *Rescue and security equipment *Other safety devices and safety equipment,etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, accuracy. *Aerospace equipment *Communications equipment for trunk lines *Control equipment for the nuclear power industry *Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding above three Paragraphs to a sales representative l Please direct representative all queries regarding of the company. the products covered the interpretation of the company. herein to a sales of the
or
SHARP
LH1560F
1
Contents Page
1. Summary . . . . . . . . . . . . ..*..................................
2 2
2. Features 3. Block
................................................ Diagram ........................................... of Each Block .....................
3 3 5 5
8
4. Functional 5. Pin
Operations
Configuration
.......................................
........................................ 6. Pin Descriptions - -.................... 7. Description of Functional Operations 8. precaution 9. Absolute
10. 11.
. . . . . . . . . . . . . . . . . . . . . . . . . . . ..-........-....... Maximum Ratings
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Conditions . . . . . . . . . . . . . . . . . . . . . . . . 18
Recommended Electrical
Operating Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 . . . . . . . . . . . . . . . . . . . . . . . . . 25 .......................
l
12. Example
13. Example
of System of Typical and Packing
Configuration Characteristic Specification
26 27
14. Package
***......*****.*.**...
SH4RP
LH1560F
2
1. Summary The LH1560F is a 160 output segment/common driver LSI suitable for driving large scale dot matrix LC panels using as personal computers/work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LC module. The LH1560F is good both segment driver and common driver, and a low power consuming, high-precision LC panel display can be assembled. In case of segment mode. the data input is selected 4bit parallel input mode and 8bit parallel input mode by a mode(MD) pin. In case of common mode, data input/output pins are bidirectional, four data shift directions are pin-selectable. c 2. Features (Segment mode) Shift Clock frequency : 14 MHz (Max.) (VoD=+5 V+lO%) 8 MHz (Max.) (VoD=+2.5 V-+4.5 V) 9 Adopts a data bus system 4-hit/8-bit parallel input modes are selectable with a mode (MD) pin Automatic transfer function of an enable signal Automatic counting function which, in the chip select mode, causes the internal clock to be stopped- by automatically counting 160 of input data
l l l l
(Common mode) Shift clock frequency : 4.0 MHz (Max.) Built-in 160-bits bidirectional shift register (divisible into 80-bits x2) Available in a single mode (160-bits shift register) or in a dual mode (80-bits shift register x2) Single mode 0 y, + YlSO
l l l
@ 0 @
y160 Yl YlSO
+ .+
+
YI YSO.
y6l l
n YEI YIJO -) + YlSO y1
Dual
"
mode
The above
4 shift
directions
are pin-selectable
(Both segment mode and sommon mode) Supply voltage for LC drive : +15.0 to +42.0 V Number of LC drive outputs : 160 Low output impedance Low power consumption Supply voltage for the logic system : +2.5 to +5.5 V COMS silicon gate process(P-type Silicon Substrate) Package : 186pin TCP (Tape Carrier Not designed or rated as radiation hardened
l l l l l l l l
Package)
LH1560F
3
1. Block
Diagram
160 Bits 4-Level Driver A
%60 I, Control I I I
160 Bits Level Shifter
160
f-l60 Bits Linr-*-I I=LICC "
L/R I S/C Di, Di, 1. Functional Block ctive Contra Operations Di, of Each Block DI, VOO vss vss
;P Conversion L Data Contro
bata Latch :ontrol
Function In case of segment mode, controls the selection or deselection of the chip. Following a LP signal input, and after the chip select signal is a select signal is generated internally until 160 bits of input, data have been read in. Once data input has been completed, a select signal for cascade connection is output. and the chip is deselected. In case of common mode, controls the input/output data of bidirectional pins. In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of XCK at 8-bit parallel mode into latch circuit.after that they are put on the internal data bus 8 bits at a time. the state of the data latch In case of segment mode, selects which reads in the data bus signals. The shift direction is for every 16 bits of data read controlled by the control logic, signal shifts one bit based on the state of in, the selection the control circuit.
LH1560F
4
latched cotrol
state of each LC driver logic and the data latch
output control.
pin
is controlled by the 160 bits of data are
Shift
Registe
the data latch are simultaneously latched on the falling and output to the level shifter block. the LP signal, se of common mode
edge of
control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled,160 bits of data are read in, and the chip is deselected. In case of common mode, controls the direction of data shift.
SHARP
LH1560F
5
5. Pin
Configuration
I.
6. Pin Descriptions 6-l. Pin Designations Pin No. 1 Symbol 1 to 160 1 Y,-Ylcn
161, 162, 163, 165 166 167 168 169 to 176 177 178 179 180 181 182 164,
Chip Surface
) I/O 1 Designation 1 0 1 LC drive outnut 186 VO~, V,,R Power supply for LC drive Power supply for LC drive 185 V,~L. VlZR Power supply for LC drive 184 Vd3L, v43R I Display data shift direction selection L/R V Power supply for logic system(+2.5 to +5.5 V) s"/; I Segment mode/common mode selection EI02 I/O Input/output for chip select or data of shift register 175 DIO-D18 I Display data input for segment mode I Display data input for Segment mode/ DI7 Dual mode data input XCK Display data shift clock input for segment mode .I DISPOFF I Control input for deselect output level LP I Latch pulse input/shift clock input for shift register EIO, I/O Input/output for chip select or'data of shift register FR I AC-converting signal input for LC drive waveform MD I Mode selection input Vss 183 Ground( 0 V)
LH1560F
6
6-2.
Input/Output
Circuits
Input
Signal
[Applicable pins] L/R,S/C.DIo-DIB, DISPOFF.LP,FR.MD Fig.1 Input
Circuit(l)
Input
Signal
[Applicable D17 ,XCK Fig.2 Input Circuit(2)
pins]
LH1560F
Input
Signal
Output
Signal
Control
Signal
[Applicable EIO, .EIO:! Fig.3 Input/Output Circuit
p ins]
Control
Signal
3 V43 Vss
Control
Signal
4
[Applicable
Yl to Y160
pins]
Fig.4
LC Drive
Output
Circuit
LH1560F
a
7. Description
of Functional
Operations
7-l. Pin Functions (Segment mode)
the bias -To further
voltage
used is set between externally
by a resistor the output connect
divider. waveforms of LC ViR and Vi,.
reduce the difference pins Y, and Yteo,
mode,
input
data
into
the 4 pins
DI,,-D13.
DISPOFF
FR
MD
ic voltage level to LC drive voltage level.and controls LC drive circuit. *When set to VSS level "L". the LC drive output pins (Y1-Yleo) are set to level Vss . *While set to "L",the contents of the line latch are reset.but read the display data in the data latch regardless of condition of DISPOFF. When the DISPOFF function is canceled.the driver outputs deselect level (V,, or V,,),then outputs the contents of the date latch on the next falling edge of the LP. That time,if DISPOFF removal time can not keep regulation what is shown AC characteristics (Page 2l).can not output the reading data correctly. AC signal input for LC driving waveform *The input signal is level-shifted from logic voltage level to LC drive voltage level,and controls LC drive circuit. l Normally.inputs a frame inversion signal. *The LC driver output pin's output voltage level can be set using the line latch output signal and the FR signal. Table of truth values is shown in 7-2-l. Mode selection pin *When set to Vss level "L", 4-bit parallel input mode is set. *When set to VDo level "HI', g-bit parallel input mqde is set. *The relationship between the display data and driver output pins is shown in 7-2-2.
SHARP
LHl560F
9
EIO, EIOp
yI-ylso
*When set to VDD level `H".segment mode is set. Input/Output pin for chip selection *When L/R input is at VSS level "L", EIO, is set for output, and EIO: is set for input. *When L/R input is at Voo level "H", EIO, is set for input, and EIOz is set for output. *During output. set to "H" while LP*E is "H" and after 160-bits of data have been read, set to "L" for one cycle (from falling edge to falling edge of XCK). after which it returns to "H". *During input. after the LP signal is input, the chip is selected while EI is set to "L". After 160-bits of data have been read, the chip is deselected. LC driver output pins *Corresponding directly to each bit of the data latch, one level or VSS> is selected and output. (Vo. VIZ? v43* Table of truth values is shown in 7-2-l.
r
the bias voltage used is set by a resistor divider. V~~R.V,~~ *Normally. V43L *Ensure that voltages are set such that VSSLH1560F
DISPOFF
FR
ND
DI7
s/c DI,,-DIG XCK
YI-Ylso
Control input pin for output deselect level *The input signal is level-shifted from logic voltage level to LC drive voltage level.and controls LC drive circuit. *When set to Vss level "L", the LC driver output pins (Yi-Ylso) are set to level Vss. *While set to "L",the contents of the shift resister are reset not reading data. When the DISPOFF function is canceled, the driver outputs deselect level (VIZ or Vd3), and the shift data is reading on the falling edge of the LP. That time,if DISPOFF removal time can not keep regulation what is shown AC characteristics (Page 24). the shift data is not reading correctly. AC signal input for LC driving waveform *The input signal is level-shifted from logic voltage level to LC drive voltage level.and controls LC drive circuit. .Normally. input a frame inversion signal. *The LC driver output pin's output voltage level can be set using the shift register output signal and the,FR signal. Table of truth values is shown in 7-2-l. Mode selection pin *When set Vss level "L", Single Mode operation is selected, when set level "H", Dual Mode operation is selected. to voo Dual Mode data input pin *According to the data shift direction of the data shift register, data can be input starting from the 81st bit. When the chip is used as Dual Mode, D17 will be pull-down. When the chip is used as Single Mode, DI, won't pull-down. Segment mode/common mode selection pin *When set to Vss level "L", common mode is set. Not used *Connect DIO-D16 to Vss or Voo. Avoiding floating. Not used l XCK is pull-down in common mode, so connect to Vss or open. LC driver output pins *Corresponding directly to each bit of the shift register, one level )is selected and output. (Vo, Viz. V43, or Vss Table of truth values is shown in 7-2-l.
LH1560F
11
7-2. 7-2-l.
Functional Truth
Operations Table
(Segment
Mode)
(Common Mode)
(Note]There are two kinds of power supply (logic level voltage, LC drive voltage) for LCD driver, please supply regular voltage which assigned by specification for each power pin. That time "Don't careV should be fixed to `H" or "L", avoiding floating.
LH1560F
12
7-2-2.
Relationship Mode) Parallel
between
the Display
Data and Driver
Output
pins
(Segment (a) 4-bit
node
DIo
DII
YISO
Y159
YISB
Y155
y152 Y,5,
*-.
Y 12 Y,,
I
y y 6 7 y y 4 3
L
H
Input-Output
D12
DI3
Ylse
y157
Y154
y153
y150
yl49
..
-.
ylo
Y g
y6
y 5
y2
y 1
(b)
a-bit
Parallel
Mode
I
I
I
I
I lJl7
I
I
rsn
I
..
I
rldn
1
1'48
Yl56
.. DIs
DI6
1 rl4l
y142 y143
1 r14g
y150 y151 yl52
1 Y 157
1
1yB
y 7
)
y14
Y22 y23 y2 y144 4
.. .. .. -* --
Y 15
Yl6
DI7
DIo DII
y8
yieo Y159
Y 144
y2 4
Y 156 Y 159 Y 160
y Y 6 7
Y 152
y151
Y 143
Y 23
Y 16 Y 15
(Common Mode) I MD L/R Data Transl
Here, [Note]
L:Vs5(0 "Don't
V). H:VDD(+2.5V to +5.5 V). x:Don't Care care" should be fixed to "H" or "L", avoiding
floating.
SHARP
LHl560F
13
7-2-3.
Connection
Examples
of Plural
Segment
Drivers
(a) Case of L/R=`L"
top data ' i/.; (data taking flow) YISO BY,
last
data ii,.' :;
XCK LP MD FR DIo-Dr.7 vss
(b) Case of L/R="H"
VDO
1
I I
I
IDIo-DI, FR MD -/.. LP XCK
w-2 g7 n a 4 I g
I
8 /
_.._....... i-l
. . .. . __.. _._ _._.._ ._..._..... I-
-0s 27"
n =
SE
x
-p:naY ,-cz.s 2:`:
"5:
-
L/R EIO, Y1 -y,eo ..f., `j' (data top data EIOz
-
L/R > EIOl Y* -----+Y*so
vss
L/R EI& - ___________ EI(), + YI -----+YlSO
EIOz ,./: last data
taking
flow)
LH1560F
7-2-4.
Timing
Chart
of 4-Device
cascade
Connection
of Segment
Drivers
FR
LP
l-l
l-l
XCK
J-ulnrL .-..-.-.. ....-.. ....-nnnrt ....--.- J-uln-n nJlnl-L JUULI-L..
._......._..... K II device A device B I/ device C II device D >I H L
DIo-DI7
EI (device
A)
EO (device A) EO (device B) EO (device C) (*I n: 4-bit &bit parallel para llel mode 40 mode 20
LH1560F
15
7-2-5.
Conection
Examples
for
Plural
Common Drivers
FR
! Fig.1 Single
i Mode (Shifting toward left)
I
FR DISPOFF VDD V
= I _
I1 T -I I I
vss&os, _-
I
Fig.2
Single
Mode (Sifting
toward right)
LH1560F
First1
Last1 First2
Last2
+,
T
p-Lid-&
I
I
DIl
Y 160 rLs
2 EIO, 3I
Yl
VDD
Vss DISPOFF FR
11
Fig. 3 Dual hfode (Shifting
toward left)
EIO,i=
EIOz
First
1
Fig.4
Last1 First2
La&2
Dual Mode (Shifting
toward right)
SHARP
LHl560F
17
8. Precaution OPrecaution when connecting or disconnecting the power This LSI has a high-voltage LC driver, so it may be permanently damaged by a high current which may flow if a voltage is supplied to the LC driver power supply while the logic system power supply is floating. The detail is as follows. *When connecting the power supply, connect the LC drive power after connecting the logic system power. Furthermore. when disconnecting the the logic system power after disconnecting the LC drive power, disconnect power. *We recommend-you connecting the serial resistor(50-100 Q) or fuse to the LC drive power V0 of the system as a current limitter. And set up the suitable value of the resistor in consideration of LC display grade. And when connecting the logic power supply, the logic condition of this LSI inside is insecurity. Therefore connect the LC drive power supply after resetting logic condition of this LSI inside on DISPOFF function. After that, cancel the m function after the LC drive power supply has become stable. Furthermore. when disconnecting the power, set the LC drive output pins to level Vss on DISPOFF `function. After that, disconnect the logic system power after disconnecting the LC drive power. When connecting the power supply, show the following recommend sequence.
VDD
vo
V-I
\
SHARP
LH1560F 18
9. Absolute I Parameter
Maximum
Ratings ISymbol/ Condi t
I
I IInput
voltage
IDIo-,
.XCK.LP
10. Recommended
Operating
Conditions
I
L
[Note]Ensure
ihat
I voltages
are
set
such that
VssSHARP
11. Electrical 11-l. Characteristics
LHl560F
19
DC Characteristics Mode) (Vss=O v, VDD= +2.5
(Segment
V to +5.5
V, V,,=+15.0
to +42.0
V, Ta=-20
to +85 t)
[Note] *l VDo=+5.0 *2 VDo=+5.0 The input *3 vDo=+5.0 The input *4 VoD=+5.0 The input
V, V0=+42.0 V, V. V,,=+42.0 V. data is turned v. V,,=+42.0 V. data is turned V. V0=+42.0 V. data is turned
V,=Vss fxcK=14 MHz. No-load, over by data taking fxcK=14 MHz. No-load. over by data taking fxcK=14 MHz, fLr=41.6 over by data taking
EI=Voo clock(4-bit Parallel input EI=Vss clock(4-bit parallel input kHz. fFR=80 Hz, No-load clock(4-bit parallel-input
mode) mode) mode)
LH1560F
20
(Common Mode) (Vss=O V, Voo=+2.5
V to +5.5
V. V ,,=+15.0
to +42.0
V. Ta=-20
to +85 "c)
IInput
^ .. ^
leakage
^ ^ l
I LIL
v,=vss
Input Icurrent Output
pull-down
I Ip D IRo N 1 IS - l-0
D
VI=VDD
DIo-, ,XCK,LP.L/R FR.HD.S/C.EIO, EIOz ,DISPOFF XCK.EIO, , I3102 nT
0.7 1.0
-10.0
PA
100.0 1.0 1.5
VA
resistance current
4c
el n
kS
(Stand-by
}W
*1 vDD=+5.0
VDD
*2
=+5.0
case of
V, V,,=+42. TiV, Vo=+42.0 V. fLp=41.6 kHz, l/480 duty operation. No-load
fFR=80
Hz
LH1560F
11-2.
AC Characteristics Hode 1) (vss=O V, VoD=+4.5 Parameter
(Segment
pulse width "L" pulse width Data setup time Data hold time Latch pulse YH" pulse width Shift clock rise to Latch pulse rjse. time Shift clock fall to Latch pulse fall time Latch pulse rise to IShift clock rise time Latch pulse fall to Shift pulse fall time Input signal rise time *2 Input signal fall time *2 Enable setup time DISPOFF removal time DISPOFF yL" nulse width lOutnut delay time (1) Output delay time (2) Output delay time (3)
[Note] *l Take
V to +5.5 V, V,,=+15.0 to +42.0 Symbol , Co1 edition 1 Min. t,,t,SlO ns 1 71 twclc twrau 23 1 twcKI. or-1 231 10 tos 20 tDH 23 tWLpH
tLD
V, Ta=-20 to +a5 "cl ) Typ. ) Max. 1 IJq 1 ns 1 I ns I irns ns ns ns 0 ns ns ns I
tSL
25 25 I
tLS
tLII
I t,
tf
I
25
I
I 50 50
I
ts
tSD
tWDL
1 I
1 c~=15
t
pd.2 1
21 100 1.2
1 I
1
ns ns ns ns ns
us ps !.ls
I
I
I tD
1 t pdl. 1 t vd3
DF
1
I
1 I
40
1.2 1.2
I ns I
1 I
c~=15
1 CL=15
PF pF
the cascade connection into consideration. is maximum in the case of high *2 (tCK-tNCKII -tWCKL)/2
speed
operation.
LHl560F
22
(Segment
Mode 2) (Vs s =0 V, v00=+2.5
V to +4.5
V. V0=+15.0
to +42.0
V. Ta=-20
to +85 "c)
Data setup time Data hold time Latch pulse "H" pulse Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall -time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift pulse fall time
tos t DH width
tWLPH tLD
30 I
40 51
1 I
I I
0
51 51
I ns I I ~~~ I ns ns ns
9
tSL
ns ns
tLS
t L II
I w I Ins/
[Noie] *l Take
*2
I the cascade connection into consideration. )/2 is maximum in the case of high speed operation.
1
(tCK-tWCKII-t*CKL
(Timing
characteristics
of Segment
Mode)
LP
LP
EO
(*) n :4-bit
a-bit
parallel parallel
mode 40 mode 20
FR < >
LH1560F
24
(Common Mode) vss =O v, vDo=+2.5
to +5.5
V. v0=+15.0
to +42.0
V, Ta=-20
1 2501 15 I
to +a5 t) ns ns ns ns I nsl 501 nsl 50 ns ns I
US 200 1.2 1.2
, VoD=+2.5 Data setup time Data hold time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF yL" pulse width Output delay time(l) Output delay time(2) OutDut delay time(3) tsu t&l tr tr
tSD tWDL
V-.+4.5
V
30
30 50
I
100 1.2 CL=15 pF CL=15 pF
c~=15 DF
t DL t udl* tpd2 tads
ns
us us
I
(Timing
Characteristics
of Common Mode)
tWLP <
>
G
7.
LP 4 tr
_ tWLPH _ t-t
F
EI02 01,)
tDL < z
EIO,
tWDL d
DISPOFF
FR
LP
<
t.as
>
Yl-YIGO
3:
[L/R="L"]
SHARP
LH1560F
25
12 . Example
of System
Configuration
EIO, YF C f:R DIo-DI7
SEGs4c SEGssr
-DISP
FR .Lp
OFF
-XCK
EI02-j
-@a !j $
SEC2 SEC, :: 7-v . . .... . .._.........~......................................................~...~.... ___.__..._.._... zE Y,-YISO Y,-Y160 YI-Ylso
II
II
II
k
i
I I
LHl560F
13. Example
of Typical
Characteristic Conditions C, VSS=O V, VDo=+5.0 Min. V Typ.
10
Parameter Typical Fundamental Rating Propagation Delay Time
Max.
Ta=+25
Unit ns
14. PACKAGE AND PACKING
LH 1560F SPECIFICATION
27 1
1. Package Outline Specification Refer to drawing No. SPN3321-00 2. Markings The meanings of the device code printed on each tape carrier package are as follows. (1) Date code : --- 4 3 4 a> b) a) denotes the last figure of Anno b) denotes the week (of production) c) denotes the number of times of (example) 0 c) Domini (of production) alteration
3. Packing Specifications ntt-stattc treate nti-static treate
(2) Packing Form * Specification of label a) Tape carrier package(TCP)is wound on a reel with separators 1 and 2 and the ends of them are fixed with adhesive tape. b) A label indicating production name, lot no. TYPE RODUCTION NAME and quantity is stuck on one side of the reel. c) The reel and silica gel is put in a laminated aluminium bag. Nitrogen gas is enclosed in 2UANTITY 1 QUANTITY 1 the bag and the bag is sealed. The same label(b) is affixed to the bag. The bag is put LQT(DATE)/ SHIPPING DATE 1 in a carton and the same label(b) is affixed to one side of the carton. 4. Miscellaneous (1) The length of the tape carrier is 34-46 meters maximum per reel, and depends on shipping quantity. (2) Before unpacking, prepare a work bench equipped with anti-static devices. Also, the operater shoud ware anti-static wrist bands. (3) The device, once unpacked, should be stored in a nitrogen gas, room temperature atomosphere and used within 1 week.
4
DESIGN
(NOTE)
/'
4'
,'
,'
,<----__ -'

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