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| MC54/74F373 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS The MC54/74F373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FASTTM SCHOTTKY TTL * Eight Latches in a Single Package * 3-State Outputs for Bus Interfacing * ESD > 4000 Volts CONNECTION DIAGRAM (TOP VIEW) VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 20 1 J SUFFIX CERAMIC CASE 732-03 N SUFFIX PLASTIC CASE 738-03 20 1 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND 20 LOGIC SYMBOL 3 4 7 8 13 14 17 18 1 DW SUFFIX SOIC CASE 751D-03 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 11 1 D0 D1 D2 D3 D4 D5 D6 D7 LE OE O0 O1 O2 O3 O4 O5 O6 O7 2 5 6 9 12 15 16 19 VCC = PIN 20 GND = PIN 10 GUARANTEED OPERATING RANGES Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54, 74 54 74 IOH IOL Output Current -- HIGH Output Current -- LOW 54, 74 54, 74 Min 4.5 -55 0 Typ 5.0 25 25 Max 5.5 125 70 -3.0 24 mA mA Unit V C FAST AND LS TTL DATA 4-167 MC54/74F373 FUNCTIONAL DESCRIPTION The F373 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent; i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs one setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output Enable (OE) input. When (OE) is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode, but this does not interfere with entering new data into the latches. LOGIC DIAGRAM D0 D GO LE D1 D GO D2 D GO D3 D GO D4 D GO D5 D GO D6 D GO D7 D GO OE O0 O1 O2 O3 O4 O5 O6 O7 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54, 74 74 VOL IOZH IOZL IIH Output LOW Voltage Output OFF Current -- HIGH Output OFF Current -- LOW Input HIGH Current 2.4 2.7 3.3 3.3 0.35 0.5 50 -50 20 100 IIL IOS ICCZ Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current (All Outputs OFF) -60 35 -0.6 -150 55 Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A A A A mA mA mA Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = -18 mA IOH = - 3.0 mA IOH = - 3.0 mA IOL = 24 mA VOUT = 2.7 V VOUT = 0.5 V VIN = 2.7 V VIN = 7.0 V VIN = 0.5 V VOUT = 0 V OE = 4.5 V Dn, LE = GND VCC = MIN VCC = 4.5 V VCC = 4.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-168 MC54/74F373 AC CHARACTERISTICS 54/74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Parameter Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Min 3.0 2.0 5.0 3.0 2.0 2.0 1.5 1.5 Typ 5.3 3.7 9.0 5.2 5.0 5.6 4.5 3.8 Max 7.0 5.0 11.5 7.0 11 7.5 6.5 6.0 54F TA = -55C to +125C VCC = 5.0 V 10% CL = 50 pF Min 3.0 2.0 5.0 3.0 2.0 2.0 1.5 1.5 Max 8.5 7.0 15 8.5 13.5 10 10 7.0 74F TA = 0C to +70C VCC = 5.0 V 10% CL = 50 pF Min 3.0 2.0 5.0 3.0 2.0 2.0 1.5 1.5 Max 8.0 6.0 13 8.0 12 8.5 7.5 6.0 ns ns ns Unit ns AC OPERATING REQUIREMENTS 54/74F TA = +25C VCC = +5.0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) Parameter Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH Min 2.0 2.0 3.0 3.0 6.0 Typ Max 54F TA = -55C to +125C VCC = 5.0 V 10% Min 2.0 2.0 3.0 3.0 6.0 Max 74F TA = 0C to +70C VCC = 5.0 V 10% Min 2.0 2.0 3.0 3.0 6.0 ns ns Max Unit FAST AND LS TTL DATA 4-169 |
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