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| STLVD112 HIGH SPEED PROTECTION SWITCH s s s s s 24mA CMOS OUTPUT DRIVE CURRENT LVTTL INPUT THRESHOLDS CONTROLLED SKEW BETWEEN DATA AND CLOCK SIGNALS LVDS INPUT-OUTPUT UP TO 155 MHZ IMPROVED LATCH-UP IMMUNITY UP TO 300mA DESCRIPTION The STLVD112 is a low voltage differential to LVTTL signal converter with enhanced loop-back and crosspoint features. The synchronous design allows a phase alignment between a clock and its data; this means a better BER (Bit Error Rate) performance. The advanced 0.35m technology makes the STLVD112 suitable for data rates up to 200Mbit. The main application field is SDH/SONET telecom infrastructure. The STLVD112 flexible switch architecture makes it easy to implement multiple protection schemes in STM1 access systems. Thanks to the flexible multiplexing allowed, it becomes simple to redirect the data/clock signal coming from the faulty access card to the spare card. In normal mode the STLVD112 converts the differential data levels of the LVDS and related ORDERING CODES Type STLVD112BTR STLVD112CTR Temperature Range -40 to 85 C 0 to 70 C Package TSSOP clock signal from (to) the line interface in LVTTL level signals to (from) the backpanel. In addition the switch functions prevent the equipment from line interface faults. In fact, it is possible to switch the signals coming from a different line interface to the local line interface or the signals from the local line interface to a different line interface. Comments 1000 parts per reel 1000 parts per reel TSSOP48 (Tape & Reel) TSSOP48 (Tape & Reel) April 2003 1/11 STLVD112 PIN CONFIGURATION 2/11 STLVD112 PIN DESCRIPTION PlN N 1, 6, 14, 22 2 3 4, 9, 13, 17, 21, 25, 36, 44, 48 5 7 8 10, 18, 31, 38 11 12 15 16 19 20 23 24 26, 30, 37, 43 27 28 29 32 33 34 35 39 40 41 42 45 46 47 SYMBOL VS1 CKsp_in DATAsp_in GND LOSch CKsp_out DATAsp_out VS2 CKch_in DATAch_in CKprev_in DATAprev_in CKch_out DATAch_out CKprev_out DATAprev_out N.C. Kloop_sp Kloop_I Ki DATAinB DATAinA CKinB CKinA CKoutB CKoutA DATAoutB DATAoutA LOSsp LOSi LOSprev NAME AND FUNCTION Main Power Supply LVTTL Clock Input LVTTL Data Input Ground Control Output LVTTL Clock Output LVTTL Data Output Second Power Supply LVTTL Clock Input LVTTL Data Input LVTTL Clock Input LVTTL Data Input LVTTL Clock Output LVTTL Data Output LVTTL Clock Output LVTTL Data Output Not Connected Control Input Control Input Control Input LVDS Data Input LVDS Data Input + LVDS Clock Input LVDS Clock Input + LVDS Clock Output LVDS Clock Output + LVDS Data Output LVDS Data Output + Control Output Control Input Control Input TRUTH TABLES FOR THE FIVE MUX INPUTS Ki LOW HIGH Kloop_sp X X INPUTS Ki X X Kloop_sp X X Kloop_i LOW HIGH Kloop_i X X OUTPUT DATA_out DATAch_in DATAsp_in OUTPUT DATAch_out DATAin DATAch-in 3/11 STLVD112 INPUTS Ki LOW HIGH X Kloop_sp LOW LOW HIGH INPUTS Ki X X Kloop_sp X X INPUTS Ki LOW HIGH X Kloop_sp LOW LOW HIGH Kloop_i X X X Kloop_i LOW HIGH Kloop_i X X X OUTPUT DATAsp_out DATAprev_in DATA_in DATAsp_in OUTPUT LOSch LOSi LOW OUTPUT LOSsp LOSprev LOSi LOW ABSOLUTE MAXIMUM RATINGS Symbol VS1, VS2 VS2 VI VO Iik Iok IO TL Tstg Supply Voltage Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Clamp Current DC Output Diode Clamp Current DC Output Current Lead Temperature (10sec) Storage Temperature Range Parameter Value -0.3 to 4.6 -0.3 to (VS1 + 0.3) -0.3 to (VS1 + 0.3) -0.3 to (VS1 + 0.3) 20 20 50 300 -65 to 150 Unit V V V V mA mA mA C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VS1, VS2 VS2 VI VO Top dt/dv Supply Voltage Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Maximum Input Rise and Fall Time Parameter Value 3 to 3.6 3 to (VS1 + 0.3) 0 to VS1 0 to VS1 -45 to 85 10 Unit V V V V C ns/V 4/11 STLVD112 ELECTRICAL CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol VOL VOH VIL VIH IIN ICC Parameter Low Level Output Voltage High Level Output Voltage Test Conditions Min. IOUT = 24 mA IOUT = 24 mA 0 2 -1 15 110 Typ. 0.2 VSI-0.5 VSI-0.3 0.8 VSI 1 Max. 0.4 V V V V A mA Unit Low Level Input Thresholds VOUT = 0.1V or VS1 - 0.1 High Level Input Thresholds VOUT = 0.1V or VS1 - 0.1 Input Leakage Current Quiescent Supply Current VIN = GND or VCC VIN = GND or VCC fCLOCK = 155MHz LVDS DRIVER ELECTRICAL CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol VOD VOD Parameter Differential Output Voltage Test Conditions Min. RL = 100 247 -50 1 -50 1.15 Change in differential output voltage between logic states VOC(SS) Steady-state common-mode output voltage VOC(SS) Change in steady-state commonmode output voltage between logic State VOC(PP) Peak-to-Peack common-mode output voltage Short Circuit Output Current VO(Y) or VO(Z) = 0 ISC VOD = 0 IOFF Power Off Output Current VCC = 0, VO = 2.4V -1 Typ. 364 Max. 454 50 1.30 50 mV mV V mV Unit 100 -24 -4 150 mV mA 12 1 A LVDS RECEIVER ELECTRICAL CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol VITH+ VITH|VID| VIC Parameter Positive-going Differential Input Voltage Threshold Negative-going Differential Input Voltage Threshold Magnitude of Differential Input Voltage Common-mode Input Voltage Test Conditions Min. Typ. Max. 100 -100 0.1 0.5 |VID| 0.6 2.4-0.5 |VID| VCC-1 mV mV V V Unit 5/11 STLVD112 LVDS SWITCHING TIMING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol tW Parameter Minimum Pulse Width Test Conditions Min. <1 Typ. Max. ns Unit AC LVTTL IN LVTTL OUT (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol tPLH tPHL tTLH tTHL fopr Parameter Propagation Delay Time, low-to-highlevel output (50% to 50%) Propagation Delay Time, high-to-lowlevel output (50% to 50%) Transition Time, low-to-high-level output (10% to 90%) Transition Time, high-to-low-level output (90% to 10%) Operative frequency Test Conditions Min. Measured with VIN=0 to 2.5V, fCLOCK = 1MHz, fDATA = 0.5MHz tr = tf = 0.4ns, +Duty Cycle=50% tPHL, tPLH are referred to output clock transitions. 2.4 2.5 0.7 0.7 100 Typ. 3.9 4.2 1.3 1.1 155 Max. 5.6 5.3 1.6 1.3 200 ns ns ns ns MHz Unit AC CONTROL OUTPUT (LOSsp, LOSch) (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol tPLH tPHL tTLH tTHL Parameter Propagation Delay Time, low-to-highlevel output (50% to 50%) Propagation Delay Time, high-to-lowlevel output (50% to 50%) Transition Time, low-to-high-level output (10% to 90%) Transition Time, high-to-low-level output (90% to 10%) Test Conditions Min. Measured with VIN=0 to 2.5V, fCLOCK = 1MHz, fDATA = 0.5MHz tr = tf = 0.4ns, +Duty Cycle=50% tPHL, tPLH are referred to output clock transitions. 2.4 2.4 0.9 0.7 Typ. 3.6 3.4 1.9 1.0 Max. 4.4 4.2 2.3 1.2 ns ns ns ns Unit AC LVTTL IN LVDS OUT (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol tPLH tPHL tTLH tTHL fopr Parameter Propagation Delay Time, low-to-highlevel output (50% to 50%) Propagation Delay Time, high-to-lowlevel output (50% to 50%) Transition Time, low-to-high-level output (20% to 80%) Transition Time, high-to-low-level output (80% to 20%) Operative frequency Test Conditions Min. Measured with VIN=0 to 2.5V, fCLOCK = 1MHz, fDATA = 0.5MHz tr = tf = 0.4ns, +Duty Cycle=50% tPHL, tPLH are referred to output clock transitions. 2.8 2.6 0.4 0.4 100 Typ. 3.8 3.4 0.5 0.6 155 Max. 4.7 4.1 0.6 0.7 200 ns ns ns ns MHz Unit 6/11 STLVD112 AC LVDS IN LVTTL OUT (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol tPLH tPHL tTLH tTHL fopr Parameter Propagation Delay Time, low-to-highlevel output (50% to 50%) Propagation Delay Time, high-to-lowlevel output (50% to 50%) Transition Time, low-to-high-level output (10% to 90%) Transition Time, high-to-low-level output (90% to 10%) Operative frequency Test Conditions Min. VDIFF = 400mV Measured with VICM = 1.2 V, fCLOCK = 1MHz, fDATA = 0.5MHz tr = tf = 0.4ns, +Duty Cycle=50% tPHL, tPLH are referred to output clock transitions 4.3 4.1 0.7 0.8 100 Typ. 5.6 5.4 0.9 1.0 155 Max. 6.9 6.7 1.1 1.3 200 ns ns ns ns MHz Unit LVTTL IN LVTTL OUT (VCC = 3 to 3.6V TA = -45 to 80C, unless otherwise noted. Typical values are at TA = 25C) Value Symbol ts tHSetup Time Hold Time Parameter Test Conditions Min. f = 10MHz, VICM = 1.2 V VDIFF = 400mV, VINTTL = 0 to 2.5V 1 1 Typ. Max. ns ns Unit LVTTL IN LVDS OUT (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol ts tHSetup Time Hold Time Parameter Test Conditions Min. f = 10MHz, VICM = 1.2 V VDIFF = 400mV, VINTTL = 0 to 2.5V 1 1 Typ. Max. ns ns Unit LVDS IN LVTTL OUT (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25C and VS1, VS2 = 3.3V) Value Symbol ts tHSetup Time Hold Time Parameter Test Conditions Min. f = 10MHz, VICM = 1.2 V VDIFF = 400mV, VINTTL = 0 to 2.5V 1.5 1 Typ. Max. ns ns Unit 7/11 STLVD112 LOGIC DIAGRAM 8/11 STLVD112 TSSOP48 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.50 6.0 0.5 BSC 8 0.75 0 0.020 0.17 0.09 12.4 8.1 BSC 6.2 0.236 0.0197 BSC 8 0.030 0.05 0.9 0.27 0.20 12.6 0.0067 0.0035 0.488 0.318 BSC 0.244 TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 0.496 MIN. TYP. MAX. 0.047 0.006 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7065588C 9/11 STLVD112 Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 13.1 1.5 3.9 11.9 12.8 20.2 60 30.4 8.9 13.3 1.7 4.1 12.1 0.343 0.516 0.059 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 0.524 0.067 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 10/11 STLVD112 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 11/11 |
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