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T2316160A
DRAM
FEATURES
* Industry-standard x 16 pinouts and timing functions. * Single 5V (10%) power supply. * All device pins are TTL- compatible. * 1K-cycle refresh in 16ms. * Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. * BYTE WRITE and BYTE READ access cycles.
1024K x 16 DYNAMIC RAM
FAST PAGE MODE GENERAL DESCRIPTION
The T2316160A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x16 configuration. The T2316160A has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode with Extended Data Output. The T2316160A CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL to transition low in a WRITE cycle will write data into the lower byte (DQ0~DQ7), and CASH transiting low will write data into the upper byte (DQ8~DQ15).
OPTION
TIMING MARKING 45ns -45 60ns -60 PACKAGE 42-pin SOJ J 44/50-pin TSOPII S
PIN ASSIGNMENT ( Top View )
VDD DQ0 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC
VDD DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC NC A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC CASL CASH OE A9 A8 A7 A6 A5 A4 Vss
DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 NC
NC NC WE RAS NC NC A0 A1 A2 A3 VDD
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
NC CASL CASH OE A9 A8 A7 A6 A5 A4 Vss
Taiwan Memory Technology, Inc. reserves the right P. 1 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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T2316160A
FUNCTIONAL BLOCK DIAGRAM
WE CASL CASH CONTROL LOGIC
CAS
DATA-IN BUFFER DQ0 16
. .
DQ15
NO.2 CLOCK GENERATOR DATA-OUT BUFFER 10 COLUMN DECODER
10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10
COLUMN. ADDRESS BUFFER
OE
16
1024 REFRESH CONTROLLER 16 SENSE AMPLIFIERS I/O GATING 1024x 16
REFRESH COUNTER 10 ROW DECODER ROW. ADDRESS BUFFERS(10)
10
1024
1024x 1024 x 16 MEMORY ARRAY
RAS
NO.1 CLOCK GENERATOR
Vcc Vss
PIN DESCRIPTIONS
SYM. A0-A9 RAS CASH CASL WE OE DQ0 - DQ15 Vcc Vss NC TYPE Input Input Input Input Input Input Input/ Output Supply Ground Address Input Row Address Strobe Column Address Strobe /Upper Byte Control Column Address Strobe /Lower Byte Control Write Enable Output Enable Data Input/ Output Power, 5V Ground No Connect DESCRIPTION
Taiwan Memory Technology, Inc. reserves the right P. 2 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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T2316160A
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS...... -1V to +7V Operating Temperature, Ta (ambient).. 0C to +70C Storage Temperature (plastic)........ -55C to +150C Power Dissipation ........................................... 1.2W Short Circuit Output Current........................... 50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0C Ta 70C; VCC = 5V 10 % unless otherwise noted) DESCRIPTION CONDITIONS Supply Voltage Supply Voltage Input High (Logic) voltage Input Low (Logic) voltage Input Leakage Current 0V VIN 7V Output Leakage Current 0V VOUT 7V Output(s) disabled Output High Voltage IOH = -5 mA Output Low Voltage IOL = 4.2 mA Note: 1.All Voltages referenced to Vss MAX DESCRIPTION Operating Current TTL Standby Current CONDITIONS RAS , CAS cycling , tRC = min TTL interface, RAS , SYM. Icc1 Icc2 Icc3 Icc4 Icc5 Icc6 -45 190 2.0 190 150 190 1.0 -60 170 2.0 170 130 170 1.0 UNITS NOTES mA 1,2 mA mA mA mA mA 1 2 1,3 SYM. Vcc Vss VIH VIL ILI ILO VOH VOL MIN 4.5 0 2.4 -1.0 -10 -10 2.4 0 MAX 5.5 0 Vcc+1 0.8 10 10 Vcc 0.4 UNITS V V V V uA uA V V NOTES 1 1 1
CAS =VIH, DOUT=High-Z tRC = min RAS -only refresh Current tPC = min Fast Page Mode Current t CAS Before RAS Refresh RC = min Current CMOS Standby Current CMOS interface, RAS , CAS >Vcc0.2V
Note: 1. Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Taiwan Memory Technology, Inc. reserves the right P. 3 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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T2316160A
CAPACITANCE
(Ta =25C, Vcc =5V, f = 1M HZ)
Parameter Input Capacitance (address) Input Capacitance ( RAS , CAS , WE , OE ) Output Capacitance (data-in/out) Symbol CI1 CI2 CI/O Typ Max 5 7 10 Unit pF pF pF
AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70C)
TEST CONDITIONS: Vcc=5V 10%, VIH/VIL=2.4/0.8V,VOH/VOL=2.0/0.8V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (100pF)
AC CHARACTERISTICS PARAMETER Read or Write Cycle Time Read Write Cycle Time Fast-Page-Mode Read or Write Cycle Time Fast-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time RAS to Column Address Delay Time Column Address Setup Time SYM tRC tRWC tPC tPCM tRAC tCAC tOAC tAA tACP tRAS tRASC tRSH tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC 45 45 11 28 10 40 6 10 5 0 5 8 0 34 10K -45 -60 MIN MAX MIN MAX UNIT Notes 85 110 ns 105 140 ns 26 35 ns 70 85 ns 45 60 ns 4 11 11 19 22 10K 100K 60 60 15 40 15 60 10 20 5 0 10 12 0 45 10K 15 15 30 35 10K 100K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 5 13 8
26
30
8
Taiwan Memory Technology, Inc. reserves the right P. 4 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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T2316160A
-45 -60 MIN MAX MIN MAX UNIT Notes 6 10 ns 35 45 ns 19 0 0 0 3 3 0 6 35 7 9 8 0 6 35 61 35 27 2.5 10 10 10 6 0 50 16 10 10 10 15 0 15 8 0 10 45 15 10 10 0 10 45 85 55 40 2.5 50 16 30 0 0 0 3 3 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns 6 6 15 11 11 11 2,3 10,16 16 11,14 14 14 14 14 12 12 14 9,14 9
AC CHARACTERISTICS (continued)
AC CHARACTERISTICS PARAMETER Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Read Command Setup Time Read Command Hold Time Reference to CAS Read Command Hold Time Reference to RAS CAS to Output in Low-Z Output Buffer Turn-off Delay From CAS or RAS Output Buffer Turn-off OE to Write Command Setup Time Write Command Hold Time Write Command Hold Time (Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS ) RAS to WE Delay Time Column Address to WE Delay Time CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (1024 cycles) RAS to CAS Precharge Time CAS Setup Time (CBR REFRESH) CAS Hold Time (CBR REFRESH) OE
Hold Time From
SYM tCAH tAR tRAL tRCS tRCH tRRH tCLZ tOFF1 tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tOEH tORD
WE During Read-Modify-Write Cycle
OE Setup Prior to RAS During Hidden Refresh Cycle
Taiwan Memory Technology, Inc. reserves the right P. 5 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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T2316160A
11. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycles only. If tWCS tWCS(min), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min), tAWD tAWD(min) and tCWD tCWD(min), the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE controlled) cycle. 12. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. WRITE command is defined as WE going low. 15. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 16. The I/Os open during READ cycles once tOFF1 or tOFF2 occur.
Notes: 1. An initial pause of 200us is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 2. VIH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between VIH(2.4V) and VIL(0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 5. Assume that tRCD tRCD(max) . 6. Enables on-chip refresh and address counters. 7. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, access time is controlled by tCAC. 8. Operation within the tRAD limit ensures that tRAC(max) can be met. tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, access time is controlled by tAA. 9. Either tRCH or tRRH must be satisfied for a READ cycle. 10. tOFF1(max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
Taiwan Memory Technology, Inc. reserves the right P. 6 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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CAS
TE CH
READ CYCLE
tR C tR A S tR P
T2316160A
R A S V IH V IL
tC S H tR S H tC A S tR R H
tC R P
tR C D
V IH V IL
tA R tA S R tR A D tR A H RO W tR C S tA S C tR A L tC A H C O LU M N tR C H RO W
A D D R V IH V IL W E V IH V IL
tA A tR A C tC A C tC L Z
NO TE1 tO F F 1
I/O V O H VOL O E V IH V IL
O PEN tO A C
V A L ID D A T A tO F F 2
O PEN
EARLY WRITE CYCLE
tR C tR A S tR P
RAS
V IH V IL
tC S H tR S H tC R P tR C D tC A S
C A S V IH V IL
tA R tA S R tR A D tR A H tA S C tR A L tC A H
ADDR
V IH V IL
ROW
C O LU M N tC W L tR W L tW C R
tW C S tW C H tW P
RO W
WE
V IH V IL
tD S tD H R tD H
I/O
V IO H V IO L V IH V IL
V A L ID D A T A
OE
DON'T CARE UNDEFINED
Note: tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. Taiwan Memory Technology, Inc. reserves the right P.7 to change products or specifications without notice. Publication Date:APR. 2002 Revision:A
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READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
tR W C tR A S tR P
T2316160A
R A S V IH V IL
tC S H tR S H tC A S
tC R P
tR C D
V C A S V IH IL
tA R tR A D tR A H tR A L tC A H
tA S R
tA S C
A D D R V IH V IL
RO W
C O LU M N
tR C S tR W D tC W D tA W D tC W L tR W L tW P
RO W
W E V IH V IL
tA A tR A C tC A C tC L Z tD S
V A L ID D
tD H
V IO H I/O V IO L V O E V IH IL
O PEN
tO A C
OUT tO F F 2
V A L ID D IN
tO E H
O PEN
FAST-PAGE-MODE READ CYCLE
t RASC tRP
RAS VIH VIL
tCSH tCRP tRCD tCAS tPC tCP tRSH tCAS tCP tCAS tCPN
V CAS IH VIL
tAR tRAD tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRAL
ADDR VIH VIL
ROW
tRCS
COLUMN
COLUMN
COLUMN
tRCH
ROW
tRRH
WE VIH VIL
t AA tRAC tCAC tCLZ tOFF1 tCLZ t AA tACP tCAC tOFF1 tCLZ t AA tACP tCAC tOFF1
I/O
VOH VOL
OP E N
tOAC
VAL ID DAT A
tOFF2 tOAC
VALID DATA
tOFF2 tOAC
VAL ID DAT A
tOFF2
OP E N
V OE VIH IL
DON'T CARE UNDEF INED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the tPC specification. Taiwan Memory Technology, Inc. reserves the right P.8 to change products or specifications without notice. Publication Date:APR. 2002 Revision:A
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FAST-PAGE-MODE EARLY-WRITE CYCLE
t RASC
T2316160A
RAS
V IH V IL
tC S H tC R P tR C D tC A S tP C tC P tC A S tC P tR S H tC A S tC P N
CAS
V IH V IL
tA R tR A D tA S R tR A H tA S C tC A H tA S C tC A H tA S C tR A L tC A H
ADDR
V IH V IL
RO W
C O LU M N
tW C S tC W L tW C H tW P
C O LU M N tC W L tW C S tW C H tW P
C O LU M N tC W L tW C S tW C H tW P
ROW
WE
V IH V IL
tW C R tD H R tD S tD H tD S tD H tD S tR W L tD H
I/O
V IO H V IO L V IH V IL
V A L ID D A T A
V A L ID D A T A
V A L ID D A T A
OE
FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t RA SC tR P
R A S V IH V IL
tC S H tC R P tR C D tC A S tC P tP C M tC A S tC P tR S H tC A S tC P N
CAS
V IH V IL
tA R tR A D tA S R tR A H tA S C tC A H tA S C tC A H tA S C tR A L tC A H
A D D R V IH V IL
RO W
C O LU M N tR W D
tR C S tC W L tW P tA W D tC W D
C O LU M N
C O LU M N
ROW
tR W L tC W L tW P
tC W L tW P tA W D tC W D tA W D tC W D
W E V IH V IL
tA A tR A C tC A C tC L Z tD H tD S tA A tA C P tC A C tC L Z
VALID D O UT VALID D IN VALID D O UT VALID DIN
tA A tD H tD S tA C P tC A C tC L Z
VALID D O UT VALID DIN
tD H tD S
I/O V IO H V IO L
O PEN
O PEN
tO F F 2 tO A C tO A C
tO F F 2 tO A C
tO F F 2 tO E H
OE
V IH V IL
DO N'T CARE UNDEF INED
Note: tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification. Taiwan Memory Technology, Inc. reserves the right P. 9 to change products or specifications without notice. Publication Date: APR. 2002 Revision:A
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V RA S VIH IL
TE CH
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
tRASC
T2316160A
tRP
tCSH t CRP tRCD tPC tCAS tPC tCP tCAS tCP t RSH t CAS tCP
V CA S VIH IL
tAR t RAD tASR t RAH t ASC tCAH tASC t CAH t ASC tCAH tRAL
V AD DR VIH IL
ROW
COLUMN(A)
tRCS
COLUMN(B)
t RCH
COLUMN(N)
tW CS tWCH
ROW
WE
VIH VIL
t AA tRAC t CAC tOFF1 tACP
t AA t CAC tCLZ tOFF1 tDS tDH
V I / O VIOH IOL
OP E N
t OAC
VALID DATA (A)
VALID DATA (B)
NOTE1
VALID DATA IN
V OE VIH IL
RAS ONLY REFRESH CYCLE (ADDR=A0-A9; OE , WE =DON`T CARE)
tR C tR A S tR P
R A S V IH V IL
tC R P tR P C
C A S V IH V IL
tA S R tR A H
A D D R V IH V IL I/O V O H VOL
RO W
ROW
O PEN
DON'T CARE UNDEFINED
Note1:Do not drive data prior to tristate.
Taiwan Memory Technology, Inc. reserves the right P. 10 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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RAS
TE CH
CBR REFRESH CYCLE (A0-A9; OE =DON`T CARE)
T2316160A
tR P
tR A S
tR P
tR A S
V IH V IL
tR P C tC P N tC S R tC H R tR P C tC S R tC H R
C A S H ,C A S L V IH V IL I/O W E V IH V IL
O PEN
HIDDEN REFRESH CYCLE ( WE =HIGH; OE =LOW)
(R E A D ) tR A S tR P (R E F R E S H ) tR A S
R A S V IH V IL
tC R P tR C D tR S H tC H R
C A S V IH V IL
tA R tR A D tA S R tR A H ROW tA S C tR A L tC A H
A D D R V IH V IL
C O LU M N tA A tR A C tC A C tC L Z N O TE1 tO F F 1
I/O
VOH VOL
O PEN tO A C
V A L ID D A T A tO F F 2
O PEN
O E V IH V IL
tO R D
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
Taiwan Memory Technology, Inc. reserves the right P. 11 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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TE CH
T2316160A
PACKAGE DIMENSIONS 42-LEAD SOJ DRAM (400 mil)
SYMBOL A A1 A2 B b c D E e E1 L y
DIMENSIONS IN INCHES 0.128~0.148 0.025(MIN) 0.105~0.115 0.026~0.032 0.015~0.020 0.007~0.013 1.070~1.080 0.395~0.405 0.050 0.435~0.445 0.082(MIN) 0.004(MAX)
DIMENSIONS IN MM 3.251~3.759 0.635(MIN) 2.657~2.920 0.660~0.813 0.381~0.508 0.178~0.330 27.178~27.432 10.033~10.287 1.270 11.049~11.303 2.083(MIN) 0.102(MAX)
Taiwan Memory Technology, Inc. reserves the right P. 12 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A
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TE CH
T2316160A
PACKAGE DIMENSIONS 44/50L LEAD TSOPII DRAM (400 mil)
"A"
SYMBOL A A1 A2 b c D E e E1 L L1
DIMENSIONS IN INCHES 0.047 0.002~0.006 0.037~0.041 0.012~0.018 0.005~0.008 0.820~0.830 0.455~0.471 0.031 0.395~0.405 0.016~0.024 0.031 0~5
DIMENSIONS IN MM 1.200(MAX) 0.050~0.150 0.950~1.050 0.300~0.450 0.120~0.210 20.820~21.080 11.560~11.960 0.800 10.030~10.290 0.400~0.600 0.800 0~5
Taiwan Memory Technology, Inc. reserves the right P. 13 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:A

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