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Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
FEATURES
* 12 LVCMOS / LVTTL outputs * LVCMOS / LVTTL clock input * Maximum output frequency: 250MHz * Output skew: 150ps (maximum) * Operating supply modes: Core/Output 3.3V/3.3V, 2.5V/2.5V, 1.8V/1.8V, 3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V * 0C to 85C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8312 is a low skew, 1-to-12 LVCMOS / LVTTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The ICS8312 single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The ICS8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply modes. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the ICS8312 ideal for high performance, single ended applications that also require a limited output voltage.
BLOCK DIAGRAM
PIN ASSIGNMENT
GND GND VDDO VDDO Q0 Q1 Q2 Q3
CLK_EN
nD Q LE 12 GND VDD Q0:Q11 CLK_EN CLK GND OE VDD GND 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 Q4 VDDO Q5 GND Q6 VDDO Q7 GND
CLK
ICS8312
21 20 19 18 17
OE
9 10 11 12 13 14 15 16
Q11 VDDO Q10 GND Q9 VDDO Q8 GND
32-Lead LQFP 7mm x 7mm x 1.4mm body package Y Pacakge Top View
8312AY
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1
REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
Type Power Power Input Input Input Description Power supply ground. Core supply pins. Synchronous control for enabling and disabling clock outputs. Pullup LVCMOS / LVTTL interface levels. Pulldown Clock input. LVCMOS / LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q11. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 5, 8, 12, 16, 17, 21, 25, 29 2, 7 3 4 6 Name GND VDD CLK_EN CLK OE
9, 11, 13, 15, Q11, Q10, Q9, Q8, 18, 20, 22, Q7, Q6, Q5, Output Q0 thru Q11 outputs. LVCMOS / LVTTL interface levels. 24, 26, 28, Q4, Q3, Q2, 30, 32 Q1, Q0 10, 14, 19, VDDO Power Output supply pins. 23, 27, 31 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor VDDO = 3.3V 5% Output Impedance VDDO = 2.5V 5% VDDO = 1.8V 0.2V VDDO = 3.465V VDDO = 2.625V VDDO = 2V 51 51 7 7 10 Test Conditions Minimum Typical 4 19 18 16 Maximum Units pF pF pF pF K K
TABLE 3A. OUTPUT ENABLE
Control Inputs OE 0 1 1
AND
CLOCK ENABLE FUNCTION TABLE
Output Q0:Q11 Hi-Z LOW Follows CLK input
CLK_EN X 0 1
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs OE 1 1
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Outputs CLK 0 1 Q0:Q11 LOW HIGH
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REV. C JUNE 14, 2004
CLK_EN 1 1
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 10 10 Units V V A A
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 85C
Symbol VDD VDDO IDD IDDO Symbol VDD VDDO IDD IDDO
Symbol VDD VDDO IDD IDDO
Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current
Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current
Test Conditions
Minimum 2.375 2.375
Typical 2.5 2.5
Maximum 2.625 2.625 10 10
Units V V A A Units V V A A
Units V V A A
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 85C
Test Conditions Minimum 1.6 1.6 Typical 1.8 1.8 Maximum 2.0 2.0 10 10
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 10 10
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 85C
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol VDD VDDO IDD IDDO Symbol VDD VDDO IDD IDDO
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Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current
Test Conditions
Minimum 3.135 1.6
Typical 3.3 1.8
Maximum 3.465 2.0 10 10
Units V V A A Units V V A A
TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Test Conditions Minimum 2.375 1.6 Typical 2.5 1.8 Maximum 2.625 2.0 10 10
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3
REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions VDD = 3.3V 5% CLK VDD = 2.5V 5% VDD = 1.8V 0.2V VDD = 3.3V 5% CLK_EN, OE VDD = 2.5V 5% VDD = 1.8V 0.2V VDD = 3.3V 5% CLK VDD = 2.5V 5% VDD = 1.8V 0.2V VDD = 3.3V 5% CLK_EN, OE VDD = 2.5V 5% VDD = 1.8V 0.2V VDD = 3.3V 5% CLK VDD = 2.5V 5% VDD = 1.8V 0.2V VDD = 3.3V 5% CLK_EN, OE VDD = 2.5V 5% VDD = 1.8V 0.2V VDD = 3.3V 5% CLK VDD = 2.5V 5% VDD = 1.8V 0.2V VDD = 3.3V 5% CLK_EN, OE VDD = 2.5V 5% VDD = 1.8V 0.2V VDDO = 3.3V 5%; NOTE 1 VDDO = 2.5V 5%; IOH = -1mA -5 -5 -5 -150 -150 -150 2.6 2 1.8 VDD - 0.2 VDD - 0.3 0.5 0.4 0.45 0.2 0.35 Minimum 2 1.7 0.65*VDD 2 1.7 0.65*VDD -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 1.3 0.7 0.35*VDD 1.3 0.7 0.35*VDD 150 150 150 5 5 5 Units V V V V V V V V V V V V A A A A A A A A A A A A V V V V V V V V V V
TABLE 4F. LVCMOS DC CHARACTERISTICS, TA = 0C TO 85C
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; IOH = -100uA VDDO = 1.8V 0.2V; NOTE 1 VDDO = 3.3V 5%; NOTE 1 VDDO = 2.5V 5%; IOL = 1mA
VOL
Output Low Voltage
VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; IOL = 100uA VDDO = 1.8V 0.2V; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
8312AY
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REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions f 250MHz Minimum Typical Maximum Units 250 1.2 1.9 2.5 125 800 20% to 80% f 200MHz 200 45 700 55 MHz ns ps ps ps %
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay Low to High; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Rise Time; NOTE 4 Output Duty Cycle
tsk(o) tsk(pp)
tR/tF odc
All parameters measured at fMAX unless noted otherwise. See Table 5C listed below for Notes 1 through 5.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay Low to High; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Rise Time; NOTE 4 Output Duty Cycle 20% to 80% f 150MHz 200 45 f 250MHz 1.4 2.3 Test Conditions Minimum Typical Maximum Units 250 3.2 150 1.1 700 55 MHz ns ps ns ps %
tsk(o) tsk(pp)
tR/tF odc
All parameters measured at fMAX unless noted otherwise. See Table 5C listed below for Notes 1 through
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay Low to High; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Rise Time; NOTE 4 Output Duty Cycle 20% to 80% f 100MHz 200 45 f 200MHz 1.6 3.3 Test Conditions Minimum Typical Maximum Units 200 4.8 140 2.3 800 55 MHz ns ps ns ps %
tsk(o) tsk(pp)
tR/tF odc
All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8312AY
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5
REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions f 250MHz Minimum Typical Maximum Units 250 1.4 2.1 2.7 135 900 20% to 80% f 150MHz 200 45 700 55 MHz ns ps ps ps %
TABLE 5D. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay Low to High; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Rise Time; NOTE 4 Output Duty Cycle
tsk(o) tsk(pp)
tR/tF odc
All parameters measured at fMAX unless noted otherwise. See Table 5F listed below for Notes 1 through 5.
TABLE 5E. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay Low to High; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Rise Time; NOTE 4 Output Duty Cycle 20% to 80% f 100MHz 200 45 f 200MHz 1.4 2.4 Test Conditions Minimum Typical Maximum Units 200 3.4 145 1.3 700 55 MHz ns ps ns ps %
tsk(o) tsk(pp)
tR/tF odc
All parameters measured at fMAX unless noted otherwise. See Table 5F listed below for Notes 1 through
TABLE 5F. AC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 85C
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay Low to High; NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Output Rise Time; NOTE 4 Output Duty Cycle 20% to 80% f 100MHz 200 45 f 200MHz 1.5 2.6 Test Conditions Minimum Typical Maximum Units 200 3.7 150 1.5 700 55 MHz ns ps ns ps %
tsk(o) tsk(pp)
tR/tF odc
All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8312AY
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6
REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.165V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
0.9V 0.1V
2.05V5%
1.25V5%
VDD, VDDO
SCOPE
Qx
VDD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-0.9V 0.1V
-1.25V5%
1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.40.9V 0.9V0.1V
2.05V5% 0.9V0.1V
V DD VDDO
SCOPE
Qx
V DD VDDO
SCOPE
Qx
LVCMOS
LVCMOS
GND
GND
-0.9V0.1V
-0.9V0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
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2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
REV. C JUNE 14, 2004
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Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
V
DDO
Part 1 Qx
V
DDO
Qx
2
2
V
DDO
Part 2 Qy
V
DDO
Qy
2 tsk(o)
2 tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
80% 20%
tR
80%
CLK
VDD 2
Clock Outputs
20% tF
Q0:Q11
t
PD
VDDO 2
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
V
DDO
Q0:Q11
Pulse Width t
2
PERIOD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PLUSE WIDTH/PERIOD
8312AY
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8
REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0 200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
67.8C/W 47.9C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8312 is: 339
8312AY
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REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead Free" LQFP 32 Lead "Lead Free" LQFP on Tape and Reel Count 250 per tray 1000 250 per tray 1000 Temperature 0C to 85C 0C to 85C 0C to 85C 0C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8312AY ICS8312AYT ICS8312AYLF ICS8312AYLFT Marking ICS8312AY ICS8312AY ICS8312AYLF ICS8312AYLF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8312AY
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REV. C JUNE 14, 2004
Integrated Circuit Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Pin Characteristics table - added categor y CPD. Power Supply tables - changed IDD & IDDO max. current spec to 10A and removed typical value. Features section - corrected Output Skew typo error from 160ps to 150ps. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Added Lead Free Par t Number to Ordering Information table. Date 2/25/03
Rev B
Table T2 T4A - T4F
Page 2 3 1
C C
T2 T8
2 11
5/17/04 6/14/04
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REV. C JUNE 14, 2004

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