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Ordering number: EN3202A
LC8991 NTSC CCD 1H Delay Line
Overview
The Sanyo LC8991 is a 1H delay line for NTSC television systems.
. Sample-and-hold circuit
Package Dimensions
unit : mm
Features
3001B-DIP8
[LC8991]
. Single 9 V power supply . Low clock input voltage . 1H delay signal can be obtained with low-pass filter and clock input . 7.16 MHz number of external components required because Minimum .
timing generator, driver, bias generator and output amplifier are built in 8-pin DIP (Small package)
Functions
. 453 stages CCD shift register . CCD drive circuit . Auto-bias circuit . Sync tip clamp circuit
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max Pd max Topr Tstg Conditions Ratings 11 500 -10 to +60 -55 to +125
SANYO : DIP8
Unit V mW C C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
13097HA(II)/N090JN, JK/8290TA No.3202-1/4
LC8991
Electrical Characteristics
Parameter Symbol Conditions DC Characteristics at Ta = 25C, VDD = 9 V, CLOCK = 7.15909 MHz; 0.3 Vp-p Supply voltage VDD Supply current IDD VGG OUT VOB DC output voltage VID IN CLK COMP AC Characteristics at Ta = 25C, VDD = 9 V, CLOCK = 7.15909 MHz ; 0.3 Vp-p Maximum input voltage VIN max Voltage gain VG Input : 15 kHz, 0.5 Vp-p L6 b/a, Note 1 Linearity L2 c/a, Note 1 LS d/a, Note 1 Frequency response Gf Note 2 Noise VNO 3.4 MHz bandwidth Clock input voltage Eck Output impedance ZO Delay time tO min 8.5 typ 9.0 16.5 13.5 3.1 4.5 2.8 2.0 2.7 0.5 9 60 20 40 -2.3 1.1 0.3 520 63.42 max 9.5 20.0 Unit V mA V V V V V V Vp-p dB % % % dB mVrms Vp-p s
6 56 18 37 -3.0 0.1
0.7 11 64 22 43
1.0
Note 1) Linearity test Input: 5 step staircase signal
Note 2) Frequency response test Input = 0.5 Vp-p sine wave (2.4 MHz)/(20 kHz)
Pin Assignment
Pin Description
Pin No. 1 2 3 4 5 6 7 8 Symbol VDD VSS VGG OUT VOB VID IN CLK COMP Power supply GND VGG voltage output Delay signal output Feedback output Signal input Clock input Duty cycle compensation output Function
No.3202-2/4
LC8991
Block Diagram
VGG VGG voltage generator
Input signal
Sync tip clamp
CCD 453 stages
Delay output signal
Auto-bias circuit
Clock driver
Duty cycle detector
Wave shaper
sine wave
Sample Application Circuit
Delay output
No.3202-3/4
LC8991
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1997. Specifications and information herein are subject to change without notice.
No.3202-4/4

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