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INTEGRATED CIRCUITS
DATA SHEET
UDA1340 Low-voltage low-power stereo audio CODEC with DSP features
Preliminary specification Supersedes data of 1997 May 20 File under Integrated Circuits, IC01 1997 Jul 09
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
FEATURES General * Low power consumption * 3.0 V power supply * 256, 384 and 512fs system clock * Small package size (SSOP28) * ADC plus integrated high pass filter to cancel DC offset * Overload detector for easy record level control * Separate power control for ADC and DAC * Integrated digital filter plus DAC * No analog post filter required for DAC * Easy application * Functions controllable by microcontroller interface. Multiple format input interface * I2S-bus, MSB-justified and LSB-justified format compatible * 1fs input and output format data rate. DAC digital sound processing * Digital volume control * Digital tone control, bass boost and treble * dB-linear volume and tone control (low microcontroller load) * Digital de-emphasis for 32, 44.1 and 48 kHz fs * Soft mute. Advanced audio configuration * Stereo single-ended input configuration * Stereo line output (under microcontroller volume control) * Power-down click prevention circuitry * High linearity, dynamic range, low distortion. ORDERING INFORMATION TYPE NUMBER UDA1340M PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm GENERAL DESCRIPTION
UDA1340
The UDA1340 is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. The UDA1340 supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB justified serial data format with word lengths of 16, 18 and 20 bits. The UDA1340 has special sound processing features in playback mode, de-emphasis, volume, bass boost, treble, and soft mute, which can be controlled via the microcontroller interface.
VERSION SOT341-1
1997 Jul 09
2
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
QUICK REFERENCE DATA SYMBOL Supply VDDA(ADC) VDDA(DAC) VDDO VDDD IDDA(ADC) IDDA(DAC) IDDO IDDD IPD(ADC) IPD(DAC) Tamb VI(rms) (THD + N)/S S/N cs Vo(rms) (THD + N)/S S/N cs PADDA PDA PAD PPD ADC analog supply voltage DAC analog supply voltage operational amplifiers supply voltage digital supply voltage ADC supply current DAC supply current operational amplifier supply current digital supply current digital ADC power-down supply current digital DAC power-down supply current operating ambient temperature 2.7 2.7 2.7 2.7 - - - - - - -20 - at 0 dB at -60 dB; A-weighted Vi = 0 V; A-weighted - - - - - at 0 dB at -60 dB; A-weighted code = 0; A weighted - - - - - - - - 3.0 3.0 3.0 3.0 4.5 3.5 4 6 3 3 - PARAMETER CONDITIONS MIN. TYP.
UDA1340
MAX.
UNIT
3.6 3.6 3.6 3.6 - - - - - - +85 - -80 -30 - - - -80 - - - - - - -
V V V V mA mA mA mA mA mA
C
Analog-to-digital converter input voltage (RMS value) total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio channel separation 0.8 -85 -35 95 100 V dB dBA dBA dB
Digital-to-analog converter output voltage (RMS value) total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio channel separation 0.8 -85 -35 100 100 V dB dBA dBA dB
Power performance power consumption in record and playback mode power consumption in playback only mode power consumption in record only mode power consumption in power-down mode 54 33 27 6 mW mW mW mW
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
BLOCK DIAGRAM
UDA1340
handbook, full pagewidth
VDDA(ADC) VSSA(ADC) 2 1
VADCP 7
VADCN 6
Vref(A) 4
VINL
3
5
VINR
ADC
ADC 8 TEST1 TEST2 TEST3
VDDD VSSD
10 11
UDA1340
DECIMATION FILTER
21 20
DC-CANCELLATION FILTER 18 16 17 19 DIGITAL INTERFACE L3-BUS INTERFACE 13 14 15 12
DATAO BCK WS DATAI
L3MODE L3CLOCK L3DATA SYSCLK
OVERFL
9
DSP FEATURES
INTERPOLATION FILTER
NOISE SHAPER
DAC
DAC
VOUTL
26
24
VOUTR
25 VDDO
27 VSSO
23 VDDA(DAC)
22 VSSA(DAC)
28 Vref(D)
MGG839
Fig.1 Block diagram.
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
PINNING SYMBOL VSSA(ADC) VDDA(ADC) VINL Vref(A) VINR VADCN VADCP TEST1 OVERFL VDDD VSSD SYSCLK L3MODE L3CLOCK L3DATA BCK WS DATAO DATAI TEST3 TEST2 VSSA(DAC) VDDA(DAC) VOUTR VDDO VOUTL VSSO Vref(D) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Description ADC analog ground ADC analog supply voltage ADC input left ADC reference voltage ADC input right ADC negative reference voltage ADC positive reference voltage test control 1 (pull-down) overload flag output digital supply voltage digital ground system clock 256, 384 or 512fs L3-bus mode input L3-bus clock input L3-bus data input bit clock input word selection input data output data input test output test control 2 (pull-down) DAC analog ground DAC analog supply voltage DAC output right operational amplifier supply voltage DAC output left operational amplifier ground DAC reference voltage
MGG838
UDA1340
handbook, halfpage
VSSA(ADC) 1 VDDA(ADC) 2 VINL 3 Vref(A) 4 VINR 5 VADCN 6 VADCP 7 TEST1 8 OVERFL 9 VDDD 10 VSSD 11 SYSCLK 12 L3MODE 13 L3CLOCK 14
28 Vref(D) 27 VSSO 26 VOUTL 25 VDDO 24 VOUTR 23 VDDA(DAC)
UDA1340
22 VSSA(DAC) 21 TEST2 20 TEST3 19 DATAI 18 DATAO 17 WS 16 BCK 15 L3DATA
Fig.2 Pin configuration.
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
FUNCTIONAL DESCRIPTION System clock The UDA1340 accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable. The options are 256fs, 384fs and 512fs. The system clock must be locked in frequency to the digital interface input signals. Multiple format input/output interface The UDA1340 supports the following data input/output formats: * I2S-bus with data word length of up to 20 bits * MSB justified serial format with data word length of up to 20 bits * LSB justified serial format with data word lengths of 16, 18 or 20 bits. The formats are illustrated in Fig.3. Left and right data-channel words are time multiplexed. Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1340 consists of two third-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The over-sampling ratio is 128. Decimation filter (ADC) The decimation from 128fs is performed in two stages. sin x The first stage realizes 3rd-order ----------- characteristic. This x filter decreases the sample rate by 16. The second stage, an FIR filter, consists of 3 half-band filters, each decimating by a factor of 2. Table 1 Decimation filter characteristics CONDITION 0 - 0.45fs >0.55fs 0 - 0.45fs overall VALUE (dB) 0.05 -60 108 -1.16 Overload detection (ADC) DC cancellation filter (ADC)
UDA1340
An optional IIR high-pass filter is provided to remove unwanted DC components. The operation is selected by the microcontroller via the L3-bus. The filter characteristics are given in Table 2. Table 2 DC cancellation filter characteristics CONDITION VALUE (dB) none 0 at 0.00045fs at 0.00000036fs 0 - 0.45fs 0.031 >40 >110
ITEM Passband ripple Passband gain Droop Attenuation at DC Dynamic range Mute (ADC)
On recovery from power-down or switching on of the system clock, the serial data output DATAO is held LOW until valid data is available from the decimation filter. This time depends on whether the DC cancellation filter is selected: 1024 DC cancel off: time = ------------ , t = 23.2 ms when fs fs = 44.1 kHz 12288 DC cancel on: time = --------------- , t = 279 ms when fs fs = 44.1 kHz
ITEM Passband Ripple Stop band Dynamic range Gain
In practice the output is used to indicate whenever the output data, in either the left or right channel, is greater than -1 dB (actual figure is -1.16 dB) of the maximum possible digital swing. When this condition is detected the OVERFL output is forced HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement.
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
Interpolation filter (DAC) The digital filter interpolates from 1fs to 128fs by means of a cascade of a recursive filter and an FIR filter. Table 3 Interpolation filter characteristics ITEM Passband ripple Stop band Dynamic range Gain Noise shaper (DAC) The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. CONDITION 0 - 0.45fs >0.55fs 0 - 0.45fs DC VALUE (dB) 0.03 -50 108 -3.5 The Filter Stream DAC (FSDAC)
UDA1340
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.
1997 Jul 09
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WS RIGHT >=8 1 2 3 >=8
LEFT
dbook, full pagewidth
1997 Jul 09
LSB MSB INPUT FORMAT I2S-BUS B2 LSB MSB RIGHT >=8 1 2 3 >=8 LSB MSB MSB-JUSTIFIED FORMAT B2 LSB MSB B2 LEFT 16 16 15 2 1 15 RIGHT 2 1
1
2
3
BCK
Philips Semiconductors
DATA
MSB
B2
WS
LEFT
1
2
3
BCK
DATA
MSB
B2
WS
Low-voltage low-power stereo audio CODEC with DSP features
BCK MSB LSB-JUSTIFIED FORMAT 16 BITS B2 B15 LSB MSB B2 B15 LSB
DATA
8
LEFT 18 17 16 15 2 1 18 RIGHT 17 16 15 2 1 MSB LSB-JUSTIFIED FORMAT 18 BITS B2 B3 B4 B17 LSB MSB B2 B3 B4 B17 LSB LEFT 18 17 16 15 2 1 20 19 18 RIGHT 17 16 15 2 1 B3 B4 B5 B6 B19 LSB MSB B2 B3 B4 B5 B6 B19 LSB
MGG841
WS
BCK
DATA
WS
20
19
BCK
DATA
MSB
B2
LSB-JUSTIFIED FORMAT 20 BITS
Preliminary specification
UDA1340
Fig.3 Serial interface formats.
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
L3-Interface The UDA1340 has a microcontroller input mode. In the microcontroller mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: * System clock frequency * Data input format * Power control * DC-filtering * De-emphasis * Volume * Flat/min/max switch * Bass boost * Treble * Mute. The exchange of data and control information between the microcontroller and the UDA1340 is accomplished through a serial hardware interface comprising the following pins: L3DATA: microcontroller interface data line L3MODE: microcontroller interface mode line L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is organized in accordance with the so called `L3' format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 5). The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer for the UDA1340 can only be in one direction, input to the UDA1340 to program its sound processing and other functional features. Address mode The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.4. Data bits 0 to 1 indicate the type of subsequent data transfer as given in Table 4. Data transfer mode Table 4 BIT 1 0 Selection of data transfer BIT 0 0
UDA1340
TRANSFER DATA (volume, bass boost, treble, de-emphasis, mute, mode and power control) not used STATUS (system clock frequency, data input format and DC-filter) not used
0 1 1
1 0 1
Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1340 is 000101 (bit 7 to bit 2). In the event that the UDA1340 receives a different address, it will deselect its microcontroller interface logic.
The selection preformed in the address mode remains active during subsequent data transfers, until the UDA1340 receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.4. The maximum input clock and data rate is 64fs. All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1340 after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.6. PROGRAMMING THE SOUND PROCESSING AND OTHER
FEATURES
The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode, BIT 1 and BIT 0 (see Table 4). The second selection is performed by the 2 MSBs of the data byte (BIT 7 and BIT 6). The other bits in the data byte (BIT 5 to BIT 0) is the value that is placed in the selected registers. When the data transfer of type `data' is selected, the features VOLUME, BASS BOOST, TREBLE, DE-EMPHASIS, MUTE, MODE and POWER CONTROL can be controlled. When the data transfer of type `status' is selected, the features SYSTEM CLOCK FREQUENCY, DATA INPUT FORMAT and DC-FILTER can be controlled.
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1340
handbook, full pagewidth
L3MODE t h;MA tLC t s;MA L3CLOCK tHC t h;MA t s;MA
Tcy t s;DAT t h;DAT
L3DATA
BIT 0
BIT 7
MGD016
Fig.4 Timing address mode.
handbook, full pagewidth
thalt
thalt
L3MODE tLC t s;MT tHC Tcy t h;MT
L3CLOCK
t h;DAT
t s;DAT
t h;DAT
L3DATA write
BIT 0
BIT 7
MGD017
Fig.5 Timing for data transfer mode.
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1340
handbook, full pagewidth
thalt
L3MODE
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGD018
Fig.6 Multibyte transfer.
Table 5 BIT 7 0
Data transfer of type `status'; note 1 BIT 6 X BIT 5 SC1 BIT 4 SC0 BIT 3 IF2 BIT 2 IF1 BIT 1 IF0 BIT 0 DC REGISTER SELECTED System Clock frequency (1 : 0) data Input Format (2 : 0) DC-filter not used
1 Note
X
X
X
X
X
X
X
1. X = don't care. Table 6 BIT 7 0 0 1 Data transfer of type `data'; note 1 BIT 6 0 1 0 BIT 5 VC5 BB3 X BIT 4 VC4 BB2 DE1 BIT 3 VC3 BB1 DE0 BIT 2 VC2 BB0 MT BIT 1 VC1 TR1 M1 BIT 0 VC0 TR0 M0 REGISTER SELECTED Volume Control (5 : 0) Bass Boost (3 : 0) Treble (1 : 0) DE-emphasis (1 : 0) MuTe Mode (1 : 0) Power Control (1 : 0)
1 Note
1
X
X
X
X
PC1
PC0
1. X = don't care. 1997 Jul 09 11
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
SYSTEM CLOCK FREQUENCY A 2-bit value (SC1 and SC0) to select the used external clock frequency (see Table 7). Table 7 SC1 0 0 1 1 System clock frequency settings SC0 0 1 0 1 FUNCTION 512fs 384fs 256fs not used VOLUME CONTROL DC-FILTER
UDA1340
A 1-bit value to enable the digital DC-filter (see Table 9). Table 9 DC-filtering DC 0 1 FUNCTION no DC-filtering DC-filtering
DATA INPUT FORMAT A 3-bit value (IF2 to IF0) to select the used data format (see Table 8). Table 8 IF2 0 0 0 0 1 1 1 1 Data input format settings IF1 0 0 1 1 0 0 1 1 IF0 0 1 0 1 0 1 0 1 FUNCTION I2S-bus LSB justified, 16 bits LSB justified, 18 bits LSB justified, 20 bits MSB justified not used not used not used
A 6-bit value to program the left and right channel volume attenuation (VC5 to VC0). The range is 0 dB to - dB in steps of 1 dB (see Table 10). Table 10 Volume settings VC5 0 0 0 0 : 1 1 1 1 1 VC4 0 0 0 0 : 1 1 1 1 1 VC3 0 0 0 0 : 1 1 1 1 1 VC2 0 0 0 0 : 0 1 1 1 1 VC1 0 0 1 1 : 1 0 0 1 1 VC0 0 1 0 1 : 1 0 1 0 1 VOLUME (dB) 0 0 -1 -2 : -58 -59 -60 - -
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
BASS BOOST A 4-bit value to program the bass boost setting. The used set depends on the MODE bits. Table 11 Bass boost settings BASS BOOST BB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TREBLE A 2-bit value to program the treble setting. The used set depends on the MODE bits. Table 12 Treble settings TREBLE TR1 0 0 1 1 TR0 FLAT SET (dB) 0 1 0 1 0 0 0 0 MIN. SET (dB) 0 2 4 6 BB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BB0 FLAT SET (dB) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN. SET (dB) 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18
UDA1340
MAX. SET (dB) 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24
MAX. SET (dB) 0 2 4 6
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
DE-EMPHASIS A 2-bit value to enable the digital de-emphasis filter. Table 13 De-emphasis settings DE1 0 0 1 1 MUTE A 1-bit value to enable the digital mute. Table 14 Mute MT 0 1 MODE A 2-bit value to program the mode of the sound processing filters of Bass Boost and Treble. There are three modes: flat, min. and max. FUNCTION no muting muting Table 16 Power control settings DE0 0 1 0 1 FUNCTION no de-emphasis de-emphasis, 32 kHz de-emphasis, 44.1 kHz de-emphasis, 48 kHz POWER CONTROL Table 15 The flat/min./max. switch M1 0 0 1 1 M0 0 1 0 1
UDA1340
FUNCTION flat min. min. max.
A 2-bit value to disable the ADC and/or DAC to reduce power consumption.
FUNCTION PC1 0 0 1 1 PC0 ADC 0 1 0 1 off off on on DAC off on off on
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground, VDDD = VDDA = VDDO = 3 V; Tamb = 25 C; unless otherwise specified. SYMBOL VDDD Txtal(max) Tstg Tamb Ves PARAMETER supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic handling note 1 CONDITIONS MIN. - - -65 -20 -3000 -300 MAX. 5.0 150 +125 +85 +3000 +300 UNIT V C C C V V
note 2 note 3
Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor, except pins 24, 26 and 28 which can withstand ESD pulses of -1500 V to +1500 V. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1997 Jul 09 PARAMETER thermal resistance from junction to ambient in free air VALUE 90 UNIT K/W
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1340
DC CHARACTERISTICS VDDD = VDDA = VDDO = 3 V; Tamb = 25 C; RL = 5 k; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL Supply VDDA(ADC) VDDA(DAC) VDDO VDDD IDDA(ADC) IDDA(DAC) IDDO IDDD ADC analog supply voltage DAC analog supply voltage operational amplifiers supply voltage digital supply voltage ADC supply current operation mode ADC power-down DAC supply current operation mode DAC power-down operational amplifier supply current operation mode DAC power-down digital supply current operation mode DAC power-down ADC power-down HIGH level input voltage LOW level input voltage input leakage current input capacitance HIGH level output voltage LOW level output voltage reference voltage VrefA reference output resistance input resistance input capacitance reference voltage VrefD reference output resistance DAC output resistance maximum output current load resistance load capacitance IOH = -2 mA IOL = 2 mA with respect to VSSA pin 4 1 kHz 2.7 2.7 2.7 2.7 - - - - - - - - - 0.8VDDD -0.5 - - 3.0 3.0 3.0 3.0 4.5 200 3.5 15 4 15 6 3 3 - - - - 3.6 3.6 3.6 3.6 - - - - - - - - - VDDD + 0.5 +0.2VDDD 10 10 - 0.4 0.55VDDA - - - 0.55VDDA - 3.0 - - 200 V V V V mA A mA A mA A mA mA mA V V A pF V V V k k pF V k mA k pF PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital input pins VIH VIL ILI Ci VOH VOL Vref Ro(ref) Ri Ci Vref Ro(ref) Ro Io(max) RL CL Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads must be driven then a 100 resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier.
Digital output pins 0.85VDDD - - - 0.45VDDA - - - 0.45VDDA - - - 3 - 0.5VDDA 24 9.8 20 0.5VDDA 28 0.13 0.22 - -
Analog-to-digital converter
Digital-to-analog converter with respect to VSSA pin 28 (THD + N)/S < 0.1% RL = 5 k note 2
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
AC CHARACTERISTICS (ANALOG) VDDD = VDDA = VDDO = 3 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - at 0 dB at -60 dB; A-weighted Vi = 0 V; A-weighted fripple = 1 kHz; Vripple(p-p) = 30 mV - - - - - TYP.
UDA1340
MAX. - - -80 -30 - - -
UNIT
Analog-to-digital converter Vi(rms) input voltage (RMS value) unbalance between channels 0.8 0.1 -85 -35 95 100 30 V dB dB dBA dBA dB dB
Vi
(THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N CS PSRR signal-to-noise ratio channel separation power supply rejection ratio
Digital-to-analog converter Vo(rms) output voltage (RMS value) unbalance between channels at 0 dB at -60 dB; A-weighted code = 0; A-weighted fripple = 1 kHz; Vripple(p-p) = 100 mV - - - - - - - 0.8 0.1 -85 -35 100 80 50 - - -80 - - - - V dB dB dBA dBA dB dB
Vo
(THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N cs PSRR signal-to-noise ratio channel separation power supply rejection ratio
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1340
AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = -20 to +85 C; RL = 5 k; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL Tcy clock cycle PARAMETER CONDITIONS fsys = 256fs fsys = 384fs fsys = 512fs tCWL tCWH fsys LOW level pulse width fsys HIGH level pulse width fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz Serial input/output data timing; see Fig.7 tBCK tBCK(H) tBCK(L) tr tf ts;DATI th;DATI td(DATO)(BCK) td(DATO)(WS) th;DATO ts;WS th;WS Tcy tHC tLC ts;MA th;MA ts;MT th;MT ts;DAT th;DAT thalt bit clock period bit clock HIGH time bit clock LOW time rise time fall time data input set-up time data input hold time data output delay time (from BCK falling edge) data output delay time (from WS edge) data output hold time word selection set-up time word selection hold time
1 64fs
MIN. 78 52 39 30 40 30 40
TYP. 88 59 44 - - - - - - - - - - - - - - - - - - - - - - - - - -
MAX. 131 87 66 70 60 70 60 - - - 20 20 - - 80 80 - - - - - - - - - - - - -
UNIT ns ns ns %Tsys %Tsys %Tsys %Tsys ns ns ns ns ns ns ns ns ns ns ns ns
100 100 - - 20 0 - MSB-justified format - 0 20 10
Address and data transfer mode timing; see Figs 4 and 5 L3CLK cycle time L3CLK HIGH period L3CLK LOW period L3MODE set-up time L3MODE hold time L3MODE set-up time L3MODE hold time L3DATA set-up time L3DATA hold time L3MODE halt time address mode address mode data transfer mode data transfer mode data transfer mode and address mode data transfer mode and address mode 500 250 250 190 190 190 190 190 30 190 ns ns ns ns ns ns ns ns ns ns
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
UDA1340
handbook, full pagewidth
WS tBCK(H) td(DATO)(BCK)
tr BCK
tf
th;WS
ts;WS
tBCK(L) Tcy DATAO
td(DATO)(WS)
th;DATO
ts;DATI DATAI
th;DATI
MGG840
Fig.7 Serial interface timing.
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
APPLICATION INFORMATION
UDA1340
handbook, full pagewidth
L1 3V 8LM32A07 L2 8LM32A07 ground C12 100 F (16 V) VDDD C11 100 F (16 V) C2 100 F (16 V) C21 100 nF (63 V) VDDA
VDDA R21 1
VDDD R28 1
R24
C9 100 F (16 V)
C25 100 nF (63 V) VADCN 7 VADCP
C29 100 nF (63 V) VSSD 11
VSSA(ADC) VDDA(ADC) system clock R30 47 DATAO BCK WS DATAI SYSCLK 1 12 2 6
VDDD 10
18 16 17 19
4
Vref(A) C22 100 nF (63 V) C3 47 F (16 V)
overload flag
OVERFL
9 26
VOUTL
C5 47 F (16 V) R22 10 k
R23 100
X2
left output
left input
X4
C1 47 F (16 V) C31 1 nF (63 V) R32 1 M
VINL
3
UDA1340
24 VINR 5
VOUTR
C8
R26 100 R27 10 k
X3
right input
X5
C6 47 F (16 V) C32 1 nF (63 V) R33 680 k
47 F (16 V)
right output
L3MODE L3CLOCK L3DATA
13 14 15 27 VSSO C26 100 nF (63 V) C7 100 F (16 V) 25 VDDO 22 VSSA(DAC) C27 100 nF (63 V) C10 100 F (16 V) 23
28
Vref(D) C23 100 nF (63 V) C4 47 F (16 V)
MGK582
VDDA(DAC)
R25 1 VDDO
R29 1 VDDA
Fig.8 Application diagram.
1997 Jul 09
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Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
UDA1340
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150AH EIAJ EUROPEAN PROJECTION A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
ISSUE DATE 93-09-08 95-02-04
1997 Jul 09
20
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
UDA1340
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Jul 09
21
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
UDA1340
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Jul 09
22
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio CODEC with DSP features
NOTES
UDA1340
1997 Jul 09
23
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/02/pp24
Date of release: 1997 Jul 09
Document order number:
9397 750 02548

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