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| DATA SHEET PD17072,17073 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM MOS INTEGRATED CIRCUIT DESCRIPTION PD17072 and 17073 are low-voltage 4-bit single-chip CMOS microcontrollers containing hardware ideal for organizing a digital tuning system. The CPU employs 17K architecture and can manipulate the data memory directly, perform arithmetic operations, and control peripheral hardware with a single instruction. All the instructions are 16-bit one-word instructions. As peripheral hardware, a prescaler that can operate at up to 230 MHz for a digital tuning system, a PLL frequency synthesizer, and an intermediate frequency (IF) counter are integrated in addition to I/O ports, an LCD controller/driver, A/D converter, and BEEP. Therefore, a high-performance, multi-function digital tuning system can be configured with a single chip of PD17072 or 17073. Because the PD17072 and 17073 can operate at low voltage (VDD = 1.8 to 3.6 V), they are ideal for controlling battery-cell driven portable devices such as portable radio equipment, headphone stereos, or radio cassette recorders. FEATURES * 17K architecture: general-purpose register system * Program memory (ROM) 6 KB (3072 x 16 bits): PD17072 8 KB (4096 x 16 bits): PD17073 * General-purpose data memory (RAM) 176 x 4 bits * Instruction execution time 53.3 s (with 75-kHz crystal resonator: normal operation) 106.6 s (with 75-kHz crystal resonator: low-speed mode) * Decimal operation * Table reference * Hardware for PLL frequency synthesizer Dual modulus prescaler (230 MHz max.), programmable divider, phase comparator, charge pump * Various peripheral hardware General-purpose I/O ports, LCD controller/driver, serial interface, A/D converter, BEEP, intermediate frequency (IF) counter * Many interrupts External: 1 channel Internal: 2 channels * Power-ON reset, CE reset, and power failure detector * CMOS low power consumption * Supply voltage: VDD = 1.8 to 3.6 V Unless otherwise stated, the PD17073 is taken as a representative product in this document. The information in this document is subject to change without notice. Document No. U11450EJ1V0DS00 (1st edition) Date Published September 1996 P Printed in Japan (c) 1996 PD17072,17073 ORDERING INFORMATION Part Number Package 56-pin plastic QFP (10 x 10 mm, 0.65-mm pitch) 64-pin plastic TQFP (fine pitch) (10 x 10 mm, 0.5-mm pitch) 56-pin plastic QFP (10 x 10 mm, 0.65-mm pitch) 64-pin plastic TQFP (fine pitch) (10 x 10 mm, 0.5-mm pitch) PD17072GB-xxx-1A7 PD17072GB-xxx-9EU PD17073GB-xxx-1A7 PD17073GB-xxx-9EU Remark xxx is a ROM code number. 2 PD17072,17073 FUNCTION OUTLINE Item Program memory (ROM) Function * 6K bytes (3072 x 16 bits): PD17072 * 8K bytes (4096 x 16 bits): PD17073 * Table reference area: 4096 x 16 bits * 176 x 4 bits General-purpose register: 16 x 4 bits (fixed at 00H through 0FH of BANK0, shared with data buffers.) 15 x 4 bits 32 x 4 bits * 53.3 s (with 75-kHz crystal resonator: normal operation) * 106.6 s (with 75-kHz crystal resonator: low-speed mode) Selectable by software * Address stack: 2 levels (stack can be manipulated) * Interrupt stack: 1 level (stack cannot be manipulated) * I/O port: 8 * Input port: 4 * Output port: 9 * 1 type * Selectable frequency (1.5 kHz, 3 kHz) * 15 segments, 4 commons 1/4 duty, 1/2 bias, frame frequency of 62.5 Hz, drive voltage VLCD1 = 3.1 V (TYP.) * 1 channel (Serial I/O mode) 3-wire/2-wire mode selectable 4 bits x 2 channels (successive approximation via software) * 3 channels (maskable interrupt) External interrupt: 1 (INT pin) Internal interrupt: 2 (basic timer 1, serial interface) * 2 channels Basic timer 0: 125 ms Basic timer 1: 8 ms, 32 ms * Power-ON reset (on power application) * Reset by CE pin (CE pin: low level high level) * Power failure detection function Division method * Direct division method * Pulse swallow method (VCOL pin: 8 MHz MAX.) (VCOL pin: 55 MHz MAX.) (VCOH pin: 230 MHz MAX.) General-purpose data memory (RAM) LCD segment register Peripheral control register Instruction execution time Stack level General-purpose port BEEP LCD controller/driver Serial interface A/D converter Interrupt Timer Reset PLL frequency synthesizer Reference frequency Charge pump Phase comparator Frequency counter * 6 types selectable by program 1, 3, 5, 6.25, 12.5, 25 kHz Error out output: 1 line (EO pin) Unlock detectable by program * Frequency measurement P0D3/FMIFC/AMIFC pin: FMIF mode, 10 to 11 MHz P0D3/FMIFC/AMIFC pin: AMIF mode 400 to 500 kHz P0D2/AMIFC pin VDD = 1.8 to 3.6 V * 56-pin plastic QFP (10 x 10 mm, 0.65-mm pitch) * 64-pin plastic TQFP (10 x 10 mm, 0.5-mm pitch) Supply voltage Package 3 PD17072,17073 BLOCK DIAGRAM SCK/P0B2 Serial Interface P0B0-P0B3 RAM 176x4 bits BEEP SYSTEM REG. P0D2, P0D3 Port Interrupt Controller ALU Basic Timer0 P1B0-P1B3 Instruction Decoder INT SI/SO1/P0B3 SO0/P1C0 P0A0-P0A3 P0C0, P0C1 BEEP P1A0-P1A3 P1C0 Basic Timer1 REGLCD0 REGLCD1 CAPLCD0 CAPLCD1 Voltage Doubler ROM 3072x16 bits ( PD17072) 4096x16 bits ( PD17073) A/D Converter AD0/P1A2 AD1/P1A3 FMIFC/AMIFC/P0D3 AMIFC/P0D2 EO Frequency Counter COM0 COM3 LCD0 LCD14 LCD Controller /Driver Program Counter 12 bits PLL VCOH VCOL Stack 2x12 bits PLL Voltage Regulator REG0 XIN XOUT OSC CPU Peripheral Reset XTAL Voltage Regulator VDD CE GND REG1 4 PD17072,17073 PIN CONFIGURATION (Top View) 56-pin plastic QFP (10 x 10 mm) PD17072GB-xxx-1A7 PD17073GB-xxx-1A7 P0B3/SI/SO1 P0B2/SCK LCD14 LCD13 LCD12 LCD11 LCD10 BEEP LCD9 44 56 P1C0/SO0 P0A0 P0A1 P0A2 P0A3 P1B0 P1B1 P1B2 P1B3 P1A0 P1A1 P1A2/AD0 P1A3/AD1 P0C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 55 54 53 52 51 50 49 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 COM3 COM2 COM1 COM0 REGLCD1 CAPLCD1 16 17 18 19 20 21 22 23 24 25 26 27 28 P0C1 REG1 P0D3/FMIFC/AMIFC P0D2/AMIFC REGLCD0 REG0 CAPLCD0 GND EO VCOH VCOL XOUT VDD XIN LCD8 P0B1 P0B0 INT CE 5 PD17072,17073 64-pin plastic TQFP (fine pitch) (10 x 10 mm) PD17072GB-xxx-9EU PD17073GB-xxx-9EU P0B3/SI/SO1 P0B2/SCK LCD14 LCD13 LCD12 LCD11 LCD10 BEEP LCD9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P1C0/SO0 P0A0 P0A1 P0A2 NC P0A3 P1B0 P1B1 P1B2 P1B3 P1A0 NC P1A1 P1A2/AD0 P1A3/AD1 P0C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LCD7 LCD6 LCD5 NC LCD4 LCD3 LCD2 LCD1 LCD0 COM3 NC COM2 COM1 COM0 REGLCD1 CAPLCD1 P0C1 REG1 P0D3/FMIFC/AMIFC REGLCD0 REG0 P0D2/AMIFC 6 CAPLCD0 GND GND EO VCOH VCOL XOUT VDD VDD XIN LCD8 P0B1 P0B0 INT NC NC CE PD17072,17073 PIN IDENTIFICATION AD0, AD1 AMIFC BEEP CE COM0-COM2 EO FMIFC GND INT LCD0-LCD14 NC P0A0-P0A3 P0B0-P0B3 P0C0, P0C1 P0D2, P0D3 P1A0-P1A3 P1B0-P1B3 P1C0 REG0 REG1 SCK SI SO0, SO1 VCOL VCOH VDD XIN, XOUT : A/D converter input : Intermediate frequency (IF) counter input : BEEP output : Chip enable : LCD common signal output : Error out : Intermediate frequency (IF) counter input : Ground : External interrupt request signal input : LCD segment signal output : No connection : Port 0A : Port 0B : Port 0C : Port 0D : Port 1A : Port 1B : Port 1C : PLL voltage regulator : Oscillation circuit voltage regulator : Serial clock I/O : Serial data input : Serial data output : Local oscillator input : Local oscillator input : Positive power supply : Crystal resonator connection pins CAPCLD0, CAPLCD1 : Capacitor connection for LCD drive voltage REGLCD0, REGLCD1 : LCD drive voltage 7 PD17072,17073 CONTENTS 1. PIN FUNCTION .................................................................................................................................. 12 1.1 1.2 1.3 1.4 Pin Function List ...................................................................................................................................... 12 Equivalent Circuits of Pins ....................................................................................................................... 15 Processing of Unused Pins ..................................................................................................................... 18 Notes on Using CE Pin ............................................................................................................................ 19 2. PROGRAM MEMORY (ROM) ........................................................................................................... 20 2.1 2.2 2.3 2.4 2.5 General ..................................................................................................................................................... 20 Program Memory ..................................................................................................................................... 21 Program Counter ...................................................................................................................................... 21 Execution Flow of Program Memory ....................................................................................................... 22 Notes on Using Program Memory ........................................................................................................... 22 3. ADDRESS STACK (ASK) ................................................................................................................. 23 3.1 3.2 3.3 3.4 3.5 General ..................................................................................................................................................... 23 Address Stack Register (ASR) ................................................................................................................ 23 Stack Pointer (SP) ................................................................................................................................... 24 Operations of Address Stack ................................................................................................................... 25 Notes on Using Address Stack ................................................................................................................ 25 4. DATA MEMORY (RAM) ..................................................................................................................... 26 4.1 4.2 4.3 4.4 General ..................................................................................................................................................... 26 Configuration and Function of Data Memory .......................................................................................... 27 Addressing Data Memory ........................................................................................................................ 30 Notes on Using Data Memory ................................................................................................................. 31 5. SYSTEM REGISTER (SYSREG) ...................................................................................................... 32 5.1 5.2 5.3 5.4 5.5 General ..................................................................................................................................................... 32 Address Register (AR) ............................................................................................................................. 33 Bank Register (BANK) ............................................................................................................................. 35 Program Status Word (PSWORD) .......................................................................................................... 36 Notes on Using System Register ............................................................................................................ 37 6. GENERAL REGISTERS (GR) ........................................................................................................... 38 6.1 6.2 6.3 Outline of General Registers ................................................................................................................... 38 Address Creation of General Register with Each Instruction ................................................................ 39 Notes on Using General Register ........................................................................................................... 39 7. ALU (ARITHMETIC LOGIC UNIT) BLOCK ....................................................................................... 40 7.1 7.2 7.3 7.4 General ..................................................................................................................................................... 40 Configuration and Function of Each Block ............................................................................................. 41 ALU Processing Instructions ................................................................................................................... 41 Notes on Using ALU ................................................................................................................................ 44 8 PD17072,17073 8. PERIPHERAL CONTROL REGISTERS ........................................................................................... 45 8.1 8.2 Outline of Peripheral Control Registers .................................................................................................. 45 Configuration and Function of Peripheral Control Registers ................................................................. 46 9. DATA BUFFER (DBF) ....................................................................................................................... 54 9.1 9.2 9.3 9.4 General ..................................................................................................................................................... 54 Data Buffer ............................................................................................................................................... 55 List of Peripheral Hardware and Data Buffer Functions ........................................................................ 56 Notes on Using Data Buffer ..................................................................................................................... 56 10. GENERAL-PURPOSE PORT ............................................................................................................ 57 10.1 10.2 10.3 10.4 General ..................................................................................................................................................... 57 General-Purpose I/O Ports (P0B, P0C, P0D) ......................................................................................... 58 General-Purpose Input Ports (P1A) ........................................................................................................ 62 General-Purpose Output Ports (P0A, P1B, P1C) ................................................................................... 65 11. INTERRUPT ....................................................................................................................................... 66 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 General ..................................................................................................................................................... 66 Interrupt Control Block ............................................................................................................................. 67 Interrupt Stack Register ........................................................................................................................... 70 Stack Pointer, Address Stack Register, and Program Counter ............................................................. 72 Interrupt Enable Flip-Flop (INTE) ............................................................................................................ 72 Accepting Interrupt ................................................................................................................................... 73 Operations after Accepting Interrupt ....................................................................................................... 77 Exiting from Interrupt Service Routine .................................................................................................... 78 External (INT Pin) Interrupts ................................................................................................................... 79 11.10 Internal Interrupt ....................................................................................................................................... 81 12. TIMER ................................................................................................................................................ 82 12.1 12.2 12.3 General ..................................................................................................................................................... 82 Basic Timer 0 ........................................................................................................................................... 82 Basic Timer 1 ........................................................................................................................................... 91 13. A/D CONVERTER ............................................................................................................................. 98 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 General ..................................................................................................................................................... 98 Setting A/D Converter Power Supply ...................................................................................................... 99 Input Selector Block ............................................................................................................................... 100 Compare Voltage Generator Block and Compare Block ..................................................................... 102 Comparison Timing Chart ...................................................................................................................... 107 Performance of A/D Converter .............................................................................................................. 107 Using A/D Converter .............................................................................................................................. 108 Status at Reset ....................................................................................................................................... 111 14. SERIAL INTERFACE ....................................................................................................................... 112 14.1 14.2 14.3 14.4 General ................................................................................................................................................... 112 Clock Input/Output Control Block and Data Input/Output Control Block ............................................. 113 Clock Control Block ............................................................................................................................... 116 Clock Counter ........................................................................................................................................ 116 9 PD17072,17073 14.5 14.6 14.7 14.8 14.9 Presettable Shift Register ...................................................................................................................... 117 Wait Control Block ................................................................................................................................. 117 Serial Interface Operation ..................................................................................................................... 118 Notes on Setting and Reading Data ..................................................................................................... 122 Operational Outline of Serial Interface ................................................................................................. 123 14.10 Status on Reset ..................................................................................................................................... 125 15. PLL FREQUENCY SYNTHESIZER ................................................................................................ 126 15.1 15.2 15.3 15.4 15.5 15.6 15.7 General ................................................................................................................................................... 126 Input Selector Block and Programmable Divider ................................................................................. 127 Reference Frequency Generator ........................................................................................................... 133 Phase Comparator (-DET), Charge Pump, and Unlock FF ............................................................... 135 PLL Disable Status ................................................................................................................................ 139 Use of PLL Frequency Synthesizer ...................................................................................................... 140 Status on Reset ..................................................................................................................................... 143 16. INTERMEDIATE FREQUENCY (IF) COUNTER ............................................................................. 144 16.1 16.2 16.3 16.4 16.5 Outline of Intermediate Frequency (IF) Counter .................................................................................. 144 IF Counter Input Selector Block and Gate Time Control Block ........................................................... 145 Start Control Block and IF Counter ....................................................................................................... 147 Using IF Counter .................................................................................................................................... 152 Status at Reset ...................................................................................................................................... 154 17. BEEP ................................................................................................................................................ 155 17.1 17.2 17.3 Configuration and Function of BEEP .................................................................................................... 155 Output Wave Form of BEEP ................................................................................................................. 156 Status at Reset ...................................................................................................................................... 157 18. LCD CONTROLLER/DRIVER ......................................................................................................... 158 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Outline of LCD Controller/Driver ........................................................................................................... 158 LCD Drive Voltage Generation Block .................................................................................................... 159 LCD Segment Register .......................................................................................................................... 160 Common Signal Output and Segment Signal Output Timing Control Blocks ..................................... 162 Common Signal and Segment Signal Output Waves .......................................................................... 163 Using LCD Controller/Driver .................................................................................................................. 165 Status at Reset ...................................................................................................................................... 167 19. STANDBY ........................................................................................................................................ 168 19.1 19.2 19.3 19.4 19.5 19.6 19.7 General ................................................................................................................................................... 168 Halt Function .......................................................................................................................................... 170 Clock Stop Function ............................................................................................................................... 178 Device Operations in Halt and Clock Stop Statuses ............................................................................ 181 Note on Processing of Each Pin in Halt and Clock Stop Statuses ..................................................... 182 Device Control Function by CE Pin ...................................................................................................... 185 Low-Speed Mode Function .................................................................................................................... 187 10 PD17072,17073 20. RESET .............................................................................................................................................. 188 20.1 20.2 20.3 20.4 20.5 20.6 Configuration of Reset Block ................................................................................................................. 188 Reset Function ....................................................................................................................................... 189 CE Reset ................................................................................................................................................ 190 Power-ON Reset .................................................................................................................................... 194 Relations between CE Reset and Power-ON Reset ............................................................................ 197 Power Failure Detection ........................................................................................................................ 199 21. PD17012 INSTRUCTIONS ............................................................................................................ 204 21.1 21.2 21.3 21.4 Instruction Set Outline ........................................................................................................................... 204 Legend .................................................................................................................................................... 205 Instruction List ........................................................................................................................................ 206 Assembler (AS17K) Embedded Macroinstructions .............................................................................. 207 22. PD17073 RESERVED WORDS .................................................................................................... 208 22.1 22.2 22.3 22.4 22.5 22.6 22.7 Data Buffer (DBF) .................................................................................................................................. 208 System Register (SYSREG) .................................................................................................................. 208 LCD Segment Register .......................................................................................................................... 209 Port Register .......................................................................................................................................... 210 Peripheral Control Register ................................................................................................................... 211 Peripheral Hardware Register ..................................................................................................................... Others ..................................................................................................................................................... 213 23. ELECTRICAL CHARACTERISTICS ............................................................................................... 214 24. PACKAGE DRAWINGS ................................................................................................................... 217 25. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 219 APPENDIX A. NOTES ON CONNECTING CRYSTAL RESONATOR ................................................ 220 APPENDIX B. DEVELOPMENT TOOLS.............................................................................................. 221 11 PD17072,17073 1. PIN FUNCTION 1.1 Pin Function List Pin No. QFP 1 TQFP 1 P1C0/SO0 Port 1C and output of serial interface. P1C0 * 1-bit output port * SO0 * Serial data output CMOS push-pull Symbol Function Output format At power-ON reset Low-level output * 2 3 4 5 6 7 8 9 10 11 12 13 2 3 4 6 7 8 9 10 11 13 14 15 P0A0 P0A1 P0A2 P0A3 P1B0 P1B1 P1B2 P1B3 P1A0 P1A1 P1A2/AD0 P1A3/AD1 4-bit output port (port 0A). CMOS push-pull Low-level output 4-bit output port (port 1B). CMOS push-pull Low-level output Port 1A and analog inputs to A/D converter. -- Inputs with pulldown resistor * * P1A3-P1A0 * 4-bit input port AD1, AD0 * Analog inputs to A/D converter CMOS push-pull 14 15 16 17 16 17 18 19 P0C0 P0C1 P0D2/AMIFC P0D3/FMIFC/ AMIFC 2-bit I/O port (port 0C). Input/output mode can be set in 1-bit units. Port 0D and IF counter inputs. * P0D3, P0D2 * 2-bit I/O port * Can be set in input/output mode in 1-bit units. * FMIFC, AMIFC * IF counter inputs Ground Input CMOS push-pull Input 18 20 21 GND -- -- 19 20 21 22 22 23 24 25 EO VCOL VCOH REG0 Output from charge pump of PLL frequency synthesizer Input local oscillation frequency of PLL. CMOS 3-state -- Floating Floating Output of PLL voltage regulator. Connect this pin to GND via 0.1-F capacitor. -- Low-level output REG0 0.1 F 12 PD17072,17073 Pin No. QFP 23 TQFP 26 27 VDD Positive power supply. Supply 1.8 to 3.6 V (TA = -20 to +70 C) to operate all functions. Do not apply voltage higher than that of VDD pin to any pin other than VDD. Pins for connecting crystal resonator for system clock oscillation. Output of voltage regulator for oscillation circuit. Connect this pin to GND via 0.1-F capacitor. -- Symbol Function Output format At power-ON reset -- 24 25 26 28 29 30 XOUT XIN REG1 CMOS push-pull -- -- -- -- REG1 0.1 F 27 28 29 30 31 32 33 34 REGLCD0 CAPLCD0 CAPLCD1 REGLCD1 * * REGLCD1, REGLCD0 LCD drive power pins. CAPLCD1, CAPLCD0 Connect capacitors for doubler circuit to generate LCD drive voltage, across these pins. To configure doubler circuit, connect capacitors as shown below. -- -- C1 REGLCD1 C1 = C2 = 0.1 F C3 = 0.01 F CAPLCD1 C3 CAPLCD0 REGLCD0 C2 Caution The value of the LCD drive voltage differs if the values of C1, C2, and C3 are changed because of the configuration of the doubler circuit. 13 PD17072,17073 Pin No. QFP 31 32 33 34 35 | 49 50 51 TQFP 35 36 37 39 40 | 56 57 58 COM0 COM1 COM2 COM3 LCD0 | LCD14 CE INT Common signal outputs of LCD controller/driver. CMOS ternary output Symbol Function Output format At power-ON reset Low-level output Segment signal outputs of LCD controller/driver. CMOS push-pull Low-level output Device operation select and reset signal input. External interrupt request signal input. Interrupt request is issued at rising or falling edge of signal input to this pin. BEEP signal output pin. BEEP output of 1.5 kHz or 3 kHz can be selected. Port 0B and serial interface I/O. * P0B3-P0B0 * 4-bit I/O port * Can be set in input or output mode in 1-bit units. * SCK * Serial clock I/O * SO1 * Serial data output * SI * Serial data input No connection -- -- Input Input 52 60 BEEP CMOS push-pull Low-level output 53 54 55 56 61 62 63 64 P0B0 P0B1 P0B2/SCK P0B3/SI/SO1 CMOS push-pull Input -- 5 12 38 45 54 59 NC -- -- 14 PD17072,17073 1.2 Equivalent Circuits of Pins (1) P0B (P0B3/SI/SO1, P0B2/SCK, P0B1, P0B0) P0C (P0C1, P0C0) P0D (P0D3/FMIFC/AMIFC, P0D2/AMIFC) (I/O) VDD VDD (2) P0A (P0A3, P0A2, P0A1, P0A0) P1B (P1B3, P1B2, P1B1, P1B0) P1C (P1C0/SO0) LCD14-LCD0 BEEP EO (Output) VDD (3) P1A (P1A3/AD1, P1A2/AD0, P1A1, P1A0) (Input) VDD High ON resistance 15 PD17072,17073 (4) CE (Schmitt trigger input) VDD CE flag (5) INT (Schmitt trigger input) VDD (6) XOUT (output), XIN (input) VDD High ON resistance VDD XIN High ON resistance XOUT 16 PD17072,17073 (7) COM3 through COM0 (output) VLCD0 VLCD1 (8) VCOH (input) High ON resistance VDD VDD (9) VCOL (input) High ON resistance VDD PLL disable signal High ON resistance VDD PLL disable signal 17 PD17072,17073 1.3 Processing of Unused Pins It is recommended that the unused pins be connected as follows: Table 1-1. Processing of Unused Pins Pin name Port pin P0A0-P0A3 P0B0, P0B1 P0B2/SCK P0B3/SI/SO1 P0C0, P0C1 P0D2/AMIFC P0D3/FMIFC/AMIFC P1A0, P1A1 P1A2/AD0 P1A3/AD1 P1B0-P1B3 P1C0/SO0 Pins other than port pins BEEP CE COM0-COM3 EO INT LCD0-LCD14 VCOH, VCOL CMOS push-pull output Input Output Output Input CMOS push-pull output Input Connect to GND via resistor Open Connect each of these pins to GND via resistorNote 2. Note 2 I/O mode CMOS push-pull output I/O Note 1 Recommended processing of unused pins Open Set by software to output low level and open Input Connect each of these pins to VDD or GND via resistor Note 2 . CMOS push-pull output Open Open Connect to VDD via resistor Open Note 2 . . Notes 1. The I/O ports are set in the input mode on power application, on clock stop, and on CE reset. 2. When pulling up (connecting to VDD via resistor) or pulling down (connecting to GND via resistor) a pin externally with high resistance, the pin almost goes into a high-impedance state, and consequently, the current consumption (through current) of the port increases. Generally, the pull-up or pull-down resistance is several 10 k, though it varies depending on the application circuit. 18 PD17072,17073 1.4 Notes on Using CE Pin The CE pin has a function to set a test mode in which the internal operations of the PD17073 are tested (dedicated to IC test), in addition to the functions listed in 1.1 Pin Function List. When a voltage higher than VDD is applied to the CE pin, the test mode is set. This means that if noise exceeding VDD is applied to the CE pin even during normal operation, the test mode is set, affecting the normal operation. If the wiring of the CE pin is too long, the above problem occurs because wiring noise is superimposed on the CE pin. Therefore, wire the CE pin with as short a wiring length as possible to suppress noise. If noise cannot be avoided, use external components as shown below to suppress noise. * Connect a diode with low VF between CE and VDD VDD * Connect a capacitor between CE and VDD VDD Diode with low VF CE VDD VDD CE 19 PD17072,17073 2. PROGRAM MEMORY (ROM) 2.1 General Figure 2-1 shows the configuration of the program memory. As shown in this figure, the program memory consists of a program memory and a program counter. The addresses of the program memory are specified by the program counter. The program memory has the following two major functions: (1) Stores program (2) Stores constant data Figure 2-1. Outline of Program Memory Program counter Specifies address Program memory * * * Instruction * * * * * * Constant data * * * 20 PD17072,17073 2.2 Program Memory Figure 2-2 shows the configuration of the program memory. As shown in this figure, the program memory is configured as follows: PD17072: 3072 x 16 bits (0000H-0BFFH) PD17073: 4096 x 16 bits (0000H-0FFFH) Therefore, the addresses of the program memory range from 0000H to 0FFFH. All the "instructions" are "one-word instructions" each of which is 16 bits long. Consequently, one instruction can be stored in one address of the program memory. As constant data, the contents of the program memory are read to the data buffer by using a table reference instruction. Figure 2-2. Configuration of Program Memory 0 0 0 0H 0 0 0 1H 0 0 0 2H 0 0 0 3H Reset start address Serial interface interrupt vector Basic timer 1 interrupt vector Page 0 INT pin interrupt vector CALL addr instruction subroutine entry address BR addr instruction branch address BR @AR instruction branch address CALL @AR instruction subroutine entry address MOVT DBF @AR instruction table reference address Page 1 0 7 F FH 0 B F FH (with PD17072) 0 F F FH (with PD17073) 16 bits Caution With the PD17072, the range of addresses that can be called by each instruction is 0000H to 0BFFH. The area from addresses 0C00H through 0FFFH is an undefined area. 2.3 Program Counter Figure 2-3 shows the configuration of the program counter. The program counter specifies an address of the program memory. As shown in this figure, the program counter is a 12-bit binary counter. The most significant bit b11 indicates a page. Figure 2-3. Configuration of Program Counter PC11 Page PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC 21 PD17072,17073 2.4 Execution Flow of Program Memory Execution of the program is controlled by the program counter which specifies an address of the program memory. Figure 2-4 shows the values to be set to the program counter when each instruction is executed. Table 2-1 shows the vector addresses that are to be set to the program counter when each interrupt occurs. Figure 2-4. Specification by Program Counter On Execution of Each Instruction Program counter Instruction Page 0 BR addr Page 1 CALL addr 1 0 b11 0 b10 b9 Contents of program counter (PC) b8 b7 b6 b5 b4 b3 b2 b1 b0 Instruction operand (addr) Instruction operand (addr) BR @AR CALL @AR MOVT DBF, @AR RET RETSK RETI When interrupt is accepted Power-ON reset, CE reset 0 0 0 Contents of address register Contents of address stack register (ASR) specified by stack pointer (SP) (Return address) Vector address of each interrupt 0 0 0 0 0 0 0 0 0 Table 2-1. Interrupt Vector Address Priority 1 2 3 Internal/external External External External Interrupt source INT pin Basic timer 1 Serial interface Vector address 0003H 0002H 0001H 2.5 Notes on Using Program Memory (1) PD17072 The program memory addresses of the PD17072 are 0000H through 0BFFH. However, because the addresses that can be specified by the program counter (PC) are 0000H through 0FFFH, keep the following points in mind when specifying a program memory address: * Be sure to write a branch instruction to address 0BFFH, when writing an instruction to this address. * Do not write an instruction to addresses 0C00H through 0FFFH. * Do not branch to addresses 0C00H through 0FFFH. (2) With PD17073 The program memory addresses of the PD17073 are 0000H through 0FFFH. Keep the following point in mind: * Be sure to write a branch instruction to address 0FFFH, when writing an instruction to this address. 22 PD17072,17073 3. ADDRESS STACK (ASK) 3.1 General Figure 3-1 outlines the address stack. The address stack consists of a stack pointer and an address stack register. The address of the address stack register is specified by the stack pointer. The address stack saves return addresses when a subroutine call instruction has been executed and when an interrupt has been accepted. The address stack is also used when a table reference instruction is executed. Figure 3-1. Outline of Address Stack Stack pointer Specifies address Address stack register Return address 3.2 Address Stack Register (ASR) Figure 3-2 shows the configuration of the address stack register. The address stack register consists of three 12-bit registers ASR0-ASR2. Actually, however, no register is assigned to ASR2, and the address stack register therefore consists of two 12-bit registers (ASR0 and ASR1). The address stack saves return addresses when a subroutine call instruction has been executed, when an interrupt has been accepted, and when a table reference instruction is executed. Figure 3-2. Configuration of Address Stack Register Stack pointer (SP) Bit Address b3 0 b2 0 b1 b0 0H b11 b10 Address stack register (ASR) Bit b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SP1 SP0 ASR0 1H ASR1 Cannot be used 2H ASR2 (Undefined) 23 PD17072,17073 3.3 Stack Pointer (SP) Figure 3-3 shows the configuration and functions of the stack pointer. The stack pointer is a 4-bit binary counter. The stack pointer specifies the addresses of the address stack registers. The value of the stack pointer can be directly read or written by using a register manipulation instruction. Figure 3-3. Configuration and Functions of Stack Pointer Flag symbol Name b3 Stack pointer SP b2 b1 S P 1 b0 S P 0 Address Read/ Write 0 0 01H R/W Specifies address of address stack register (ASR) 0 0 1 0 1 0 Address 0 (ASR0) Address 1 (ASR1) Address 2 (ASR2) Fixed to "0" Power-ON At reset Clock stop CE 0 0 1 1 1 0 0 0 24 PD17072,17073 3.4 Operations of Address Stack 3.4.1 Subroutine call ("CALL addr" or "CALL @AR") and return ("RET" or "RETSK") instructions When a subroutine call instruction is executed, the value of the stack pointer is decremented by one and the return address is stored to the address stack register specified by the stack pointer. When a return instruction is executed, the contents of the address stack specified by the stack pointer (return address) is restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.2 Table reference instruction ("MOVT DBF, @AR") When the table reference instruction is executed, the value of the stack pointer is decremented by one and the return address is stored to the address stack register specified by the stack pointer. Next, the contents of the program memory addressed by the address register are read to the data buffer, and the contents of the address stack register specified by the stack pointer (return address) are restored to the program counter. The value of the stack pointer is then incremented by one. 3.4.3 On acceptance of interrupt and execution of return instruction ("RETI" instruction) When an interrupt is accepted, the value of the stack pointer is decremented by one, and the return address is stored to the address stack register specified by the stack address. When the return instruction is executed, the contents of the address stack register specified by the stack pointer (return address) are restored to the program counter and the value of the stack pointer is incremented by one. 3.4.4 Address stack manipulation instructions ("PUSH AR" and "POP AR") When the "PUSH" instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register are transferred to the address stack register specified by the stack pointer. When the "POP" instruction is executed, the contents of the address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one. 3.5 Notes on Using Address Stack The nesting level of the address stack is two, and the value of the address stack register ASR2 is "undefined" when the value of the stack pointer is 2H. Consequently, if a subroutine is called or an interrupt is used exceeding 2 levels without manipulating the stack, program execution returns to an "undefined" address. 25 PD17072,17073 4. DATA MEMORY (RAM) 4.1 General Figure 4-1 outlines the data memory. As shown in this figure, the data memory consists of a general-purpose data memory, system register, data buffer, general register, LCD segment register, port register, and peripheral control register. The data memory stores data, transfers data with peripheral hardware, sets conditions for the peripheral hardware, display data, transfers data with ports, and controls the CPU. Figure 4-1. Outline of Data Memory Peripheral hardware Data transfer Column address 0 0 1 2 1 2 3 4 5 6 7 8 9 A B C D E F Data buffer General register Row address 3 Data memory 4 5 6 7 Port register BANK0 BANK1 LCD segment register Peripheral control register Port register System register Data transfer Port Data transfer LCD Condition setting Peripheral hardware 26 PD17072,17073 4.2 Configuration and Function of Data Memory Figure 4-2 shows the configuration of the data memory. As shown in this figure, the data memory is divided into three banks, and each bank consists of 128 nibbles with 7H row addresses and 0FH column addresses. In terms of function, the data memory can be divided into six blocks each of which is described in the following paragraphs 4.2.1 through 4.2.8. The contents of the data memory can be operated, compared, judged, and transferred in 4-bit units by data memory manipulation instructions. Table 4-1 lists the data memory manipulation instructions. 4.2.1 System registers (SYSREG) The system registers are allocated to addresses 74H through 7FH. These registers are allocated independently of the bank and directly control the CPU. The same system registers exist at addresses 74H through 7FH of each bank. With the PD17073, only AR (address register: addresses 75H through 77H), BANK (bank register: address 79H), and PSWORD (program status word: addresses 7EH and 7FH) can be manipulated. For details, refer to 5. SYSTEM REGISTER (SYSREG). 4.2.2 Data buffer (DBF) The data buffer is allocated to addresses 0CH through 0FH of BANK0. The data buffer reads the constant data in the program memory (table reference), and transfers data with peripheral hardware. For details, refer to 9. DATA BUFFER (DBF). 4.2.3 General registers With the PD17073, the general registers are fixed at row address 0 of BANK0, i.e., addresses 00H through 0FH, and cannot be moved. Operations and data transfer between the general registers and data memory can be executed with a single instruction. The general registers can be controlled by data memory manipulation instructions, like the other data memory areas. For details, refer to 6. GENERAL REGISTER (GR). 4.2.4 LCD segment registers The LCD segment registers are allocated to addresses 41H through 4FH of BANK1 of the data memory, and are used to set the display data of the LCD controller/driver. For details, refer to 18. LCD CONTROLLER/DRIVER. 4.2.5 Port registers The port registers are allocated to addresses 70H through 73H of BANK0 and addresses 70H through 73H of BANK1, and are used to set the output data of each general-purpose port and read the data of the input ports. For details, refer to 10. GENERAL-PURPOSE PORT. 4.2.6 Peripheral control registers The peripheral control registers are allocated to addresses 50H through 6FH of BANK1 and are used to set the conditions of the peripheral hardware (such as PLL, serial interface, A/D converter, IF counter, and timer). For details, refer to 8. PERIPHERAL CONTROL REGISTER. 27 PD17072,17073 4.2.7 General-purpose data memory The general-purpose data memory is allocated to the area of the data memory excluding the system register, LCD segment register, port register, and peripheral control register. With the PD17073, a total of 176 nibbles (176 x 4 bits), 112 nibbles of BANK0 and 64 nibbles of BANK1, can be used as the general-purpose data memory. 4.2.8 Data memory areas not provided For these data memory areas, refer to 4.4.2 Notes on data memory areas not provided, 8.2 Configuration and Function of Peripheral Control Registers, and Table 10-1 Relation between Each Port (Pin) and Port Register. 28 PD17072,17073 Figure 4-2. Configuration of Data Memory Column address 0 0 1 1 2 3 4 5 6 7 8 9 A B C D E F Row address 2 3 4 5 6 7 Data memory BANK0 BANK1 System register Column address 0 0 1 1 2 3 4 5 6 7 8 9 A B C D E F General register Data buffer Row address 2 3 4 5 6 7 Port register BANK0 Example Address 2BH of BANK0 b3 b2 b1 b0 System register (SYSREG) 0 0 1 1 2 3 4 5 6 7 8 9 A B C D E F Row address 2 3 4 5 6 7 Port register BANK1 Same system register exists. LCD segment register Peripheral control register System register (SYSREG) Caution Address 40H of BANK1, bit 3 of address 50H, and address 73H are test mode areas. Do not write "1" to these areas. 29 PD17072,17073 Table 4-1. Data Memory Manipulation Instructions Function Add Instruction ADD ADDC SUB SUBC AND Operation Subtract Logical OR XOR SKE Compare SKGE SKLT SKNE MOV Transfer LD ST Judge SKT SKF 4.3 Addressing Data Memory Figure 4-3 shows how to address the data memory. An address of the data memory is specified by using a bank, row address, and column address. The row address and column address are directly specified by a data memory manipulation instruction, but the bank is specified by the contents of the bank register. For details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG). Figure 4-3. Addressing Data Memory Bank b3 b2 b1 b0 Row address Column address b2 b1 b0 b3 b2 b1 b0 Data memory address M Bank register Instruction operand 30 PD17072,17073 4.4 Notes on Using Data Memory 4.4.1 On power-ON reset On power-ON reset, the contents of the general-purpose data memory are "undefined". Initialize the memory if necessary. 4.4.2 Notes on data memory not provided If a data memory manipulation instruction is executed to manipulate an address where no data memory is assigned, the following operations are performed: (1) Device operation When a read instruction is executed, "0" is read. Nothing is changed even when a write instruction is executed. Address 40H of BANK1, bit 3 of address 50H, and address 73H are test mode areas. Do not write "1" to these areas. (2) Assembler operation The program is assembled normally. No "error" occurs. (3) In-circuit emulator operation "0" is read when a read instruction is executed. Nothing is changed when a write instruction is executed. No "error" occurs. 31 PD17072,17073 5. SYSTEM REGISTER (SYSREG) 5.1 General Figure 5-1 shows the location of the system register on the data memory and outline. As shown, the system register is assigned to addresses 74H-7FH of the data memory, regardless of bank. In other words, the same system register is assigned to addresses 74H-7FH of any bank. Since the system register is located on the data memory, it can be manipulated by all the data memory manipulation instructions. With the PD17073, only the address register (AR: 74H through 77H), bank register (BANK: 79H), and program status word (PSWORD: 7EH, 7FH) of addresses 74H through 7FH can be manipulated. Figure 5-1. Location of System Register on Data Memory and Outline 0 0 1 2 3 4 5 6 7 1 2 3 4 5 Column address 6789A Data memory B C D E F Row address BANK0 BANK1 System register Address 74H 75H 76H 77H 78H 79H Name Address register (AR) Fixed to 0 Bank register (BANK) Outline Controls program memory address Specifies data memory bank Address 7AH 7BH 7CH 7DH 7EH 7FH Name Fixed to 0 Program status word (PSWORD) Outline Controls operation 32 PD17072,17073 5.2 Address Register (AR) 5.2.1 Configuration of address register Figure 5-2 shows the configuration of the address register. As shown in this figure, the address register consists of 16 bits of the system register: 74H through 77H (AR3 through AR0). However, the higher 4 bits are always fixed to 0, and therefore, the address register actually functions as a 12-bit register. Figure 5-2. Address Register Configuration Address Name Symbol Bit b3 74H 75H 76H 77H Address register (AR) AR3 b2 b1 b0 b3 M AR2 b2 b1 b0 b3 AR1 b2 b1 b0 b3 AR0 b2 b1 b0 L S B Data 0 0 0 0 S B At reset Power-ON Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 Remark Power-ON : On power-ON reset Clock stop : On execution of clock stop instruction CE : On CE reset 33 PD17072,17073 5.2.2 Functions of address register The address register specifies a program memory address when the table reference instruction ("MOVT DBF, @AR"), stack manipulation instruction ("PUSH AR" or "POP AR"), indirect branch instruction ("BR @AR"), and indirect subroutine call instruction ("CALL @AR") has been executed. A dedicated instruction ("INC AR") that can increment the value of the address register by one is available. The following paragraphs (1) through (5) describe the operations of the address register when each of these instructions has been executed. (1) Table reference instruction ("MOVT DBF, @AR") When the "MOVT DBF, @AR" instruction is executed, the constant data (16 bits) of the program memory address specified by the contents of the address register are read to the data buffer. The addresses of the constant data which can be specified by the address register are 0000H-0FFFH. (2) Stack manipulation instruction ("PUSH AR", "POP AR") By executing the "PUSH AR" instruction, the stack pointer is decremented by one and the contents of the address register (AR) are stored to the address stack register specified by the stack pointer. When the "POP AR" instruction is executed, the contents of the address stack register specified by the stack pointer are transferred to the address register, and the stack pointer is incremented by one. (3) Indirect branch instruction ("BR @AR") When the "BR @AR" instruction is executed, the program execution branches to a program memory address specified by the contents of the address register. The branch addresses that can be specified by the address register are 0000H-0FFFH. (4) Indirect subroutine call instruction ("CALL @AR") When the "CALL @AR" instruction is executed, the subroutine at the program memory address specified by the contents of the address register can be called. The first addresses of the subroutine that can be specified by the address register are 0000H-0FFFH. (5) Address register increment instruction ("INC AR") This instruction increments the contents of the address register by one each time it is executed. Since the address register is configured of 12 bits, its contents become "0000H" when the "INC AR" instruction is executed with the contents of the address register being "0FFFH". 5.2.3 Address register and data buffer The address register can transfer data through the data buffer as a part of the peripheral hardware. For details, refer to 9. DATA BUFFER (DBF). 34 PD17072,17073 5.3 Bank Register (BANK) 5.3.1 Configuration of bank register Figure 5-3 shows the configuration of the bank register. As shown in this figure, the bank register consists of 4 bits of address 79H (BANK) of the system register. Note, however, that the higher 3 bits are always fixed to "0"; therefore, this register actually serves as a 1-bit register. Figure 5-3. Bank Register Configuration Address Name Symbol Bit b3 79H Bank register (BANK) BANK b2 b1 b0 Data 0 0 0 At reset Power-ON Clock stop CE 0 0 0 5.3.2 Function of bank register The bank register selects a bank of the data memory. Table 5-1 shows the value of the bank register and how a bank of the data memory is specified. Since the bank register exists on the system register, its contents can be rewritten regardless of the currently specified bank. In other words, the current bank status has nothing to do with manipulation of the bank register. Table 5-1. Specifying Bank of Data Memory Bank register (BANK) b3 ------ Bank of data memory b0 0 1 BANK0 BANK1 b2 ------ b1 ------ 0 0 0 0 0 0 35 PD17072,17073 5.4 Program Status Word (PSWORD) 5.4.1 Configuration of program status word Figure 5-4 shows the configuration of the program status word. As shown in this figure, the program status word consists of a total of 5 bits: the least significant bit of address 7EH (RPL) and 4 bits of 7FH (PSW) of the system register. However, bit 0 of 7FH is always fixed to 0. Each of the 5 bits in the program status word has its own function as a BCD flag (BCD), compare flag (CMP), carry flag (CY), zero flag (Z), respectively. Figure 5-4. Program Status Word Configuration Address Name Symbol Bit b0 7EH 7FH Program status word (PSWORD) PSW b0 B C D b0 C M P b2 C Y 0 b2 Z b0 (RP) RPL b2 b2 Data At reset Power-ON Clock stop CE 0 0 0 0 0 0 36 PD17072,17073 5.4.2 Functions of program status word The program status word sets conditions, under which the ALU (Arithmetic Logic Unit) performs arithmetic or transfer operations, and indicates the results of the operations. Table 5-2 outlines the function of each flag of the program status word. For details, refer to 7. ALU (Arithmetic Logic Unit) BLOCK. Table 5-2. Functional Outline of Each Flag of Program Status Word (RP) RPL b3 b2 b1 Program status word (PSWORD) PSW b0 B C D b3 C M P b2 C Y b1 Z b0 0 Flag name Zero flag (Z) Function Indicates that the result of arithmetic operation is 0. Condition under which this flag is set differs depending on contents of compare flag. Indicates occurrence of carry or borrow as a result of executing addition or subtraction instruction. Reset (0) when carry or borrow does not occur. Set (1) when carry or borrow occurs. Also used as shift bit of "RORC r" instruction. Stores or does not store result of arithmetic operation in data memory or general register. 0: Stores result 1: Does not store result Executes arithmetic operation in decimal. 0: Executes binary operation 1: Executes decimal operation Carry flag (CY) Compare flag (CMP) BCD flag (BCD) 5.4.3 Notes on using program status word When an arithmetic operation (addition or subtraction) instruction is executed to the program status word, the result of the arithmetic operation is stored in the program status word. Even if an operation that generates a carry has been executed, for example, if the result of the operation is 0000B, 0000B is stored in PSW. 5.5 Notes on Using System Register The data in the system register which are fixed to "0" are not influenced even when a write instruction is executed. When these data are read, "0" is always read. 37 PD17072,17073 6. GENERAL REGISTERS (GR) 6.1 Outline of General Registers With the PD17073, the general registers are fixed at row address 0 of BANK0 on the data memory, and consist of 16 nibbles (16 x 4 bits) of 00H through 0FH. The 16 nibbles of the row address 0 specified as the general registers can perform operations and data transfer with the data memory with a single instruction. In other words, operations and data transfer between data memory areas can be executed with a single instruction. The general registers can be controlled by data memory manipulation instructions, like the other data memory areas. Figure 6-1. Outline of General Registers Column address 0 0 1 1 2 3 4 5 6 7 8 9 A B C D E F General registers Transfer, operation Row address 2 3 4 Data memory 5 6 7 BANK0 BANK1 System registers 38 PD17072,17073 6.2 Address Creation of General Register with Each Instruction The following paragraphs 6.2.1 and 6.2.2 describe how the address of the general register is created when each instruction is executed. For details of the operation of each instruction, refer to 7. ALU (Arithmetic Logic Unit) BLOCK. 6.2.1 Addition ("ADD r, m", "ADDC r, m"), subtraction ("SUB r, m", "SUBC r, m"), logical operation ("AND r, m", "OR r, m", "XOR r, m"), direct transfer ("LD r, m", "ST m, r"), rotate processing ("RORC r") instructions Table 6-1 shows the address of general register "R" specified by an instruction operand "r". The operand "r" specifies only the column address. Table 6-1. Address Creation of General Register Bank b3 b2 b1 b0 Row address Column address b2 b1 b0 b3 b2 b1 b0 General register address R Fixed to 0 Fixed to 1 r 6.2.2 Indirect transfer ("MOV @r, m", "MOV m, @r") instructions Table 6-2 shows the address of the general register "R" specified by instruction operand "r", and the indirect transfer address specified by "@R". Table 6-2. Address Creation of General Register Bank b3 b2 b1 b0 Row address Column address b2 b1 b0 b3 b2 b1 b0 General register address R Fixed to 0 Fixed to 0 r Indirect transfer address @R Fixed to 0 Fixed to 0 Contents of R 6.3 Notes on Using General Register There is no instruction available that performs an operation between the general register and immediate data. To perform an operation between the data memory specified as the general register and immediate data, the data memory must be treated as data memory instead of as the general register. 39 PD17072,17073 7. ALU (ARITHMETIC LOGIC UNIT) BLOCK 7.1 General Figure 7-1 shows the configuration of the ALU block. As shown in the figure, the ALU block consists of an ALU, temporary registers A and B, program status word, decimal adjuster circuit, and data memory address control circuit. The ALU performs arithmetic operation, judgment, comparison, rotation, and transfer of 4-bit data on the data memory. Figure 7-1. Outline of ALU Block Data bus Address control Temporary register A Temporary register B Program status word Carry/borrow/zero detection/decimal/storage Data memory ALU * Arithmetic operation * Logical operation * Bit judgment * Comparison * Rotation * Transfer Decimal adjuster circuit 40 PD17072,17073 7.2 Configuration and Function of Each Block 7.2.1 Functions of ALU The ALU performs arithmetic operation, logical operation, bit judgment, comparison, rotation, and transfer of 4bit data as the instruction specified by the program. 7.2.2 Temporary registers A and B Temporary registers A and B temporarily stores 4-bit data. These registers are automatically used when an instruction is executed and cannot be controlled by program. 7.2.3 Program status word The program status word controls the operations of the ALU and stores the status of the ALU. For details, refer to 5.4 Program Status Word (PSWORD). 7.2.4 Decimal adjuster circuit When the BCD flag of the program status word is set to 1 during an arithmetic operation, the result of the operation is converted into decimal numbers by the decimal adjuster circuit. 7.2.5 Address control circuit The address control circuit specifies an address of the data memory. 7.3 ALU Processing Instructions Table 7-1 shows the operations of the ALU when each instruction is executed. Table 7-2 shows the decimal adjusted data when a decimal operation is performed. 41 PD17072,17073 Table 7-1. ALU Processing Instruction List Difference of operation due to program status word (PSWORD) ALU function Instruction Value of BCD flag ---------------------------------------------------------------------------------------------------- Value of CMP flag 0 Operation Stores result of binary addition Operation of CY flag Set if carry or borrow occurs; otherwise, reset Operation of Z flag Set if result of operation is 0000B; otherwise, reset Addition ADD r, m m, #n4 r, m ADDC m, #n4 0 0 1 Does not store result of binary operation Stores result of decimal operation Retains status if result of operation is 0000B; otherwise, reset Set if result of operation is 0000B; otherwise, reset Subtraction SUB r, m m, #n4 r, m SUBC m, #n4 1 0 1 1 Does not store result of decimal operation No change Retains previous status Retains status if result of operation is 0000B; otherwise, reset Retains previous status Logical operation r, m OR m, #n4 r, m AND m, #n4 r, m XOR m, #n4 Any (retained) Any (retained) Judgment SKT SKF SKE m, #n m, #n Any (retained) Any (reset) No change Retains previous status Retains previous status Comparison SKNE SKGE SKLT m, #n4 Any (retained) m, #n4 m, #n4 m, #n4 r, m m, r m, #n4 Any (retained) Any (retained) No change Retains previous status Retains previous status Transfer LD ST Any (retained) No change Retains previous status Retains previous status MOV @r, m m, @r Rotation RORC r Any (retained) Any (retained) No change Value of b0 of general register Retains previous status 42 PD17072,17073 Table 7-2. Decimal Adjusted Data Hexadecimal addition CY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Result of operation 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B Decimal addition CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Result of operation 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1110B 1111B 1100B 1101B 1110B 1111B 1100B 1101B 1010B 1011B 1100B 1101B Result of operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 Decimal subtraction CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Result of operation 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1100B 1101B 1110B 1111B 1100B 1101B 1110B 1111B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B Result of operation Hexadecimal subtraction CY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Result of operation 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Remark The shaded part indicates that decimal adjustment is not made correctly. 43 PD17072,17073 7.4 Notes on Using ALU 7.4.1 Notes on executing operation to program status word When an arithmetic operation is performed to the program status word, the result of the operation is stored in the program status word. The CY and Z flags of the program status word are usually set or reset according to the result of an arithmetic operation executed. However, if the program status word itself is used for an operation, the result of the operation is stored in the program status word, making it impossible to judge whether a carry or borrow occurs, or the result of the operation is zero. However, if the CMP flag is set, the result of the operation is not stored in the program status word; consequently, the CY and Z flags are set (1) or cleared (0) normally. 7.4.2 Notes on using decimal operation A decimal operation can be executed only if the result of the operation falls within the following range: (1) Result of addition must be 0 to 19 in decimal. (2) Result of subtraction must be 0 to 9 or -10 to -1 in decimal. If a decimal operation is executed exceeding this range, the CY flag is set, and the result is 1010B (0AH) or higher. 44 PD17072,17073 8. PERIPHERAL CONTROL REGISTERS 8.1 Outline of Peripheral Control Registers Figure 8-1 outlines the peripheral control registers. Thirty-two 4-bit peripheral registers are available that control the peripheral hardware such as the PLL frequency synthesizer, serial interface, and intermediate frequency counter (IF). Because the peripheral control registers are located on the data memory, they can be manipulated by all the data memory manipulation instructions. Figure 8-1. Outline of Peripheral Control Registers Column address 0 0 1 1 2 3 4 5 6 7 8 9 A B C D E F BANK0 B BANK1 C D E F 0 1 Data memory 2 3 4 Peripheral control register System registers 5 6 7 Row address 2 3 4 5 6 7 Peripheral hardware 45 PD17072,17073 8.2 Configuration and Function of Peripheral Control Registers Figure 8-2 shows the configuration of the peripheral control registers. Table 8-1 lists the peripheral hardware control functions of the peripheral control registers. As shown in Figure 8-2, the peripheral control registers consist of a total of 32 nibbles (32 x 4 bits) of addresses 50H through 6FH of BANK1. Each peripheral control register has an attribute of 1 nibble, and is classified into four types: read/write (R/W), readonly (R), write-only (W), and read-and-reset (R&Reset) registers. Nothing is changed even if data is written to the read only (R and R&Reset) registers. If a write-only (W) register is read, the value is undefined. Of the 4-bit data of 1 nibble, the bits fixed to "0" are always "0" when read, and also "0" when data is written to these bits. Caution Bit 3 of address 50H of BANK1 (bit 3 of the LCD driver display start register) is allocated to a test mode area. Therefore, do not write "1" to this bit. 46 PD17072,17073 [MEMO] 47 PD17072,17073 Figure 8-2. Configuration of Peripheral Control Registers (1/2) (BANK1) Column address Row address Item LCD driver Name display start register A D C O 0N L C D E N Basic timer 0 CE pin status carry register detection register B T M 0 0C0 Y Port 1A Stack pointer pull-down resistor select register P 1 A P L D 1 P 1 A P L0 D 0 SS PP 10 0 0 0 System clock Interrupt edge Interrupt enable register 0 1 2 3 4 5 6 7 select register select register S Y S C 0K Note 5 Symbol 0 0 0 0 CPP E11 AA PP 0 LL DD 32 IBI III NTE PPP TMG SB 1 IT 0 C 0OM K 1 Read/ Write R/W R&Reset R R/W R/W R/W R/W R/W Serial I/O Name Serial I/O IF counter mode select register S I O C K 0 I F C M D 1 I F C M D 0 I F C C K 1 I F C C K 0 mode select clock select register S I O S E L S I O H I Z S I O T S register S I O C 0K 1 IF counter gate status detection register I F C G 0 0 0 IF counter control register I F C S T R T I F C R E S PLL mode select register P L L M 0D 1 P L L M D 0 PLL PLL reference data register frequency select register P L L R 0F C K 2 P L L R F C K 1 P L L R F C K 0 P L L R 1 7 P L L R 1 6 P L L R 1 5 P L L R 1 4 6 Symbol 0 0 0 0 0 Read/ Write R/W R/W R/W R W R/W R/W R/W Note This is a test mode area. Do not write "1" to this area. 48 PD17072,17073 Figure 8-2. Configuration of Peripheral Control Registers (2/2) 8 9 A B C D E F INT pin interrupt request register I R Q 0 0 0 Basic timer 1 Serial interface BEEP clock A/D converter interrupt interrupt request select register channel select request register register register I R Q B 0T0 M 1 I R Q S 0I0 O B E E P 00 C K 1 R/W B E E P 00 C K 0 A D C C 0H 1 A D C C H 0 A/D converter A/D converter reference compare start voltage setting register register A D C R F S E L 3 A D C R F S E L 2 A D C R F S E L 1 A D C R F0 S E L 0 A/D converter compare result detection register A D C C 0M P 0 0 0 0 A D C S 0T0 R T 0 R/W R/W R/W R/W R/W R/W R PLL data register PLL data set register PLL unlock FF register Port 0B bit I/O Port 0C bit I/O select register select register P 0 B B I O 3 P 0 B B I O 2 P 0 B B I O 1 P 0 B B I O 0 P 0 D B I O 3 P 0 D B I O 2 P 0 C B I O 1 P 0 C B I O 0 PPPPPPPP LLLLLLLL LLLLLLLL RRRRRRRR 11119876 3210 P L L R 5 P L L R 4 P L L R 3 P L L R 2 P L L R 10 0 0 0 0 P L L P 0U0 T 0 P L L U 0L R/W W R&Reset R/W R/W 49 PD17072,17073 Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (1/4) Peripheral hardware Name Control register Address Read/ b3 Write b2 Symbol b1 b0 Stack Stack pointer (SP) (BANK1) 54H R/W 0 --------- Peripheral hardware control function Functional outline Set value At reset Power- Clock CE ON stop 0 Fixed to 0 1 2 2 2 0 - - - - - - - - -- - - - - - - - -- - - - - - - - -- - - - - - - -- SP1 --------- Stack pointer SP0 Timer Basic timer 0 carry register (BANK1) 51H R& 0 ----------------- Fixed to 0 0 1 1 Reset 0 0 ------------------------------------------------------------ BTM0CY Interrupt Interrupt edge select register (BANK1) 56H R/W 0 INT BTM1CK IEG Interrupt enable register (BANK1) 57H R/W 0 IPSIO --------- Detects status of carry FF Fixed to 0 Detects status of INT Pin Sets set time interval of IRQBTM1 flag Sets interrupt issuing edge of INT pin Fixed to 0 Serial interface Basic timer 1 INT pin Fixed to 0 Enables interrupt Reset Set 0 0 0 ------------------------------------------------------------ Low level High level ------------------------------------------------------------ 32 ms (31.25 Hz) 8 ms (125 Hz) Rising edge Falling edge 0 Disables interrupt Enables interrupt 0 0 ------------------------------------------------------------ ------------------------------------------------------------ IPBTM1 --------- IP INT pin interrupt request register (BANK1) 58H R/W 0 --------- 0 0 0 0 --------- 0 ------------------------------------------------------------ IRQ Basic timer 1 interrupt request register (BANK1) 59H R/W 0 --------- Detects interrupt request of INT pin Fixed to 0 Not requested Requested 0 0 0 0 --------- 0 ------------------------------------------------------------ IRQBTM1 Serial interface interrupt request register (BANK1) 5AH R/W 0 --------- Detects interrupt request of basic timer 1 Not requested Fixed to 0 Requested 0 0 0 0 --------- 0 ------------------------------------------------------------ IRQSIO Pin CE pin status detection register (BANK1) 52H R 0 --------- Detects interrupt of serial interface Fixed to 0 Not requested Requested - - - 0 --------- 0 ------------------------------------------------------------ CE Port 1A pull-down (BANK1) select register 53H R/W P1APLD3 --------- Detects status of CE pin P1A3 P1A2 P1A1 P1A0 Selects pull-down resistor of these pins Low level Resistor ON High level Resistor OFF 0 R R P1APLD2 --------- P1APLD1 --------- P1APLD0 Remark -: Determined by status of pin, R: Previous status is retained. 50 PD17072,17073 Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (2/4) Peripheral hardware Name Control register Address Read/ b3 Write b2 Symbol b1 b0 PLL PLL mode select (BANK1) 65H R/W 0 --------- Peripheral hardware control function Functional outline Set value At reset Power- Clock CE ON stop 0 Fixed to 0 1 0 0 R frequency register synthesizer 0 ----------------------------------------------------------- PLLMD1 --------- Sets division mode of PLL PLLMD0 PLL reference frequency select register (BANK1) 66H R/W 0 --------- 0 0 Disable 0 1 1 0 1 1 MF VHF HF 0 0 R Fixed to 0 0:1 kHz 1:3 kHz 2:5 kHz 3:6.25 kHz 4:12.5 kHz 5:25 kHz 6, 7: PLL disable ----------------------------------------------------------- PLLRFCK2 Sets reference frequency of PLL PLLRFCK1 --------- PLLRFCK0 PLL data register (BANK1) 67H R/W PLLR17 - - - -- - - - - Sets division ratio of PLL PLLR16 --------- PLLR15 - - - - - - - -- PLLR14 (BANK1) 68H PLLR13 - - - -- - - - - * In direct division mode PLLR6-PLLR17: Valid data PLLR1-PLLR5: don't care 0-15 (000H-00FH): Setting prohibited 16-212 - 1 (010H-FFFH): Can be setNote * In pulse swallow mode PLLR1-PLLR17: Valid data 0-1023 (0000H-03FFH): Setting prohibited 17 1024-2 - 1 (0400H-1FFFFH): Note Can be set U R R PLLR12 --------- PLLR11 - - - - - - - -- PLLR10 (BANK1) 69H PLLR9 - - - -- - - - - PLLR8 --------- PLLR7 - - - - - - - -- PLLR6 (BANK1) 6AH PLLR5 - - - -- - - - - PLLR4 --------- PLLR3 - - - - - - - -- PLLR2 (BANK1) 6BH PLLR1 ------------------------------------------------------------ 0 --------- Fixed to 0 0 --------- 0 PLL data set register (BANK1) 6CH W 0 --------- Fixed to 0 0 0 0 0 --------- 0 ------------------------------------------------------------ PLLPUT PLL unlock FF register (BANK1) 6DH R& 0 ----------------- Data transfer to programmable counter Fixed to 0 Does not transfer Transfers U R R Reset 0 0 ------------------------------------------------------------ PLLUL Detects status of unlock FF Locked status Unlocked status Note For the details of the set value, refer to Figure 15-4 Configuration of PLL Data Register. Remark U: Undefined, R: Previous status is retained. 51 PD17072,17073 Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (3/4) Peripheral hardware Name Control register Address Read/ b3 Write b2 Symbol b1 b0 A/D A/D converter (BANK1) 5CH R/W 0 --------- Peripheral hardware control function Functional outline Set value At reset Power- Clock CE ON stop 0 Fixed to 0 1 0 0 0 converter channel select register 0 ------------------------------------------------------------ ADCCH1 --------- Selects pin used for A/D converter ADCCH0 A/D converter reference voltage setting register A/D converter compare start register (BANK1) 5EH R/W (BANK1) 5DH R/W ADCRFSEL3 Sets compare voltage - - - -- - - - - 0 0 1 1 Not used AD0 AD1 AD1 0 1 0 1 0 VREF = x + 0.5 x VDD (V) 16 (0 x 0FH) 0 0 ADCRFSEL2 - - - -- - - - - ADCRFSEL1 - - - -- - - - - ADCRFSEL0 0 --------- Fixed to 0 0 0 0 0 --------- 0 ------------------------------------------------------------ ADCSTRT A/D converter compare result detection register (BANK1) 5FH R 0 --------- Starts A/D converter operation/checks comparator operation Fixed to 0 Invalid/Stop Starts/operates 0 0 0 0 --------- 0 ------------------------------------------------------------ ADCCMP Generalpurpose port Port 0B bit I/O select register (BANK1) 6EH R/W P0BBIO3 - - - -- - - - - Detects compare result P0B3 pin P0B2 pin P0B1 pin P0B0 pin P0D3 pin P0D2 pin P0C1 pin P0C0 pin Fixed to 0 Sets I/O mode of these pins (bit I/O) VADCIN < VREF Input VADCIN > VREF Output 0 0 0 P0BBIO2 - - - -- - - - - P0BBIO1 - - - -- - - - - P0BBIO0 Port 0C bit I/O select register (BANK1) 6FH R/W P0DBIO3 - - - -- - - - - P0DBIO2 - - - -- - - - - P0CBIO1 - - - -- - - - - P0CBIO0 Serial interface Serial I/O mode select register (BANK1) 60H R/W 0 SIOSEL 0 Serial output 0 0 ------------------------------------------------------------ Selects serial I/O mode of P0B3/SI/SO1 pin Serial input ------------------------------------------------------------ SIOHIZ Sets P1C0/SO0 pin in serial output mode General-purpose Serial output output port ------------------------------------------------------------ SIOTS Serial I/O clock select register (BANK1) 61H R/W 0 --------- Sets start or stop of operation Fixed to 0 Stops operation Starts operation 0 0 0 0 ------------------------------------------------------------ SIOCK1 --------- Sets clock of serial interface SIOCK0 0 0 1 1 External clock 12.5 kHz 18.75 kHz 37.5 kHz 0 1 0 1 52 PD17072,17073 Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (4/4) Peripheral hardware Name Control register Address Read/ b3 Write b2 Symbol b1 b0 IF counter IF counter mode select register (BANK1) 62H R/W IFCMD1 --------- Peripheral hardware control function Functional outline Set value At reset Power- Clock CE ON stop 0 Sets mode of IF counter 0 0 0 1 ms 0 Fixed to 0 1 0 1 0 4 ms 0 1 0 1 8 ms 1 1 1 1 Open 1 0 0 0 0 0 0 IFCMD0 IFCCK1 --------- IF counter OFF FMIFC pin AMIFC pin FMIFC pin (General I/O port) FMIF mode AMIF mode AMIF mode ------------------------------------------------------------ Sets gate time of IF counter IFCCK0 IF counter gate status detection register (BANK1) 63H R 0 --------- 0 --------- 0 ------------------------------------------------------------ IFCG IF counter control (BANK1) register 64H W 0 --------- Detects opening/closing gate of IF counter Fixed to 0 Closed Open 0 0 0 0 ------------------------------------------------------------ IFCSTRT IFCRES BEEP BEEP clock select register (BANK1) 5BH R/W 0 --------- Starts counting of IF counter Resets IF counter Fixed to 0 Does not start Does not reset Starts Resets 0 0 R ------------------------------------------------------------ 0 ------------------------------------------------------------ BEEP0CK1 Sets output status of BEEP pin --------- 0 0 1 1 General output port General output port BEEP (low-level output) BEEP BEEP0CK0 LCD LCD driver (BANK1) 50H R/W 0 --------- (high-level output) (1.5 kHz) (3 kHz) 0 Fixed to 0 1 0 1 controller/ display start driver register 0 ---------------------------------------------------------------------- ADCONNote Sets A/D converter power supply and --------- 0 0 1 1 LCDEN Standby System clock select register (BANK1) 55H R/W 0 --------- ON/OFF of all LCD display Fixed to 0 Power OFF Power ON Power ON Power ON Display OFF Display ON Display OFF Display ON 0 0 0 0 0 R 0 R R ----------- 0 1 0 1 0 --------- 0 ------------------------------------------------------------ SYSCK Selects system clock (1 instruction execution time) 53.3 s 106.6 s Note When LCDEN= 1, the power supply for the A/D converter is ON even if ADCON = 0. Remark R: Previous status is retained. 53 PD17072,17073 9. DATA BUFFER (DBF) 9.1 General Figure 9-1 outlines the data buffer. The data buffer is located on the data memory and has the following two functions: (1) Reads constant data on program memory (table reference) (2) Transfers data with hardware peripherals Figure 9-1. Outline of Data Buffer Data buffer Data write (PUT instruction) Table reference (MOVT instruction) Data read (GET instruction) Peripheral hardware Constant data Program memory 54 PD17072,17073 9.2 Data Buffer 9.2.1 Configuration of data buffer Figure 9-2 shows the configuration of the data buffer. As shown in this figure, the data buffer is configured of 16 bits of addresses 0CH-0FH of BANK0 on the data memory. Of these 16 bits, bit 3 of address 0CH is the MSB, while bit 0 of address 0FH is the LSB. Since the data buffer is on the data memory, it can be manipulated by all the data memory manipulation instructions. Figure 9-2. Configuration of Data Buffer 0 0 1 Row address 2 3 1 2 3 4 5 Column address 6 7 8 9A Data buffer (DBF) B C D E F Data memory 4 5 6 7 7 System register BANK0 BANK1 Address Data memory Bit Bit Symbol Data buffer Data M S B 0CH 0DH 0EH 0FH b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DBF3 DBF2 DBF1 DBF0 L S B Data 55 PD17072,17073 9.2.2 Table reference instruction ("MOVT DBF, @AR") When this instruction is executed, the contents of the program memory addressed by the contents of the address register are incorporated into the data buffer. The program memory addresses to which table reference can be executed are addresses 0000H-0FFFH, i.e., all the addresses of the program memory. 9.2.3 Peripheral hardware control instructions ("PUT" and "GET") The operations of the "PUT" and "GET" instructions are as follows: (1) GET DBF, p Reads the data of the peripheral register addressed by p to the data buffer. (2) PUT p, DBF Sets the data of the data buffer to the peripheral register addressed by p. 9.3 List of Peripheral Hardware and Data Buffer Functions Table 9-1 lists the peripheral hardware and data buffer functions. 9.4 Notes on Using Data Buffer When transferring data with the peripheral hardware through the data buffer, keep in mind the following three points in respect with the unused peripheral addresses, write-only peripheral registers (only when using PUT), and readonly peripheral registers (only when using GET): (1) An "undefined value" is read when a write-only register is read. (2) Nothing is changed even when data is written to a read-only register. (3) An "undefined value" is read when an unused address is read. Nothing is changed when data is written to this address. Table 9-1. Relation between Peripheral Hardware and Data Buffer Peripheral hardware Peripheral register transferring data with data buffer Name Symbol Peripheral Execution address of PUT/GET instruction 03H PUT/ GET PUT/ GET GET No. of data buffer I/O bits 8 No. of actual bits 8 Function Outline Serial interface Presettable shift register Address register SIOSFR Sets serial out data and reads serial in data Transfers data with address register Reads count value of IF counter Address register (AR) IF counter AR 40H 16 12 IF counter data register IFC 43H 16 16 56 PD17072,17073 10. GENERAL-PURPOSE PORT The general-purpose ports output high or low floating signals to external circuits, and reads high or low level signals from external circuits. 10.1 General Table 10-1 shows the relations between each port and port register. The general-purpose ports are classified into I/O ports, input ports, and output ports. The I/O port is the bit I/O ports, which can be set in the input or output mode in 1-bit (1-pin) units. Table 10-1. Relations between Each Port (Pin) and Port Register Port No. 56-pin 64-pin QFP Port 0A 5 TQFP 6 P0A3 Output BANK0 70H P0A Pin Symbol I/O Bank Data setting method Port register (data memory) Address Symbol Bit symbol (reserved word) b3 b2 b1 b0 I/O (bit I/O) 71H P0B b3 b2 b1 b0 72H P0C b3 b2 ---------------------------- Remarks ---------------------------------------------------------- P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 - - P0C1 P0C0 P0D3 P0D2 - - P1A3 P1A2 P1A1 P1A0 P1B3 P1B2 P1B1 P1B0 - - - Fixed to "0" Fixed to "0" ------------ ------------ ------------ 4 3 4 3 P0A2 P0A1 2 Port 0B 56 55 54 53 Port 0C No pin 2 64 63 62 61 P0A0 P0B3 P0B2 P0B1 P0B0 ---------------------------------------------------------- ------------ ------------ ------------ ------------ - - - - - - - -- - - - - - - - -- -- - - - - - - - - - - - - - - - - - - 15 14 Port 0D 17 17 16 19 P0C1 P0C0 P0D3 I/O (bit I/O) I/O (bit I/O) 73H P0D b1 b0 b3 - - - - - - - - - - - - - - - - - - -- ------------ - - - - - - - - - - - - - - - - - - -- ------------ - - - - - - - -- - - - - - - - -- -- - - - - - - - - - - - - - - - - - - ------------ ---------------------------- 16 18 P0D2 b2 No pin b1 Fixed to "0" b0 Port 1A 13 12 11 10 Port 1B 9 8 7 6 Port 1C No pin 15 14 13 11 10 9 8 7 P1A3 P1A2 P1A1 P1A0 P1B3 P1B2 P1B1 P1B0 72H P1C Output 71H P1B Input BANK1 70H P1A b3 b2 b1 b0 b3 b2 b1 b0 ---------------------------------------------------------- ------------ ------------ ------------ ---------------------------------------------------------- ------------ ------------ ------------ b3 b2 b1 ------------ ------------ ---------------------------- - - - - - - - -- - - - - - - - -- -- - - - - - - - - - - - - - - - - - - 1 1 P1C0 Output 73H - b0 b3 ----- P1C0 - Test mode area. Do not write "1" to this area. b2 ----- b1 ----- b0 57 PD17072,17073 10.2 General-Purpose I/O Ports (P0B, P0C, P0D) 10.2.1 Configuration of I/O ports The configurations of the I/O ports are shown below. P0B (P0B3, P0B2, P0B1, P0B0) P0C (P0C1, P0C0) P0D (P0D3, P0D2) VDD I/O mode selector flag Output latch Write instruction Port register (1 bit) VDD 1 0 Read instruction RESET 10.2.2 Use of I/O ports The I/O port is set in the input or output mode by the I/O select registers P0B and P0C of the control register. P0D, P0C, and P0D are the bit I/O ports. Therefore, these ports can set in input or output mode in 1-bit units. To set output data or to read input data, data is written to the corresponding port register, or an instruction that reads the data is executed. 10.2.3 describes the configuration of the I/O select register of each port. 10.2.4 describes how to use an I/O port as an input port. 10.2.5 describes how to use an I/O port as an output port. 58 PD17072,17073 10.2.3 Control register of I/O port The port 0B bit I/O select register sets the input or output mode of each pin of P0B. The port 0C bit I/O select register sets the input or output mode of each pin of P0C and P0D. The following paragraphs (1) and (2) describe the configuration and function. (1) Port 0B bit I/O select register Flag symbol Name b3 P 0 B B I O 3 b2 P 0 B B I O 2 b1 P 0 B B I O 1 b0 P 0 B B I O 0 Address Read/ Write Port 0B bit I/O select register (BANK1) 6EH R/W Sets input or output mode 0 1 Sets P0B0 in input mode Sets P0B0 in output mode Sets input or output mode 0 1 Sets P0B1 in input mode Sets P0B1 in output mode Sets input or output mode 0 1 Sets P0B2/SCK in input mode Sets P0B2/SCK in output mode Sets input or output mode 0 1 Sets P0B3/SI/SO1 in input mode Sets P0B3/SI/SO1 in output mode Power-ON At reset Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 59 PD17072,17073 (2) Port 0C bit I/O select register Flag symbol Name b3 P 0 D B I O 3 b2 P 0 D B I O 2 b1 P 0 C B I O 1 b0 P 0 C B I O 0 Address Read/ Write Port 0C bit I/O select register (BANK1) 6FH R/W Sets input or output of port 0 1 Sets P0C0 pin in input mode Sets P0C0 pin in output mode Sets input or output of port 0 1 Sets P0C1 pin in input mode Sets P0C1 pin in output mode Sets input or output of port 0 1 Sets P0D2/AMIFC pin in input mode Sets P0D2/AMIFC pin in output mode Sets input or output of port 0 1 Sets P0D3/FMIFC/AMIFC pin in input mode Sets P0D3/FMIFC/AMIFC pin in output mode Power-ON At reset Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 60 PD17072,17073 10.2.4 To use I/O port in input mode The port pin to be used in the input mode is selected by the I/O select register of each port. The pin set in the input mode is floated (Hi-Z) and waits for the input of an external signal. The input data can be read by executing a read instruction (such as SKT instruction) to the port register corresponding to each pin. "1" is read from the port register when the high level is input to the corresponding pin, and "0" is read from the register when the low level is input to the pin. If a write instruction (such as MOV instruction) is executed to the port register corresponding to a port set in the input mode, the contents of the output latch are rewritten. 10.2.5 To use I/O Port in output mode The port pin to be set in the output mode is selected by the I/O select register corresponding to the port. The pin set in the output mode outputs the contents of the output latch. The output data is set by executing a write instruction (such as MOV instruction) to the port register corresponding to each pin. To output the high level to each pin, "1" is written to the port register, and to output the low level, "0" is written. The port pin can be floated (Hi-Z) by setting it in the input mode. If a read instruction (such as SKT) is executed to the port register corresponding to a port set in the output mode, the contents of the output latch are read. 10.2.6 I/O port status on reset (1) On power-ON reset All the ports are set in the input mode. The contents of the output latch become 0. (2) On CE reset All the ports are set in the input mode. The contents of the output latch are retained. (3) On execution of clock stop instruction All the ports are set in the input mode. The contents of the output latch are retained. Increasing current consumption can be prevented due to noise of the input buffer, by using the RESET signal, as described in 10.2.1. (4) In halt status The previous status is retained. 61 PD17072,17073 10.3 General-Purpose Input Ports (P1A) 10.3.1 Configuration of input ports The configuration of the input ports is illustrated below. P1A (P1A3, P1A2, P1A1, P1A0) To A/D converter Write instruction VDD Port register (1 bit) Read instruction RESET High ON resistance P1APLD3 P1APLD2 P1APLD1 P1APLD0 62 PD17072,17073 10.3.2 Using input port The input data can be read by executing an instruction that reads the contents of the port register P1A (such as SKT instruction). "1" is read from each bit of the port register when the high level is input to the corresponding port pin, and "0" is read when the low level is input. Nothing is changed even if a write instruction (such as MOV) is executed to the port register. Port 1A can be connected to or disconnected from a pull-down resistor bitwise by software. Whether the pull-down resistor is connected or disconnected is specified by the port 1A pull-down resistor select register. Figure 10-1 shows the configuration and function of the port 1A pull-down resistor select register. Figure 10-1. Configuration of Port 1A Pull-Down Resistor Select Register Flag symbol Name b3 P 1 A Port 1A pull-down P resistor select register L D 3 L D 2 L D 1 L D 0 P P P 53H b2 P 1 A b1 P 1 A b0 P 1 A (BANK1) Address Read/ Write R/W Selects ON/OFF of pull-down resistor of P1A0 pin 0 1 Pull-down resistor ON Pull-down resistor OFF Selects ON/OFF of pull-down resistor of P1A1 pin 0 1 Pull-down resistor ON Pull-down resistor OFF Selects ON/OFF of pull-down resistor of P1A2/AD0 pin 0 1 Pull-down resistor ON Pull-down resistor OFF Selects ON/OFF of pull-down resistor of P1A3/AD1 pin 0 1 Pull-down resistor ON Pull-down resistor OFF Power-ON At reset Clock stop CE 0 0 0 0 Retained Retained 63 PD17072,17073 10.3.3 Reset status of input port (1) On power-ON reset All pins are specified as a input port. Pulled down internally. (2) On CE reset All pins are specified as a input port. The previous status of the pull-down resistor is retained. (3) On execution of clock stop instruction All pins are specified as a input port. The previous status of the pull-down resistor is retained. (4) In halt status The previous status is retained. 64 PD17072,17073 10.4 General-Purpose Output Ports (P0A, P1B, P1C) 10.4.1 Configuration of output ports The configurations of the output ports are shown below. P0A (P0A3, P0A2, P0A1, P0A0) P1B (P1B3, P1B2, P1B1, P1B0) P1C (P1C0) VDD Output latch Write instruction Port register (1 bit) Read instruction 10.4.2 Using output port The output port outputs the contents of the output latch from its pins. The output data is set by executing an instruction that writes data to the port register corresponding to each pin (such as MOV instruction). "1" is written to each bit of the port register when the high level is output to the corresponding port pin, and "0" is written when the low level is output. If a read instruction (such as SKT instruction) is executed to the port register, the contents of the output latch are read. 10.4.3 Reset status of output port (1) On power-ON reset All the pins output the contents of the output latch. The contents of the output latch become 0. (2) On CE reset Retains the contents of the output latch. The contents of the output latch are retained; therefore, the output data is not changed on CE reset. (3) On execution of clock stop instruction Retains the contents of the output latch. The contents of the output latch are retained; therefore, the output data is not changed on execution of the clock stop instruction. Initialize the port through program as necessary. (4) In halt status The contents of the output latch are output. The contents of the output latch are retained; therefore, the output data is not changed in the halt status. 65 PD17072,17073 11. INTERRUPT 11.1 General Figure 11-1 shows the outline of the interrupt block. As shown in this figure, the interrupt block temporarily stops the program under execution, and branches to an interrupt vector address according to an interrupt request output by each peripheral hardware. The interrupt block consists of "interrupt control blocks" that control interrupt requests output from the corresponding peripheral hardware, "interrupt enable flip-flop" that enables all the interrupts, "stack pointer" that is controlled when an interrupt is accepted, "address stack register", "program counter", and "interrupt stack". The "interrupt control block" of each peripheral hardware consists of an "interrupt request flag (IRQxxx)" that detects each interrupt, "interrupt enable flag (IPxxx)" that enables each interrupt, and "vector address generator (VAG)" that specifies each vector address when an interrupt is accepted. The following peripheral hardware have the interrupt functions: * INT pin * Basic timer 1 * Serial interface Figure 11-1. Outline of Interrupt Block Interrupt control block IPSIO flag Program counter Serial interface IRQSIO flag Vector address generator 01H Stack pointer Address stack register IPBTM1 flag Bank register Basic timer 1 IRQBTM1 flag Vector address generator 02H Interrupt stack IP flag INT pin IRQ flag Vector address generator 03H DI, EI instruction Interrupt enable flip-flop 66 PD17072,17073 11.2 Interrupt Control Block An interrupt control block is available for each peripheral hardware. Each of these blocks detects the presence/ absence of an interrupt request, enables/disables the interrupt, and generates a vector address when the interrupt is accepted. 11.2.1 Interrupt request flag (IRQxxx) The interrupt request flags are set to (1) when an interrupt request has been issued from the corresponding peripheral hardware, and is cleared (0) when the interrupt has been accepted. Therefore, even when the interrupt is not enabled, whether an interrupt request has been issued can be detected by checking these interrupt request flags. Writing "1" directly to an interrupt request flag is equivalent to issuance of an interrupt request. Once this flag has been set, it will not be cleared until the corresponding interrupt has been accepted, or "0" is written to the flag by an instruction. If two or more interrupt requests are issued at the same time, the interrupt request flag corresponding to the interrupt request that has not been accepted is not cleared. The interrupt request flags are address 58H through 5AH of BANK1 of RAM. Figures 11-2 through 11-4 show the configuration and functions of each interrupt request register. Figure 11-2. Configuration of INT Pin Interrupt Request Register Flag symbol Name b3 INT pin interrupt request register b2 b1 b0 I R Q Address Read/ Write 0 0 0 (BANK1) 58H R/W Sets interrupt request issuing status of INT pin. 0 1 Interrupt request not issued. Interrupt request issued. Fixed to "0". Power-ON At reset Clock stop CE 0 0 0 0 0 0 67 PD17072,17073 Figure 11-3. Configuration of Basic Timer 1 Interrupt Request Register Flag symbol Name b3 b2 b1 b0 I R Q B T M 1 Address Read/ Write Basic timer 1 interrupt request register 0 0 0 (BANK1) 59H R/W Sets interrupt request issuing status of basic timer 1. 0 1 Interrupt request not issued. Interrupt request issued. Fixed to "0". Power-ON At reset Clock stop CE 0 0 0 0 0 0 Figure 11-4. Configuration of Serial Interface Interrupt Request Register Flag symbol Name b3 b2 b1 b0 I R Q S I O Address Read/ Write Serial interface interrupt request register 0 0 0 (BANK1) 5AH R/W Sets interrupt request issuing status of serial interface. 0 1 Interrupt request not issued. Interrupt request issued. Fixed to "0". Power-ON At reset Clock stop CE 0 0 0 0 0 0 68 PD17072,17073 11.2.2 Interrupt enable flag (IPxxx) Each interrupt enable flag enables or disables the interrupt request of the corresponding peripheral hardware. So that an interrupt is accepted, all the following three conditions must be satisfied: * The interrupt must be enabled by the corresponding interrupt enable flag. * The interrupt request must be issued from the corresponding interrupt request flag. * The "EI" instruction (which enables all the interrupts) must be executed. The interrupt enable flags are located on the interrupt enable registers on the register file. Figure 11-5 shows the configuration and functions of the interrupt enable register. Figure 11-5. Configuration of Interrupt Enable Register Flag symbol Name b3 b2 I P S I O b1 I P B T M 1 b0 I P (BANK1) 57H Address Read/ Write Interrupt enable register 0 R/W Enables interrupt from INT pin 0 1 Disables interrupt Enables interrupt Enables interrupt from basic timer 1 0 1 Disables interrupt Enables interrupt Enables interrupt from serial interface 0 1 Disables interrupt Enables interrupt Fixed to 0 Power-ON At reset Clock stop CE 0 0 0 0 0 0 0 0 0 0 69 PD17072,17073 11.2.3 Vector address generator (VAG) When an interrupt request from peripheral hardware has been accepted, the vector address generator generates a branch address (vector address) to which the program execution is to be branched. The vector addresses corresponding to each interrupt source are listed in Table 11-1. Table 11-1. Vector Address of Each Interrupt Source Interrupt source INT pin Basic timer 1 Serial interface Vector address 03H 02H 01H 11.3 Interrupt Stack Register 11.3.1 Configuration and functions of interrupt stack register Figure 11-6 shows the configuration of the interrupt stack register. The interrupt stack saves the contents of the bank registers when an interrupt has been accepted: When an interrupt has been accepted, and the contents of bank registers have been saved to the interrupt stack, the contents of the registers are reset to "0". The interrupt stack can save up to one level of the contents of the bank registers; therefore, multiplexed interrupt cannot be performed. The contents of the interrupt stack register are restored to the respective system registers when an interrupt return ("RETI") instruction has been executed. Caution With the PD17073, the contents of the program status word (PSWORD) are not saved to the stack but retained when an interrupt is accepted. Therefore, the contents of the program status word must be backed up by software. Figure 11-6. Configuration of Interrupt Stack Register Interrupt stack register (INTSK) Name Bit 0H b3 _ Bank stack b2 _ b1 _ b0 Remark -: Bit not saved 70 PD17072,17073 11.3.2 Operations of interrupt stack Figure 11-7 illustrates the operations of the interrupt stack. When multiplexed interrupts have been accepted, the first contents saved to the stack are popped. If these contents are necessary, therefore, they must be saved through program. Figure 11-7. Operations of Interrupt Stack (a) If interrupt level does not exceed 1 Undefined BANK1 BANK1 Application of VDD Interrupt A (BANK1) RETI (b) If interrupt level exceeds 1 BANK1 BANK0 BANK0 BANK0 Interrupt A (BANK1) Interrupt B (BANK0) RETI RETI 71 PD17072,17073 11.4 Stack Pointer, Address Stack Register, and Program Counter The address stack register saves the return address to which the program execution is to restore when execution exits from an interrupt service routine. The stack pointer specifies the address of the address stack register. When an interrupt has been accepted, therefore, the value of the stack pointer is decremented by one, and the value of the program counter at that time is saved to the address stack register specified by the stack pointer. Next, when dedicated instruction "RETI" has been executed after the interrupt service routine has been executed, the contents of the address stack register specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. Also refer to 3. ADDRESS STACK (ASK). 11.5 Interrupt Enable Flip-Flop (INTE) The interrupt enable flip-flop enables all the interrupts. When this flip-flop is set, all the interrupts are enabled. When it is reset, all the interrupts are disabled. This flip-flop is set or reset by dedicated instruction "EI (set)" or "DI (reset)". The "EI" instruction sets this flip-flop when the instruction next to it has been executed, while the "DI" instruction resets the flip-flop while it is executed. When an interrupt has been accepted, this flip-flop is automatically reset. This flip-flop is reset on power-ON reset, execution of the clock stop instruction, or CE reset. 72 PD17072,17073 11.6 Accepting Interrupt 11.6.1 Interrupt accepting operation and priority An interrupt is accepted in the following sequence: (1) Each peripheral hardware issues an interrupt request signal to an interrupt request block when a certain condition is satisfied (for example, when a falling signal has been input to the INT pin). (2) Each interrupt request block sets the corresponding interrupt request flag (e.g., IRQ flag for the INT pin) to "1" when it has received an interrupt request signal from peripheral hardware. (3) When the interrupt request flag is set, the interrupt request block whose interrupt enable flag (e.g., IP flag for IRQ flag) is set to "1" outputs "1". (4) The signal output by the interrupt request block is ORed with the output of the interrupt enable flip-flop and an interrupt accept signal is output. This interrupt enable flip-flop can be set to "1" by the EI instruction and reset to "0" by the DI instruction. When "1" is output from an interrupt request block with the interrupt enable flip-flop set to "1", the interrupt enable flip-flop outputs "1" and the interrupt is accepted. When the interrupt has been accepted, the output of the interrupt enable flip-flop is input to the block that has issued the interrupt request, through an AND circuit, as shown in Figure 11-1. The signal input to the block that has issued the interrupt request clears the interrupt request flag of that block to "0", and a vector address corresponding to the interrupt is output. If any of the blocks that have issued an interrupt request outputs "1" at this time, the interrupt accept signal is not transmitted to the next stage. When two or more interrupt request have generated at the same time, therefore, the interrupts are accepted according to the following priority: INT pin > basic timer 1 > serial interface The interrupt corresponding to an interrupt source is not accepted unless the interrupt enable flag is set to "1". Therefore, by clearing the interrupt enable flag to "0", an interrupt with a high hardware priority can be disabled. 73 PD17072,17073 11.6.2 Timing to accept interrupt Figure 11-8 is a timing chart illustrating how interrupts are accepted. (1) (a) in this figure illustrate how one type of interrupt is accepted. in (1) indicates the case where the interrupt request flag is set to "1" last, while (b) shows the case where the interrupt enable flag is set to "1" last. In either case, the interrupt is accepted after all the interrupt request flag, interrupt enable flip-flop, and interrupt enable flag have been set. If it is during the first instruction cycle of the "MOVT DBF, @AR" instruction or an instruction with the skip condition satisfied that sets the last flag or flip-flop to "1", the interrupt is accepted during the second instruction cycle of the "MOVT DBF, @AR" instruction or when the skipped instruction ("NOP") has been executed. The interrupt enable flip-flop is set in the instruction cycle next to the one in which the "EI" instruction is executed. (2) in Figure 11-8 shows the timing chart where two or more interrupts are used. When using two or more interrupts, the interrupt given the highest hardware priority at that time is accepted if all the interrupt enable flags are set. However, the hardware priority can be changed by manipulating the interrupt enable flag through program. "Interrupt cycle" in Figure 11-8 is a special cycle in which the interrupt request flag is clear, a vector address is specified, and the contents of the program counter are saved after an interrupt has been accepted, and lasts for 53.3 s, (normal operation) or one instruction execution time. For details, refer to 11.7 Operations after Accepting Interrupt. 74 PD17072,17073 Figure 11-8. Interrupt Accepting Timing Chart (1/2) (1) When one type of interrupt (e.g., rising edge of INT pin) is used (a) When there is no time to mask interrupt by interrupt enable flag (IPxxx) <1> If an ordinary instruction which is not "MOVT" or does not satisfy the skip condition is executed when interrupt is accepted Instruction EI MOV POKE WR, #0001B INTPM1, WR Ordinary instruction Interrupt cycle INTE INT pin IRQ flag IP flag 1 instruction cycle 53.3 s (normal operation) Interrupt service routine Interrupt accepted Interrupt enable period <2> If "MOVT" or an instruction that satisfies the skip condition is executed when interrupt is accepted Instruction EI MOV POKE WR, #0001B INTPM1, WR MOVT DBF,@AR skip instruction Interrupt cycle INTE INT pin IRQ flag IP flag Interrupt enable period Interrupt service routine Interrupt accepted (b) When there is interrupt pending time by interrupt enable flag Instruction EI Interrupt POKE MOV cycle WR, #0001B INTPM1, WR INTE INT pin IRQ flag IP flag Interrupt pending period Interrupt service routine Interrupt accepted 75 PD17072,17073 Figure 11-8. Interrupt Accepting Timing Chart (2/2) (2) When two or more interrupts are used (e.g., INT pin and basic timer 1) (a) Hardware priority Instruction INTE INT pin IRQ flag Basic timer 1 IRQBTM1 flag IP flag IPBTM1 flag INT pin interrupt pending period INT pin interrupt service routine MOV POKE WR, #0011B INTPM1, WR EI Interrupt cycle EI RETINote Interrupt cycle Basic timer 1 interrupt pending period INT pin interrupt accepted Basic timer 1 interrupt service Basic timer 1 interrupt accepted (b) Software priority Instruction INTE INT pin IRQ flag Basic timer 1 IRQBTM1 flag IP flag IPBTM1 flag INT pin interrupt pending period Basic timer 1 interrupt service routine MOV POKE WR, #0010B INTPM1, WR EI Interrupt cycle MOV POKE WR, #0011B INTPM1, WR EI RETINote Interrupt cycle Basic timer 1 interrupt pending period Basic timer 1 interrupt accepted INT pin interrupt service INT pin interrupt accepted Note Because the level of the interrupt stack is 1, multiplexed interrupt cannot be performed. 76 PD17072,17073 11.7 Operations after Accepting Interrupt When an interrupt has been accepted, the following processing is automatically executed in sequence: (1) The interrupt enable flip-flop and the interrupt request flag corresponding to the accepted interrupt request are cleared to "0". Therefore, the interrupt is disabled. (2) The contents of the stack pointer are decremented by one. (3) The contents of the program counter are saved to the address stack register specified by the stack pointer. At this time, the content of the program counter is the program memory address next to the one at which the interrupt has been accepted. For example, if the interrupt has been accepted while a branch instruction is executed, the branch destination address is loaded to the program counter. If a subroutine call instruction is executed when the interrupt has been accepted, the address that called the subroutine is loaded to the program counter. When the skip condition of a skip instruction is satisfied, the next instruction is treated as a no-operation instruction ("NOP") and then the interrupt is accepted. Consequently, the contents of the program counter are the skipped address. (4) The lower 1 bit of the bank register (BANK) is saved to the interrupt stack. Caution At this time, the contents of the program status word (PSWORD) are not saved. Save the contents of the program status word by software as necessary. (5) The contents of the vector address generator corresponding to the accepted interrupt are transferred to the program counter. Therefore, the execution branches to an interrupt service routine. The above steps (1) through (5) are executed in one special instruction cycle (53.3 s: normal operation) that does not involve execution of an ordinary instruction. This instruction cycle is called an interrupt cycle. Therefore, it takes the CPU one instruction cycle to branch to the corresponding vector address after it has accepted an interrupt. 77 PD17072,17073 11.8 Exiting from Interrupt Service Routine To return to the service that was executed when the interrupt was accepted from the interrupt service routine, a dedicated instruction "RETI" is used. When this instruction is executed, the following processing is automatically executed in sequence: (1) The contents of the address stack register specified by the stack pointer are restored to the program counter. (2) The contents of the interrupt stack are restored to the lower 1 bit of the bank register (BANK). Caution If the contents of the program status word are saved in the program, its contents must be restored to the program status word at the same time. (3) The contents of the stack pointer are incremented by one. The processing (1) through (3) above is executed in one instruction cycle during which the "RETI" instruction is executed. The only difference between the "RETI" and subroutine return instructions "RET" and "RETSK" is the restore operation of each system register described in step (2) above. 78 PD17072,17073 11.9 External (INT Pin) Interrupts 11.9.1 Outline of external interrupts Figure 11-9 outlines the external interrupts. As shown in this figure, an interrupt request for an external interrupt is issued at the rising or falling edge of the signal input to the INT pin. Whether the interrupt request is to be issued at the rising or falling edge of INT is specified independently through program. The INT pin is Schmitt trigger input pin to protect malfunctioning due to noise. This pin do not accept a pulse input that lasts for less than 100 ns. Figure 11-9. Outline of External Interrupt INT flag IEG flag Interrupt control block INT pin Edge detection block Schmitt trigger IRQ flag Remark INT: detects pin status IEG: selects interrupt edge 11.9.2 Edge Detection Block The edge detection block specifies the edge (rising or falling edge) of the input signal that issues the external interrupt request of the INT pin, and detects the specified edge. The edge is specified by IEG flag. Figure 11-10 shows the configuration and function of the interrupt edge select register. 79 PD17072,17073 Figure 11-10. Configuration of Interrupt Edge Select Register Flag symbol Name b3 b2 I N Interrupt edge select 0 register 1 C K 56H T b1 B T M b0 I E G (BANK1) Address Read/ Write R/W Sets input edge to issue interrupt request of INT pin 0 1 Rising edge Falling edge Sets time interval at which IRQBTM1 flag is setNote 0 1 32 ms (31.25 Hz) 8 ms (125 Hz) Detects status of INT pin 0 1 Low level is input to INT pin High level is input to INT pin Fixed to "0" Power-ON At reset Clock stop CE 0 0 0 0 0 0 0 0 0 0 Note For the function of the BTM1CK flag, refer to 12.3.1 Outline of basic timer 1. Note that as soon as the interrupt request issuing edge is changed by the IEG flag, the interrupt request signal may be issued. Suppose that the IEG flag is set to "1" (specifying the falling edge) and that a high level is input to the INT pin, as shown in Table 11-2. If the IEG flag is cleared at this time, the edge detector circuit judges that a rising edge has been input, and issues an interrupt request. 80 PD17072,17073 Table 11-2. Issuing Interrupt Request By Changing IEG Flag Changes in IEG flag 10 (falling) 01 (rising) (falling) (rising) INT pin status Low level High level Low level High level Interrupt request Not issued Issued Issued Not issued IRQ flag status Retains previous status Set to "1" Set to "1" Retains previous status 11.9.3 Interrupt control block The level of a signal input to the INT pin can be detected by using the INT flag. This flag is set or cleared independently of interrupts; therefore, it can be used as a 1-bit general-purpose input port when the interrupt function is not used. The INT flag can also be used as a general-purpose port that can detect the rising or falling edge by reading an interrupt request flag if the interrupt corresponding to the flag is not enabled. In this case, however, the interrupt request flag is not automatically cleared and must be cleared by program. Also refer to Figure 11-10. 11.10 Internal Interrupt Two internal interrupt sources, basic timer 1, and serial interface, are available. 11.10.1 Interrupt by basic timer 1 This interrupt request is issued at fixed time intervals. For details, refer to 12. TIMER. 11.10.2 Interrupt by serial interface This interrupt request is issued when a serial output or serial input operation has been completed. For details, refer to 14. SERIAL INTERFACE. 81 PD17072,17073 12. TIMER The timers are used to control the program execution time. 12.1 General As shown in this figure, the PD17013 is provided with the following two timers: * Basic timer 0 * Basic timer 1 The basic timer 0 is used to detect the status of a flip-flop that is set at fixed time intervals. The basic timer 1 is used to issue an interrupt request at fixed time intervals. The basic timer 0 can also be used to detect a power failure. The clock of each timer is generated by dividing the system clock (75 kHz). 12.2 Basic Timer 0 12.2.1 General Figure 12-1 outlines the basic timer 0. The basic timer 0 is used as a timer by detecting the status of a flip-flop which is set at fixed time intervals, by using the BTM0CY flag (BANK1 of RAM: address 51H, bit 0). The content of the flip-flop corresponds to the BTM0CY flag on a one-to-one basis. The set time for BTM0CY flag (BTM0CY flag set pulse) is 125 ms (8 Hz). If the BTM0CY flag is read for the first time after power-ON reset, its content is always "0". After that, the flag is set to "1" at fixed time intervals. If the CE pin goes high, CE reset is effected when the BTM0CY flag is set next time. By reading the content of the BTM0CY flag at system reset (power-ON reset and CE reset), therefore, a power failure can be detected. For details on power failure detection, refer to 20. RESET. Figure 12-1. Outline of Basic Timer 0 75 kHz Divider 125 ms (8 Hz) Basic timer 0 carry FF Set/clear BTM0CY flag Remark BTM0CY (bit 0 of basic timer 0 carry register: refer to Figure 12-2) detects the status of the flip-flop. 82 PD17072,17073 12.2.2 Flip-flop and BTM0CY flag The flip-flop is set at fixed time intervals and its status is detected by the BTM0CY flag of the basic timer 0 carry register. The BTM0CY flag is a read-only flag, and is reset to "0" if its contents are read (Read & Reset) by using the instructions shown in Table 12-1. The BTM0CY flag is reset to "0" at power-ON reset, and is set to "1" at CE reset and at CE reset after the clock stop instruction is executed. Therefore, this flag can be used as a power failure detection flag. The BTM0CY flag is not set until its contents are read by the instruction shown in Table 12-1 after application of the supply voltage. Once a read instruction has been executed, this flag is set at fixed time intervals. Figure 12-2 shows the configuration and function of the basic timer 0 carry register. Table 12-1. Instructions to Reset BTM0CY Flag Mnemonic ADD ADDC SUB SUBC AND OR XOR SKE SKEG SKLT SKNE Operand m, #n4 Mnemonic ADD ADDC SUB SUBC AND OR XOR LD SKT SKF MOV @r, m m, @rNote m, #n Operand r, m Note When the row address of m is 5H and 1H is written to r. Remark m = 51H 83 PD17072,17073 Figure 12-2. Configuration of Basic Timer 0 Carry Register Flag symbol Name b3 b2 b1 b0 B T M 0 C Y Address Read/ Write Basic timer 0 carry register 0 0 0 (BANK1) 51H R&Reset Detects status of flip-flop. 0 1 Flip-flop is not set. Flip-flop is set. Fixed to "0". Power-ON At reset Clock stop CE 0 0 0 0 1 1 12.2.3 Application example of basic timer 0 An example of a program in which the basic timer 0 is used is shown below. In this example, processing A is executed every 1 second. Example M1 LOOP: BANK1 SKT1 BR ADD SKT1 BR BTM0CY NEXT M1, #0010B CY NEXT Processing A NEXT: Processing B BR LOOP ; Executes processing B and branches to LOOP ; Adds 2 to M1 ; Executes processing A if CY flag is "1" ; Branches to NEXT if CY flag is "0" ; Branches to NEXT if BTM0CY flag is "0" MEM 1.10H ; 1-second counter, set to bank 1 84 PD17072,17073 12.2.4 Error of basic timer 0 The time at which the BTM0CY flag is to be detected must be shorter than the time at which the BTM0CY flag is to be set (refer to 12.2.5 Notes on using basic timer 0). Where the time interval at which the BTM0CY flag is to be detected is tCHECK and the time interval at which the BTM0CY flag is to be set (125 ms) is tSET, the relation between tCHECK and tSET must be as follows: tCHECK < tSET At this time, as shown in Figure 12-3, the timer error when the BTM0CY flag is detected is: 0 < error < tSET Figure 12-3. Error of Basic Timer 0 due to Detection Time of BTM0CY Flag BTM0CY flag setting pulse H L tSET 1 BTM0CY flag 0 tCHECK1 SKT1 BTM0CY <1> tCHECK2 SKT1 BTM0CY <2> SKT1 BTM0CY <3> tCHECK3 SKT1 BTM0CY <4> As shown in Figure 12-3, the timer is updated because the BTM0CY flag is detected as "1" in <2>. In <3>, the flag is "0"; therefore, the timer is not updated until the BTM0CY flag is detected again in <4>. At this time, the time of the timer is extended by tCHECK3. 85 PD17072,17073 12.2.5 Notes on using basic timer 0 (1) BTM0CY flag detection time interval The time interval at which the BTM0CY flag is to be detected must be shorter than the time interval at which the flag is to be set. This is because, if the time of processing B in Figure 12-4 is longer than the time interval at which the BTM0CY flag is to be set, the BTM0CY flag is not set accurately. Figure 12-4. Detection of BTM0CY Flag and BTM0CY Flag BTM0CY flag setting pulse H L 1 <1> <2> <3> <4> <5> BTM0CY flag 0 SKT1 BTM0CY SKT1 BTM0CY SKT1 BTM0CY Processing A Processing B Because execution time of processing B is too long after BTM0CY flag, which has been set to "1" in step <2> above, has been detected, BTM0CY flag is not detected in step <3>. (2) Sum of timer updating processing time and BTM0CY flag detection time interval As described in (1) above, the time interval tCHECK at which the BTM0CY flag is to be detected must be shorter than the time at which the BTM0CY flag is to be set. At this time, even if the time interval at which the BTM0CY flag is to be detected is short, the timer processing may not be executed normally when CE reset is effected if the updating processing time of the timer is long. Therefore, the following conditions must be satisfied: tCHECK + tTIMER < tSET where, tCHECK: time interval at which BTM0CY flag is detected tTIMER: timer updating processing time tSET: time interval at which BTM0CY flag is set An example is shown below. 86 PD17072,17073 Example Timer updating processing and BTM0CY flag detection time interval BTIMER: BANK1 SKT1 BTM0CY BR BR AAA: Processing A BR BTIMER AAA BTIMER Timer updating ; Executes timer updating processing if BTM0CY flag is "1". ; Branches to AAA if BTM0CY flag is "0". The following is the timing chart of the above program. CE pin H L BTM0CY flag setting pulse H L 1 BTM0CY flag 0 BTM0CY detection interval tCHECK Timer updating processing tTIMER If this timer updating processing time is too long, CE reset is effected while processing is in progress. SKT1 BTM0CY SKT1 BTM0CY CE reset 87 PD17072,17073 (3) Adjusting basic timer 0 at CE reset An example of adjusting the basic timer 0 at CE reset is shown on the next page. As shown in this example, the timer may have to be adjusted if the BTM0CY flag is used for power failure detection and, at the same time, the flag is used for a watch timer. When the power is applied the first time (power-ON reset), the BTM0CY flag is cleared to "0", and not set until the contents of the flag is read again by an instruction shown in Table 12-1. If the CE pin goes high, CE reset is effected in synchronization with rising edge of the BTM0CY flag setting pulse. At this time, the BTM0CY flag is set to "1" and starts. Therefore, it can be judged, when system reset (power-ON reset or CE reset) has been effected, whether the system reset is power-ON reset or CE reset, by checking the status of the BTM0CY flag. That is, if the BTM0CY flag is "0", power-ON reset has been effected; if the flag is "1", CE reset has been effected (for power failure detection). At this time, the watch timer must continue its operation even when CE reset has been effected. However, because the BTM0CY flag is cleared to "0" as a result of reading the BTM0CY flag to detect a power failure, the set (1) status of the BTM0CY flag is overlooked once. Consequently, it is necessary to update the watch timer if CE reset has been detected as a result of power failure detection. For details on power failure detection, refer to 20.6 Power Failure Detection. Example Adjusting timer at CE reset (to detect power failure and update watch by BTM0CY flag) START: Processing A ; <1> BANK1 SKT1 BR BACKUP: ; <2> Updates watch 125 ms. ; Adjusts watch because this is back up (CE reset) LOOP: ; <3> Processing B SKF1 BR BR INITIAL: Processing C BR LOOP ; Initialization of ports and peripheral hardware. BTM0CY BACKUP LOOP ; While performing processing B, ; tests BTM0CY flag and updates watch. BTM0CY INITIAL ; Embedded macro ; Tests BTM0CY flag. ; If BTM0CY is "0", branches to INITIAL (power failure detection). ; Program address 0000H Figure 12-5 shows the timing chart of the above program. 88 PD17072,17073 Figure 12-5. Timing Chart VDD 3V 0V H L H L H L 1 0 A <1> C <3> B <3> Watch UP Power application Power-ON reset starts from address 0. BTM0CY flag detection B <3> B B B B B <3> <3> Watch UP B B <3><3> Watch UP CE reset starts from address 0. BTM0CY flag is detected. Time updated because flag is set to 1. Point B Point C Point D Point E B A <1> B B B CE Internal pulse 8 Hz BTM0CY flag setting pulse BTM0CY flag Program processing Program instruction <3> <3> <3> Watch UP <3> <3> Watch UP Point A As shown in Figure 12-5, the program is started from address 0000H in synchronization with the rising of the internal 8-Hz pulse when supply voltage VDD is applied first. When the BTM0CY flag is detected next at point A, the BTM0CY flag is cleared to 0 because power has been just applied. It is therefore judged that a power failure (i.e., power-ON reset) has been detected, and "processing C" is executed. Because the content of the BTM0CY flag has been read once at point A, the BTM0CY flag is set to 1 every 125 ms afterward. Next, even if the CE pin goes low at point B and goes high at point C, the program executes "processing B" and increments the watch, unless the clock stop instruction is executed. Because the CE pin goes high at point C, CE reset is effected at point D where the BTM0CY flag setting pulse rises, and the program is started from address 0000H. At this time, if the BTM0CY flag is detected at point E, it is judged that back up (CE reset) has been effected, because the BTM0CY flag is set to 1. As is evident from the above figure, the watch is delayed by 125 ms each time CE reset is effected, unless the watch is updated 125 ms at point E. If processing A takes 125 ms or longer when a power failure is detected at point E, setting of the BTM0CY flag is overlooked two times; therefore, processing A must be completed within 125 ms. Therefore, the BTM0CY flag must be detected for a power failure detection within the BTM0CY flag setting time after the program has been started from the address 0000H. 89 PD17072,17073 (4) If detection of BTM0CY flag overlaps with CE reset As described in (3), the CE reset is effected as soon as the BTM0CY flag has been set to 1. If the BTM0CY flag read instruction happens to be executed at the same time as the CE reset, the BTM0CY flag read instruction takes precedence. Therefore, if setting of the BTM0CY flag after the CE pin has gone high overlaps with the BTM0CY flag read instruction, the CE reset is effected when "the BTM0CY flag is set next time". This operation is illustrated in Figure 12-6. Figure 12-6. Operation when CE Reset and BTM0CY Flag Read Instruction Overlap CE pin BTM0CY flag setting pulse BTM0CY flag H L H L 1 0 SKT 1 BTM0CY BTM0CY flag setting pulse BTM0CY flag Instruction H L 1 0 SKT1 BTM0CY Embedded macro SKT .MF. BTM0CY SHR4, #.DF. BTM0CY AND 0FH If BTM0CY flag is read during this period, CE is delayed. SKT 1 BTM0CY CE reset 53.3 s Originally, program starts from address 0000H here. However, because it happens to overlap with a program that reads BTM0CY, CE reset is not effected. In a program that cyclically detects the BTM0CY flag, in which the BTM0CY flag detection time interval coincides with the BTM0CY flag setting time, CE reset is never effected. 90 PD17072,17073 12.3 Basic Timer 1 12.3.1 General Figure 12-7 outlines the basic timer 1. The basic timer 1 issues an interrupt request at fixed time interval and sets the IRQBTM1 flag to 1. The time interval of the IRQBTM1 flag is set by the BTM1CK flag of the interrupt edge select register. Figure 128 shows the configuration and function of the interrupt edge select register. The interrupt generated by the basic timer 1 is accepted when the IRQBTM1 flag is set, if the EI instruction has been issued and the IPBTM1 flag has been set (refer to 11. INTERRUPT). Figure 12-7. Outline of Basic Timer 1 BTM1CK flag Internal signal 75 kHz (fixed) 32 ms (31.25 Hz) Divider 8 ms (125 Hz) Selector IRQBTM1 set signal Remark BTM1CK (bit 1 of interrupt edge select register. Refer to Figure 12-8) set the time interval at which the IRQBTM1 flag is set. 91 PD17072,17073 Figure 12-8. Configuration of Interrupt Edge Select Register Flag symbol Name b3 b2 I N Interrupt edge 0 select register 1 C K 56H T b1 B T M b0 I E G (BANK1) Address Read/ Write R/W Sets input edge to issue interrupt request of INT pinNote 0 1 Rising edge Falling edge Sets time interval at which IRQBTM1 flag is set 0 1 32 ms (31.25 Hz) 8 ms (125 Hz) Detects status of INT pinNote 0 1 Low level is input to INT pin. High level is input to INT pin. Fixed to "0". Power-ON At reset Clock stop CE 0 0 0 0 0 0 0 0 0 0 Note For the functions of IEG and INT flags, refer to 11.9 External (INT pin) Interrupt. 92 PD17072,17073 12.3.2 Application example of basic timer 1 A program example is shown below. Example M1 MEM 0.10H 0002H START M1, #0001B CY EI_RETI M1, #0110B ; 80-ms counter ; Symbol definition of basic timer 1 interrupt vector address ; Branches to START ; Program address (0002H) ; Adds 1 to M1 ; Tests CY flag ; Returns if no carry BTIMER1 DAT BR ORG BTIMER1 ADD SKT1 BR MOV EI_RETI: EI RETI START: MOV BANK1 SET1 SET1 EI LOOP: BANK0 Processing A M1, #0110B BTM1CK IPBTM1 ; Initializes contents of M1 to 6 ; Embedded macro ; Sets basic timer 1 interrupt pulse to 8 ms ; Enables basic timer 1 interrupt ; Enables all interrupts Processing B BR LOOP This program executes processing A every 80 ms. The points to be noted in this case are that the DI status is automatically set when an interrupt has been accepted, and that the IRQBTM1 flag is set to 1 even in the DI status. This means that the interrupt is accepted even if execution exits from an interrupt service routine by execution of the "RETI" instruction, if processing A takes longer than 8 ms. Consequently, processing B is not executed. 93 PD17072,17073 12.3.3 Error of basic timer 1 As described in 12.3.2, the interrupt generated by basic timer 1 is accepted each time the basic timer 1 interrupt pulse falls, if the EI instruction has been executed, and if the interrupt has been enabled. Therefore, an error of basic timer 1 occurs only when any of the following operations are performed: * When the first interrupt after basic timer 1 interrupt has been enabled has been accepted * When the time interval at which the IRQBTM1 flag is to be set is changed, i.e., when the first interrupt is accepted after the interrupt pulse has been changed * When data has been written to the IRQBTM1 flag Figure 12-9 shows an error in each of the above operations. Figure 12-9. Error of Basic Timer 1 (1/2) (a) When interrupt by basic timer 1 is enabled Basic timer 1 interrupt pulse IRQBTM1 flag IPBTM1 flag INTE FF H L 1 0 1 0 EI DI EI Interrupt pending tSET EI EI <3> Interrupt accepted Interrupt accepted <1> <2> SET1 IPBTM1 Interrupt accepted At point <1> in the above figure, the interrupt by basic timer 1 is accepted as soon as the interrupt is enabled. At this time, the error is -tSET. If an interrupt is enabled by the "EI" instruction at the next point <3>, the interrupt occurs at the falling edge of the basic timer 1 interrupt pulse. At this time, the error is: -tSET < error < 0 94 PD17072,17073 Figure 12-9. Error of Basic Timer 1 (2/2) (b) When basic timer 1 interrupt pulse is changed Internal pulse A Internal pulse B Basic timer 1 interrupt pulse IRQBTM1 flag IPBTM1 flag INTE FF H L H L H L 1 0 1 0 EI DI EI EI <3> Basic timer 1 interrupt EI EI <1> Basic timer 1 interrupt pulse changed pulse changed Interrupt accepted Interrupt accepted <2> Interrupt accepted Even if the basic timer 1 interrupt pulse is changed to B at point <1> in the above figure, the interrupt is accepted at the next point <2> because the basic timer 1 interrupt pulse does not fall. If the basic timer 1 interrupt pulse is changed to A at <3>, the interrupt is immediately accepted because the basic timer 1 interrupt pulse falls. (c) When IRQBTM1 flag is manipulated Basic timer 1 interrupt pulse IRQBTM1 flag IPBTM1 flag INTE FF H L 1 0 1 0 EI DI EI Interrupt accepted EI <1> SET1 IRQBTM1 <2> CLR1 IRQBTM1 Interrupt not accepted Interrupt accepted EI Interrupt accepted The interrupt is immediately accepted if the IRQBTM1 flag is set to 1 at <1>. If clearing the IRQBTM1 flag to 0 overlaps with the falling of the basic timer 1 interrupt pulse at <2>, the interrupt is not accepted. 95 PD17072,17073 12.3.4 Notes on using basic timer 1 When creating a program, such as a program for watch, in which processing is always performed at fixed time intervals by using the basic timer 1 after the supply voltage has been once applied (power-ON reset), the basic timer 1 interrupt service must be completed in a fixed time. Let's take the following example: Example M1 MEM 0.10H 0002H START M1, #0001B CY EI_RETI M1, #0110B ; 80-ms counter ; Symbol definition of interrupt vector address of basic timer 1 ; Branches to START ; Program address (0002H) ; Adds 1 to M1 ; Watch processing if carry occurs ; Restores if no carry occurs BTIMER1 DAT BR ORG BTIMER1 ADD SKT1 BR MOV ; <1> Processing B EI_RETI: EI RETI START: MOV BANK1 SET1 BTM1CK ; Embedded macro ; Sets time of interrupt by basic timer 1 to 8 ms SET1 EI LOOP: Processing A BR LOOP IPBTM1 ; Embedded macro ; Enables interrupt by basic timer 1 ; Enables all interrupts M1, #0110B ; Initializes contetns of M1 to 6 In this example, processing B is executed every 80 ms while processing A is executed. If the CE pin goes high as shown in Figure 12-10, CE reset is effected in synchronization with the rising of the BTM0CY flag setting pulse. If issuance of an interrupt request by the basic timer 1 happens to overlap with the setting of the BTM0CY flag at this time, CE reset takes precedence. When CE reset is effected, the basic timer 1 interrupt request (IRQBTM1) flag is cleared. Consequently, the timer processing is skipped once. 96 PD17072,17073 Figure 12-10. Timing Chart CE pin BTM0CY flag setting pulse Basic timer 1 interrupt pulse H L H L H L Basic timer 1 interrupt Because BTM0CY flag setting pulse rises, CE reset is effected here. As a result, basic timer 1 interrupt is skipped once. 97 PD17072,17073 13. A/D CONVERTER 13.1 General Figure 13-1 outlines the A/D converter. The A/D converter compares an analog voltage input to the AD0 or AD1 pins with the internal compare voltage, judge the comparison result via software, and converts the analog signal into a 4-bit digital signal. The comparison result can be detected by the ADCCMP flag. As the comparison method, successive approximation is employed. Figure 13-1. Outline of A/D Converter ADCCH1 flag ADCCH0 flag P1A2/AD0 P1A3/AD1 Input selector block Compare block Set/reset ADCCMP flag Compare voltage generator block (R-string D/A converter) Remarks 1. ADCCH0 and ADCCH1 (bits 0 and 1 of A/D converter channel select register. Refer to Figure 134) select the pin used for the A/D converter. 2. ADCCMP (bit 0 of A/D converter compare result detection register. Refer to Figure 13-7) detects the result of comparison. 98 PD17072,17073 13.2 Setting A/D Converter Power Supply The PD17073 has a power supply for the A/D converter. This power supply is also used for LCD display. When using the A/D converter, therefore, the A/D converter power supply must be set to ON by using the ADCON flag of the LCD driver display start register. Figure 13-2 shows the configuration and function of the LCD driver display start register. Figure 13-2. Configuration of LCD Driver Display Start Register Flag symbol Name b3 b2 b1 A D LCD driver display 0 start register O N E N 0 C D 50H b0 L C (BANK1) Address Read/ Write R/W Turns ON/OFF A/D converter power supply and all LCD displays 0 0 1 1 0 1 0 1 A/D converter power supply OFF, LCD display OFF A/D converter power supply ON, LCD display ON A/D converter power supply ON, LCD display OFF A/D converter power supply ON, LCD display ON Fixed to "0". Power-ON At reset Clock stop CE 0 0 0 0 0 0 0 R Remark R: Retained Cautions 1. When the LCD display is ON (LCDEN = 1), the A/D converter power supply is ON regardless of the setting of the ADCON flag. 2. Bit 3 of the LCD driver display start register is a test mode area. Therefore, do not write "1" to this bit. 99 PD17072,17073 13.3 Input Selector Block Figure 13-3 shows the configuration of the input selector block. The input selector block selects the pin to be used by using the A/D converter channel select register. Two or more pins cannot be used at the same time with the A/D converter. Figure 13-4 shows the configuration and function of the A/D converter channel select register. For the configuration and function of the port 1A pull-down resistor select register, refer to Figure 10-1 Port 1A Pull-Down Resistor Select Register. Figure 13-3. Configuration of Input Selector Block ADCCH1 flag ADCCH0 flag Selector P1A2/AD0 P1A3/AD0 Compare block VADCIN Each I/O port 100 PD17072,17073 Figure 13-4. Configuration of A/D Converter Channel Select Register Flag symbol Name b3 b2 b1 A D A/D converter channel select register 0 0 C C H 1 b0 A D C C H 0 (BANK1) 5CH Address Read/ Write R/W Sets pins used for A/D converter 0 0 1 1 0 1 0 1 A/D converter is not used (general-purpose input port) P1A2/AD0 P1A3/AD1 pin P1A3/AD1 pin Fixed to "0" Power-ON At Clock stop reset CE 0 0 0 0 0 0 0 0 101 PD17072,17073 13.4 Compare Voltage Generator Block and Compare Block Figure 13-5 shows the configuration of the compare voltage generator block and compare block. The compare voltage generator block switches over the tap decoder by using 4-bit data set to the A/D converter reference voltage setting register to generate 16 steps of compare voltage VREF. In other words, this block is an R-string D/A converter. The power source of the R string is the same as VDD that is supplied to the device. The compare block judges which of the voltage VADCIN input from a pin and compare voltage VREF is greater. Data is compared by the comparator as soon as the ADCSTRT flag has been written to. One compare time of the A/D converter is equal to two instruction execution times (106.6 s in normal operation mode, and 213.2 s in the low-speed mode). By reading the content of the ADCSTRT flag, the current operating status of the comparator can be checked. The compare result is detected by the ADCCMP flag. Figure 13-6 shows the configuration and function of the A/D converter compare start register. Figures 13-7 and 13-8 show the configuration and function of the A/D converter compare result detection register and A/D converter reference voltage setting register. Table 13-1 lists the compare voltages. Figure 13-5. Configuration of Compare Voltage Generator Block and Compare Block 1/2 VDD VADCIN VREF A/D converter reference voltage setting register (ADCR) 2pF _ Comparator + ADCCMP flag Tap decoder 0 1 E F VDD 1 R 2 R R 1 R 2 Write to ADCSTRT flag 102 PD17072,17073 Figure 13-6. Configuration of A/D Converter Compare Start Register Flag symbol Name b3 b2 b1 b0 A D A/D converter compare start register 0 0 0 C (BANK1) S 5EH T R T Address Read/ Write R/W Read Write Checks operating status of comparator Sets start of compare operation by comparator 0 1 Operation stops (compare completes) Operating (analog voltage comparison in progress) Invalid Start Fixed to 0 Power-ON At reset Clock stop CE 0 0 0 0 0 0 Remarks 1. Even if the A/D converter channel select register or A/D converter reference voltage setting register is manipulated when ADCSTRT = 1 (when comparison by the comparator is in progress), the contents of the register remain unchanged. Therefore, the operating status of the A/D converter cannot be changed while the comparator is operating. 2. The ADCSTRT flag is cleared to "0" only when the voltage comparison operation by the comparator is completed or when the "STOP s" instruction is executed. 103 PD17072,17073 Figure 13-7. Configuration of A/D Converter Compare Result Detection Register Flag symbol Name b3 b2 b1 b0 A D C C M P Address Read/ Write A/D converter compare result detection register 0 0 0 (BANK1) 5FH R Detects result of comparison by A/D converter 0 1 VADCIN < VREF VADCIN > VREF Fixed to "0" Power-ON At reset Clock stop CE 0 0 0 0 0 0 104 PD17072,17073 Figure 13-8. Configuration of A/D Converter Reference Voltage Setting Register Flag symbol Name b3 A D C A/D converter reference voltage setting register R F S E L 3 b2 A D C R F S E L 2 b1 A D C R F S E L 1 b0 A D C R F S E L 0 5DH (BANK1) Address Read/ Write R/W Sets compare voltage of A/D converter 0 | x | 0FH VREF = 16 x + 0.5 x VDD (V) Power-ON At Clock stop reset CE 0 0 0 0 0 0 0 0 0 0 0 0 105 PD17072,17073 Table 13-1. Set Value of A/D Converter Reference Voltage Setting Register and Compare Voltage A/D Converter reference voltage setting register set data Decimal (DEC) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hexadecimal (HEX) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Compare voltage Logic voltage Unit: x VDD V 0.5/16 1.5/16 2.5/16 3.5/16 4.5/16 5.5/16 6.5/16 7.5/16 8.5/16 9.5/16 10.5/16 11.5/16 12.5/16 13.5/16 14.5/16 15.5/16 At VDD = 3 V Unit: V 0.094 0.281 0.469 0.656 0.844 1.031 1.219 1.406 1.594 1.781 1.969 2.156 2.344 2.531 2.719 2.906 106 PD17072,17073 13.5 Comparison Timing Chart The ADCEN flag is automatically cleared to 0 when the comparison operation has been completed. The ADCSTRT flag is reset to 0 two instructions after the ADCSTRT flag has been set. At this point, the compare result (ADCCMP flag) can be read. Figure 13-9 shows the timing chart. Figure 13-9. Timing Chart of A/D Converter's Compare Operation Instruction cycle A/D A/D converter start converter start instruction instruction NOP NOP ADCCMP read Sample & hold ADCSTRT flag ADCCMP flag Comparison result 13.6 Performance of A/D Converter Table 13-2 shows the performances of the A/D converter. Table 13-2. Performances of A/D Converter Parameter Resolution Input voltage range Quantization error Over range Error of offset, gain, and non-linearity Note Including quantization error Performance 4 bits 0-VDD 1/2 LSB 15.5/16 x VDD 3/2 LSBNote 107 PD17072,17073 13.7 Using A/D Converter 13.7.1 Comparing one reference voltage The following shows a program example. Example To compare voltage input to AD0 pin, VADCIN against reference voltage VREF (8.5/16 VDD). VADCIN > VREF, execution branches to AAA; if VADCIN < VREF, execution branches to BBB. BANK1 SET1 INITFLG INITFLG SET1 NOP NOP SKT1 BR BR ADCCMP AAA BBB ADCON ; A/D converter ON NOT ADCCH1, ADCCH0 ; P1A2/AD0 pin used as A/D converter pin ADCRFSEL3, NOT ADCRFSEL2, NOT ADCRFSEL1, NOT ADCRFSEL0 ; Sets compare voltage VREF to 8.5/16 x VDD ADCSTRT ; A/D operation starts ; Comparison in progress ; Comparison in progress ; Detects ADCCMP flag and, ; Branches to AAA if False (0) ; Branches to BBB if True (1) If 108 PD17072,17073 13.7.2 Successive comparison by means of binary search The A/D converter can compare only one reference voltage at a time. Consequently, successive comparison must be executed through program in order to convert input voltages into digital signals. If the processing time of the successive comparison program is different depending on the input voltage, it is not desirable because of the relations with the other programs. Therefore, the binary search method described in (1) through (3) below is useful. (1) Concept of binary search The following figure illustrates the concept of binary search. First, the reference voltage is set to 1/2VDD. If the result of comparison is True (high level), a voltage of 1/ 4VDD is applied; if the result is False (low level), a voltage of 1/4VDD is subtracted for comparison. Similarly, comparison is performed in sequence from 1/8VDD to 1/16VDD. If the result is False after comparison has been executed six times, 1/64VDD is subtracted, and the comparison ends. 1 H H 7/8 L H 3/4 H L Compare voltage (xVDD) 5/8 L 1/2 H H 3/8 L L 1/4 H L 1/8 L 0 1/16 L 3/16 L 5/16 L 7/16 L 9/16 L 11/16 L 13/16 L 15/16 L 1 15/16 14/16 13/16 12/16 11/16 10/16 9/16 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 0/16 First Second Third Fourth Subtract 1/16 if false 109 PD17072,17073 (2) Flowchart of binary search START Initial setting (A/D converter reference voltage setting register) = #1000B ADCCMP = 1? N Reset ADCRFSEL3 flag Set ADCRFSEL2 flag ADCCMP = 1? N Reset ADCRFSEL2 flag Set ADCRFSEL1 flag ADCCMP = 1? N Reset ADCRFSEL1 flag Set ADCRFSEL0 flag ADCCMP = 1? N Reset ADCRFSEL0 flag : if "0", subtract 1/16VDD and, Y : if "0", subtract 1/8VDD and, : add both "0" and "1" to 1/16VDD and set reference voltage. : Detect reference voltage and, Y : if "0", subtract 1/4VDD and, : add both "0" and "1" to 1/8VDD and set reference voltage. : Detect reference voltage and, Y : if "0", subtract 1/2VDD and, : add both "0" and "1" to 1/4VDD and set reference voltage. : Detect reference voltage and, Y : Select pin to be used. : Set reference voltage to 1/2VDD : Detect reference voltage and, Detect content of A/D converter reference voltage setting register END 110 PD17072,17073 (3) Program example of binary search START: BANK1 INITFLG INITFLG INITFLG SET1 NOP NOP SKF1 SET1 CLR1 SET1 NOP NOP SKF1 SET1 CLR1 SET1 NOP NOP SKF1 SET1 CLR1 SET1 NOP NOP SKF1 SET1 ADCCMP ADCRFSEL0 ADCCMP ADCRFSEL1 ADCRFSEL0 ADCSTRT ADCCMP ADCRFSEL2 ADCRFSEL1 ADCSTRT ADCCMP ADCRFSEL3 ADCRFSEL2 ADCSTRT NOT ADCCH1, ADCCH0 P1APLD2 NOT ADCRFSEL3, ADCRFSEL2, ADCRFSEL1, ADRFSEL0 ADCSTRT ; Selects AD0 pin ; Sets pull-down resistor of AD0 pin OFF ; Sets compare voltage to 7.5/16 VDD ; A/D converter starts operating. ; 2 wait ; ; Detects ADCCMP ; If 0, adds 7.5/16 VDD and ; subtracts 3.5/16 VDD ; A/D converter starts operating. ; 2 wait ; ; Detects ADCCMP ; If 0, adds 3.5/16 VDD and ; subtracts 1.5/16 VDD ; A/D converter starts operating. ; 2 wait ; ; Detects ADCCMP ; If 0, adds 1.5/16 VDD and ; subtracts 0.5/16 VDD ; A/D converter starts operating. ; 2 wait ; ; Detects ADCCMP ; If 0, adds 0.5/16 VDD END: 13.8 Status at Reset 13.8.1 At power-ON reset The P1A2/AD0 and P1A3/AD1 pins are set in the general-purpose input port mode, and internally pulled down. 13.8.2 On execution of clock stop instruction The P1A2/AD0 and P1A3/AD1 pins are set in the general-purpose input port mode. The previous status of the pull-down resistor is retained. 13.8.3 At CE reset The P1A2/AD0 and P1A3/AD1 pins are set in the general-purpose input port mode. The previous status of the pull-down resistor is retained. 111 PD17072,17073 14. SERIAL INTERFACE 14.1 General Figure 14-1 shows the outline of the serial interface. This serial interface is of two-wire/three-wire serial I/O type. The former type uses SCK and SO1/SI pins. The latter uses SCK, SI, and SO0 pins. Figure 14-1. Outline of Serial Interface SIOCK1, 0 flags Wait signal Clock I/O control block SIOTS flag Clock control block 75 kHz Wait control block SCK/P0B2 Clock counter Count value 8 SIOHIZ flag SIOSEL flag IRQSIO flag Presettable shift register SO1/SI/P0B3 Data I/O control block SO0/P1C0 OUT (SIOSFR) IN Remarks 1. SIOCK1 and 0 (bits 0 and 1 of serial I/O clock select register. Refer to Figure 14-2) set a shift clock. 2. SIOTS (bit 0 of serial I/O mode select register. Refer to Figure 14-3) starts/stops communication. 3. SIOHIZ (bit 1 of serial I/O mode select register. Refer to Figure 14-3) sets the function of the SO0/ P1C0 pin. 4. SIOSEL (bit 3 of serial I/O mode select register. Refer to Figure 14-3) selects I/O of SO1/SI/P0B3 pin. 112 PD17072,17073 14.2 Clock Input/Output Control Block and Data Input/Output Control Block The clock input/output control block and data input/output control block select the operation mode of the serial interface (2-wire or 3-wire mode), control the transmit/receive operation, and select a shift clock. The flags that control these blocks are allocated to the serial I/O clock select register and serial I/O mode select register. Figure 14-2 shows the configuration and function of the serial I/O clock select register. Figure 14-3 shows the configuration and function of the serial I/O mode select register. Table 14-1 shows the setting status of each pin by the corresponding control flags. As shown in this table, the input/output setting flag of each pin must be also manipulated in addition to the control flag of the serial interface, to set each pin. The SIOCK1 and 0 flags select the internal clock (master) or external clock (slave) operation. The SIOHIZ flag selects whether the SO0/P1C0 pin is used as a serial data output pin. The SIOSEL flag selects whether the SO1/SI/P0B3 pin is used as a serial data input (SI pin) or serial data output (SO1) pin. Figure 14-2. Configuration of Serial I/O Clock Select Register Flag symbol Name b3 b2 b1 S I Serial I/O O clock select register K 1 K 0 0 0 C C 61H O (BANK1) b0 S I Address Read/ Write R/W Sets shift clock of serial interface 0 0 1 1 0 1 0 1 External clock 12.5 kHz 18.75 kHz 37.5 kHz Internal clock Fixed to "0" Power-ON At Clock stop reset CE 0 0 0 0 0 0 0 0 113 PD17072,17073 Figure 14-3. Configuration of Serial I/O Mode Select Register Flag symbol Name b3 b2 S I Serial I/O O mode select register E L I Z S 0 S H T 60H O O (BANK1) b1 S I b0 S I Address Read/ Write R/W Starts/stops serial communication 0 1 Stops (wait status) Starts Sets function of P1C0/SO0 pin 0 1 General-purpose output port Serial data output pin Selects function of P0B3/SI/SO1 pin 0 1 As serial data input (SI) pin As serial data output (SO1) pin Fixed to 0 Power-ON At Clock stop reset CE 0 0 0 0 0 0 0 0 0 0 114 PD17072,17073 Table 14-1. Set Status of Each Pin By Control Flags Control flags of serial interface Communication mode S I O S E L Serial I/O select S I O H I Z Serial S I interface O C pin setting K 1 0 S I O C K 0 0 Clock setting Pin name P 0 B B I O 3 I/O setting flag of each pin P 0 B B I O 2 0 Set status of pin 3-wire serial I/O Note 1 External clock P0B2/SCK During wait: general-purpose input port Wait released: external clock input and 2-wire serial I/O Note 2 1 0 1 1 0 Internal clock (reception) Output (transmission) 0 Generalpurpose output Serial output P1C0/SO0 1 0 1 P0B3/SI/ SO1 1 0 1 0 Internal clock 0 1 General-purpose output port General-purpose input port During wait: waits for internal clock output Wait released: internal clock output During wait: general-purpose input port Wait released: serial input General-purpose output port During wait: waits for serial output Wait released: serial output General-purpose output port 1 1 During wait: waits for serial output Wait released: serial output Notes 1. To set the 3-wire serial I/O mode, be sure to reset SIOSEL to 0 and set SIOHIZ to 1. 2. To use the 2-wire serial I/O mode, be sure to reset SIOHIZ to 0. 115 PD17072,17073 14.2.1 Setting 2-/3-wire mode The serial interface uses two pins in the two-wire mode: SCK/P0B2 and SO1/SI/P0B3. The SCK/P0B2 pin is used as a shift clock input/output pin, and the SO1/SI/P0B3 pin is used as a serial data input/ output pin. The SO0/P1C0 pin is not used for the serial interface and is set in the general-purpose output port mode by the SIOHIZ flag. In this way, the serial interface operates in the two-wire mode. In the three-wire mode, three pins, SCK/P0B2, SO0/P1C0, and SO1/SI/P0B3 are used. The SCK/P0B2 is used as a shift clock input/output pin, the SO0/P1C0 pin is used as a serial data output pin, and the SO1/SI/P0B3 pin is used as a serial data input pin. Unlike in the two-wire mode, the SO0/P1C0 pin is used as a serial data output pin according to the setting of the SIOHIZ flag. The SO1/SI/P0B3 pin is used as a serial data input pin according to the setting of the SIOSEL flag. In this way, the serial interface operates in the three-wire mode. 14.2.2 Selecting data input/output using 2-wire serial interface In the two-wire mode, the SO1/SI/P0B3 pin is used as an input/output pin for serial data. Whether the SO1/SI/P0B3 pin is used as a serial data input pin (SI pin) or serial data output pin (SO1 pin) is specified by the SIOSEL flag (refer to Figure 14-3 Configuration of Serial I/O Mode Select Register). 14.3 Clock Control Block The clock control block generates a clock when the internal clock is used (master operation), and controls clock output timing. The frequency fSC of the internal clock is set by the SIOCK0 and SIOCK1 flags of the serial I/O clock select register. Figure 14-2 shows the configuration and function of the serial I/O clock select register. For the clock generation timing, refer to 14.7 Operation of Serial Interface. 14.4 Clock Counter The clock counter counts the shift clock output or input from the shift clock pin (SCK/P0B2 pin). Because the clock counter directly reads the status of the clock pin, it cannot identify whether the clock is an internal clock or an external clock. The contents of the clock counter cannot be directly read by software. For the operation and timing chart of the clock counter, refer to 14.7 Operation of Serial Interface. 116 PD17072,17073 14.5 Presettable Shift Register The presettable shift register is an 8-bit shift register that writes serial-out data and reads serial-in data. Writing/reading data to/from the presettable shift register is performed by PUT and GET instructions via data buffer. The presettable shift register outputs (transmits) the content of its most significant bit (MSB) from the serial data I/O pin in synchronization with the falling edge of the shift clock, and reads data to its least significant bit (LSB) in synchronization with the rising edge of the shift clock. Figure 14-4 shows the configuration and function of the presettable shift register. Figure 14-4. Configuration of Presettable Shift Register Data buffer DBF3 Don't care DBF2 Don't care DBF1 Transfer data GETNote 8 PUTNote Peripheral register Name Presettable shift register b7 M S B b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address L S B DBF0 SIOSFR 03H Valid data Setting of serial-out data and reading of serial-in data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial out Serial in Note If the PUT or GET instruction is executed during serial communication, the data may be lost. For details, refer to 14.8 Notes on Setting and Reading Data. 14.6 Wait Control Block The wait control block performs wait (pause) control of communication. By releasing the wait status by using the SIOTS flag of the serial I/O mode select register, serial communication is started. After the wait status has been released, and communication has been started, the wait status is resumed if shift clock rises at clock counter "8". The communication status can be detected by the SIOTS flag. That is, the communication status can be detected by detecting the status of the SIOTS flag after setting "1" to the SIOTS flag. If "0" is written to the SIOTS flag while the wait status is released, the wait status is set. This is called a forced wait status. For the configuration and function of the serial I/O mode select register, refer to Figure 14-3. 117 PD17072,17073 14.7 Serial Interface Operation The timing of each operation of the serial interface is described below. This timing is applicable to both 2-wire and 3-wire modes. 14.7.1 Timing chart Figure 14-5 shows a timing chart. Figure 14-5. Timing Chart of Serial Interface Shift clock Serial data La 1 D7 2 D6 3 D5 7 D1 8 D0 1 D7 Clock counter SIOTS 0 1 2 3 6 7 8 0 <1> <2> <3> INT <4> <5> <6> Remarks <1> Initial status (general-purpose input port) <2> Start condition satisfied by general-purpose I/O port <3> Wait released <4> Wait timing <5> General-purpose input port mode set <6> Stop condition satisfied by general-purpose I/O port 14.7.2 Operation of clock counter The initial value of the clock counter is "0". The value of the clock counter is incremented each time the falling edge of the clock pin has been detected. When the value of the clock counter reaches "8", it is reset to "0" at the next rising edge of the clock pin. After the clock counter has been reset to "0", the serial communication is placed in the wait status. The conditions under which the clock counter is reset are as follows: (1) (2) (3) (4) At power-ON reset When clock stop instruction is executed When "0" is written to SIOTS flag If shift clock rises while wait status is released and present value of clock counter is "8" 118 PD17072,17073 14.7.3 Wait operation and note When the wait status has been released, serial data is output at the next falling edge of the clock (transmission operation), and the wait released status continues until eight clocks are counted. After the eight clocks have been output, make the shift clock pin high and stop the operations of the clock counter and presettable shift register. Note that, if data is written to or read from the presettable shift register while the wait status is released and the shift clock pin is high, the correct data is not set. If data is written to the presettable shift register while the wait status is released and the shift clock pin is low, the content of the MSB of the data is output to the serial data output pin when the "PUT" instruction is executed. If the forced wait status is set while the wait status is released, the wait status is immediately set when "0" is written to the SIOTS flag. 14.7.4 Interrupt request issuance timing An interrupt request is issued when eight clocks have been transmitted (received). 14.7.5 Shift clock generation timing (1) When wait status is released from initial status The "initial status" means the point at which the P0B2/SCK pin has been made high with the internal clock operation selected. During the wait status, a high level is output to the shift clock pin. The wait status can be released and a clock can be selected at the same time. 119 PD17072,17073 Figure 14-6. Shift Clock Generation Timing of Serial Interface (1/4) Shift clock (37.5 kHz) 1:1 Wait status 1/fSC Initialization 13.33 s Wait released Shift clock (18.75 kHz) 1:1 Wait status 13.33 s Initialization Wait released 1/fSC Shift clock (12.5 kHz) 2:1 26.66 s Wait status 1/fSC Initialization Wait released (2) When wait operation is performed (a) When wait status is set at the 8th clock (normal operation) Figure 14-6. Shift Clock Generation Timing of Serial Interface (2/4) Shift clock Wait released status Contents of output latch Wait status 1/fSC Wait Wait released 120 PD17072,17073 (b) When forced wait status is set during wait status Figure 14-6. Shift Clock Generation Timing of Serial Interface (3/4) Shift clock Contents of output latch Wait period Contents of output latch Wait period Forced wait by SIOTS (c) When forced wait status is set while wait status is released Figure 14-6. Shift Clock Generation Timing of Serial Interface (4/4) Shift clock Wait released status Contents of output latch Wait status 1/fSC Forced wait by SIOTS Wait released Shift clock Wait released status Contents of output latch Wait status 1/fSC Forced wait by SIOTS Wait released (d) When wait status is released while wait status is released The clock output waveform does not change. Neither is the counter reset. However, do not change the clock frequency while the wait status is released. 121 PD17072,17073 14.8 Notes on Setting and Reading Data Use the "PUT SIOSFR, DBF" instruction to set data to the presettable shift register. Use the "GET DBF, SIOSFR" instruction to read data. Set or read the data in the wait status. While the wait status is released, the data may not be correctly set or read depending on the status of the shift clock pin. The following table describes the points to be noted in setting and reading data. Table 14-2. Data Read and Write Operations of Presettable Shift Register and Notes Status on execution of PUT/GET Read (GET) Status of shift clock pin Normal read Operation of presettable shift register Wait status Write (PUT) * Floating with external clock * Value of output latch with internal clock. Normally, used with high level Normal write Content of MSB is output as data at falling edge of shift clock after wait status is released next (transmission operation). Clock Data MSB PUT SIOSFR, DBF Wait released Low level Read (GET) High level Normal read Cannot be read normally. Contents of SIOSFR are lost. Cannot be written normally. Contents of SIOSFR are lost. Normal write Content of MSB is output as data when PUT instruction is executed. Clock counter is not reset. Low level Wait release status Write (PUT) High level Clock Data MSB PUT SIOSFR, DBF 122 PD17072,17073 14.9 Operational Outline of Serial Interface Tables 14-3 and 14-4 outline the operations of the serial interface. Table 14-3. Operation in 3-wire Serial I/O Mode Operation mode Item Status of each pin SCK/P0B2 Slave operation (SIOCK1 = SIOCK0 = 0) During wait (SIOTS = 0) * When P0BBIO2 = 0 General-purpose input port * When P0BBIO2 = 1 General-purpose output port SI/SO1/P0B3 Wait released (SIOTS = 1) * When P0BBIO2 = 0 External clock input port * When P0BBIO2 = 1 General-purpose output port Master operation (SIOCK1 = SIOCK0 = other than 0) During wait (SIOTS = 0) * When P0BBIO2 = 0 General-purpose input port * When P0BBIO2 = 1 Waits for internal clock output SIOSEL = 0 Wait released (SIOTS = 1) * When P0BBIO2 = 0 General-purpose input port * When P0BBIO2 = 1 Internal clock output ----------------------------------------------------------------------------------------- * When P0BBIO3 = 0 General-purpose input port * When P0BBIO3 = 1 General-purpose output port SO0/P1C0 Waits for serial output Program counter Operation of presettable shift register Output * When P0BBIO3 = 0 Serial input * When P0BBIO3 = 1 General-purpose output port * When P0BBIO3 = 0 General-purpose input port * When P0BBIO3 = 1 General-purpose output port SIOHIZ = 1 * When P0BBIO3 = 0 Serial input * When P0BBIO3 = 1 General-purpose output port ----------------------------------------------------------------------------------------- Serial output Waits for serial output Serial output Incremented at falling edge of SCK pin * When SIOHIZ = 0 Not output * When SIOHIZ = 1 Shifted from MSB and output from SO0 pin at falling edge of SCK pin Input * When SIOSEL = 0 Shifted from LSB and status of SI pin is input at rising edge of SCK pin. If SI pin is set in output mode, however, contents of output latch are input. 123 PD17072,17073 Table 14-4. Operation in Two-Wire Serial I/O Mode Operation mode Item Status of each pin SCK/P0B2 Slave operation (SIOCK1 = SIOCK0 = 0) During wait (SIOTS = 0) * When P0BBIO2 = 0 General-purpose input port * When P0BBIO2 = 1 General-purpose output port SI/SO1/P0B3 * When P0BBIO3 = 0 General-purpose input port * When P0BBIO3 = 1 General-purpose output port * When P0BBIO3 = 0 Serial input * When P0BBIO3 = 1 General-purpose output port Wait released (SIOTS = 1) * When P0BBIO2 = 0 External clock input port * When P0BBIO2 = 1 General-purpose output port Master operation (SIOCK1 = SIOCK0 = other than 0) During wait (SIOTS = 0) * When P0BBIO2 = 0 General-purpose input port * When P0BBIO2 = 1 Waits for internal clock output SIOSEL = 0 ----------------------------------------------------------------------------------------- Wait released (SIOTS = 1) * When P0BBIO2 = 0 General-purpose input port * When P0BBIO2 = 1 Internal clock output * When P0BBIO3 = 0 General-purpose input port * When P0BBIO3 = 1 General-purpose output port SIOSEL = 0 * When P0BBIO3 = 0 Serial input * When P0BBIO3 = 1 General-purpose output port ----------------------------------------------------------------------------------------- Waits for serial output regardless of P0BBIO3 SO0/P1C0 Serial output regardless of P0BBIO3 Waits for serial output regardless of P0BBIO3 Serial output regardless of P0BBIO3 SIOHIZ = 1 ----------------------------------------------------------------------------------------- General-purpose output port Program counter Operation of presettable shift register Input Output Incremented at falling edge of SCK pin * When SIOSEL = 1 Shifted from MSB and output from SIO1 pin at falling edge of SCK pin * When SIOSEL = 0 Shifted from LSB and status of SI pin is input at rising edge of SCK pin. If SI pin is set in output port mode, however, contents of output latch are input. 124 PD17072,17073 14.10 Status on Reset 14.10.1 At power-ON reset P0B2/SCK and P0B3/SI/SO1 pins are set in the general-purpose input port mode. P1C0/SO0 pin is set in the general-purpose port. The contents of the presettable shift register are undefined. 14.10.2 At clock stop P0B2/SCK and P0B3/SI/SO1 pins set in the general-purpose input port mode. P1C0/SO0 pin is set in the general-purpose port. The previous contents of the presettable shift register are retained. 14.10.3 At CE reset P0B2/SCK and P0B3/SI/SO1 pins are set in the general-purpose input port mode. P1C0/SO0 pin is set in the general-purpose port. The previous contents of the presettable shift register are retained. 14.10.4 In halt status All the pins hold the current status. The internal clock stops output in the status in which the HALT instruction is executed. When the external clock is used, the operation continued even if the HALT instruction is executed. 125 PD17072,17073 15. PLL FREQUENCY SYNTHESIZER The PLL (Phase Locked Loop) frequency synthesizer is used to lock a frequency in the MF (Medium Frequency), HF (High Frequency), and VHF (Very High Frequency) bands to a fixed frequency, by means of phase difference comparison. 15.1 General Figure 15-1 outlines the PLL frequency synthesizer. By connecting an external lowpass filter (LPF) and voltage controlled oscillator (VCO), the PLL frequency synthesizer can be configured. The PLL frequency synthesizer divides a signal input from the VCOH or VCOL pin by using a programmable divider, and outputs the phase difference between the signal and the reference frequency from the EO pin. However, the signal input from the VCOH pin is halved immediately before it is input to the programmable divider. The PLL frequency synthesizer operates only while the CE pin is high. When the CE pin is low, the synthesizer is disabled. For details of the PLL disable status, refer to 15.5 PLL Disable Status. Figure 15-1. Outline of PLL Frequency Synthesizer VCOH VCOL Input selector block Programmable divider (PD) Phase comparator ( -DET) Charge pump EO Note 75 kHz Reference frequency generator Lowpass filter (LPF) Unlock FF Note Voltage-controlled oscillator (VCO) PLLMD1 flag PLLMD0 flag PLLRFCK2 flag PLLRFCK1 flag PLLRFCK0 flag PLLUL flag Note External circuit Remarks 1. PLLMD1 and 0 (bits 1 and 0 of PLL mode select register. Refer to Figure 15-3) set the division method of the PLL frequency synthesizer. 2. PLLRFCK2, 1, and 0 (bits 2-0 of PLL reference frequency select register. Refer to Figure 15-7) set the reference frequency fr of the PLL frequency synthesizer. 3. PLLUL (bit 0 of PLL unlock FF register. Refer to Figure 15-10) detects the status of the unlock FF. 126 PD17072,17073 15.2 Input Selector Block and Programmable Divider 15.2.1 Configuration and function of input selector block and programmable divider Figure 15-2 shows the configuration of the input selector block and programmable divider. The input selector block selects the input pin and division method of the PLL frequency synthesizer. As the input pin, the VCOH or VCOL pin can be selected. The selected pin is at the intermediate potential (approx. 1/2VDD). The pin not selected is internally pulled down. These pins have an AC amplifier at the input stage; therefore, cut the DC component of the input signal by connecting a capacitor in series. As the division method, DC division method or pulse swallow method can be selected. The programmable divider performs frequency division according to the values set to the swallow counter and programmable counter. Table 15-1 shows each input pin (VCOH and VCOL) and division method. The input pin and division method to be used are selected by the PLL mode select register. Figure 15-3 shows the configuration of the PLL mode select register. A division value is set by using the PLL data register. The division value is transferred to the programmable divider using PLL data set register. Figure 15-2. Configuration of Input Selector Block and Programmable Divider PLL PUT flag PLLMD1 flag PLLMD0 flag PLL data register 12 bits 5 bits 5 VCOH 1/2 Swallower counter, 5 bits 2 modular prescalers 1/32, 1/33 12 Programmable counter, 12 bits To fN f -DET VCOL PLL disable signal 127 PD17072,17073 Table 15-1. Input Pins and Division Modes Division mode Pin Input frequency (MHz) 0.3 - 8 Input amplitude (Vp-p) 0.2 Division value 12 Division value set to data buffer 010xH - FFFxH (x: don't care) 0400H - 1FFFFH Direct division (MF) VCOL 16 to 2 -1 Pulse swallow (HF) Pulse swallow (VHF) VCOL 5 - 130 0.3 1024 to 217 - 1 1024 to 217 - 1 VCOH 40 - 230 0.2 0400H - 1FFFFH Figure 15-3. Configuration of PLL Mode Select Register Flag symbol Name b3 b2 b1 P L L M D 1 b0 P L L M D 0 Address Read/ Write PLL mode select register 0 0 (BANK1) 65H R/W Sets division mode of PLL frequency synthesizer 0 0 1 1 0 1 0 1 PLL disabled Direct division (VCOL pin MF mode) Pulse swallow (VCOH pin VHF mode, 1/2 division) Pulse swallow (VCOL pin HF mode) Fixed to "0" Power-ON At reset Clock stop CE 0 0 0 0 0 0 Retained 128 PD17072,17073 15.2.2 Outline of each division mode (1) Direct division mode (MF) In this mode, the VCOL pin is used. The VCOH pin is floated. The frequency of the input signal is divided only by the programmable counter in this mode. (2) Pulse swallow mode (HF) The VCOL pin is used, and the VCOH pin is floated. In this mode, the frequency is divided by the swallow counter and programmable counter. (3) Pulse swallow mode (VHF) The VCOH pin is used, and the VCOL pin is floated. If this mode is selected 1/2 division is inserted in the stage previous to programmable divider. In this mode, the swallow counter and programmable counter are used for frequency division. (4) PLL disable Refer to 15.5 PLL Disable Status. 129 PD17072,17073 15.2.3 Programmable divider, PLL data register, and PLL data set register A division value is set to the swallow counter and programmable counter by the PLL data register. The value set by the PLL data register is transferred by the PLL data set register to the swallow counter and programmable counter. The swallow counter and programmable counter are 5-bit and 12-bit binary counters. The value to be divided is called an "N value". For how to set the division value (N value) in each division mode, refer to 15.6 Using PLL Frequency Synthesizer. (1) Configuration and functions of PLL data register The configuration of the PLL data register is shown in Figure 15-4. The higher 12 bits of the 16-bit PLL data register are valid in the direct division mode, and all the 17 bits of the register are valid in the pulse swallow mode. In the direct division mode, the 12 valid register bits are set to the programmable counter. In the pulse swallow mode, the higher 12 bits are set to the programmable counter, and the remaining lower 5 bits are set to the swallow counter. (2) Configuration and function of PLL data set register Figure 15-5 shows the configuration of the PLL data set register. By writing "1" to the PLLPUT flag, the division value set by the PLL data register is transferred to the swallow counter and programmable counter. After the data has been set, the PLLPUT flag is reset to "0". (3) Relations between value N of programmable divider and output frequency Value "N" set to the PLL data register and the frequency "fN" that is divided and output by the programmable divider are determined as follows. For details, refer to 15.6 Use of PLL Frequency Synthesizer. (a) In direct division mode (MF) fN = fIN N N: 12 bits (b) In pulse swallow mode (HF, VHF) fN = Note fIN N N: 17 bits In VHF mode, frequency fIN of the signal input from VCOH pin is divided by two immediately before 1 fIN in the VHF mode. input to the programmable divider. Therefore, fN = 2N 130 PD17072,17073 Figure 15-4. Configuration of PLL Data Register Name Address Bit PLL data register BANK1 67H 68H 69H 6AH 6BH b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 P L P L L R 1 6 P L L R 1 5 P L L R 1 4 P L L R 1 3 P L L R 1 2 P L L R 1 1 P L L R 1 0 P L L R 9 P L L R 8 P L L R 7 P L L R 6 P L L R 5 P L L R 4 P L L R 3 P L L R 2 P L L R 1 0 0 0 Data L R 1 7 Fixed to "0" Valid bit: 12 bits (direct division mode) Sets division ratio of PLL frequency synthesizer 0 | 15 (00FH) 16 (010H) Direct division mode | x | 212 -1 (FFFH) don't care Division ratio N : N = x don't care Setting prohibited Valid bit: 17 bits (in pulse swallow mode) Sets division ratio of PLL frequency synthesizer 0 | 1023 (03FFH) Pulse swallow mode 1024 (0400H) | x | 217-1 (1FFFFH) Division ratio N : N = x Setting prohibited Remark On power application and at power-ON reset, the contents of the PLL data register are undefined. On execution of the clock stop instruction and at CE reset, the contents of the PLL data register are retained. 131 PD17072,17073 Figure 15-5. Configuration of PLL Data Set Register Flag symbol Name b3 b2 b1 b0 P L L PLL data set register 0 0 0 P U T 6CH (BANK1) Address Read/ Write W Data transfer to program counter 0 1 Does not transfer (data latch) Transfers Fixed to "0" Power-ON At Clock stop reset CE 0 0 0 0 0 0 132 PD17072,17073 15.3 Reference Frequency Generator Figure 15-6 shows the configuration of the reference frequency generator. The reference frequency generator divides 75 kHz output by the crystal oscillator to generate the reference frequency "fr" of the PLL frequency synthesizer. As reference frequency fr, six frequencies can be selected: 1, 3, 5, 6.25, 12.5, and 25. Reference frequency fr is selected by the PLL reference frequency select register. Figure 15-7 shows the configuration and functions of the PLL reference frequency select register. Figure 15-6. Configuration of Reference Frequency Generator PLLRFCK2 flag PLLRFCK1 flag PLLRFCK0 flag MUX 1 kHz 3 kHz 5 kHz 75 kHz Divider To -DET 6.25 kHz 12.5 kHz 25 kHz OFF PLL disable signal 133 PD17072,17073 Figure 15-7. Configuration of PLL Reference Frequency Select Register Flag symbol Name b3 b2 P L L R F C K 2 b1 P L L R F C K 1 b0 P L L R F C K 0 Address Read/ Write PLL reference frequency select register 0 (BANK1) 66H R/W Sets reference frequency fr of PLL frequency synthesizer 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 kHz 3 kHz 5 kHz 6.25 kHz 12.5 kHz 25 kHz PLL disable PLL disable Power-ON At reset Clock stop CE reset 0 0 0 0 0 0 0 Retained Remark When the PLL reference frequency select register is set to "PLL disable" status, the VCOH and VCOL pins are floated. The EO pin is floated. 134 PD17072,17073 15.4 Phase Comparator (-DET), Charge Pump, and Unlock FF 15.4.1 Configurations of phase comparator, charge pump, and unlock FF Figure 15-8 shows the configurations of the phase comparator, charge pump, and unlock FF. The phase comparator compares the output frequency of the programmable divider, "fN", against the output frequency of the reference frequency generator, "fr", and outputs UP or DW request signal. The charge pump outputs the output signal of the phase comparator from the error out pin (EO). The unlock FF detects the unlock status of the PLL frequency synthesizer. The following paragraphs 15.4.2 through 15.4.4 respectively describe the operations of the phase comparator, charge pump, and unlock FF. Figure 15-8. Configurations of Phase Comparator, Charge Pump, and Unlock FF PLLUL flag Reference frequency generator fr UP Unlock FF Phase comparator ( -DET) Programable divider fN DW Charge pump EO PLL disable signal 135 PD17072,17073 15.4.2 Functions of phase comparator As shown in Figure 15-8, the phase comparator compares the output frequency of the programmable divider "fN" against reference frequency "fr", and outputs UP or DOWN request signal. That is, if fN is lower than fr, it outputs the UP request signal; if fN is higher than fr, the DOWN request signal is output. Figure 15-9 shows the relations among fr, fN, and UP and DOWN request signals. In the PLL disable status, neither UP nor DOWN request signal is output. The UP and DOWN request signals are input to the charge pump and unlock FF. Figure 15-9. Relations among fr, fN, UP, and DW (a) If fN lags behind fr fr fN UP DW (b) If fN advances fr fr fN UP DW (c) If fN and fr are in phase fr fN UP DW (d) If fN is lower than fr fr fN UP DW 136 PD17072,17073 15.4.3 Charge pump As shown in Figure 15-8, the charge pump outputs the UP and DOWN request signals from the phase comparator to the error out pin (EO). Therefore, the relations among the outputs of the error out pins, divided frequency fN, and reference frequency fr are as follows: When fr > fN: Low-level output When fr < fN: High-level output When fr = fN: Floating 15.4.4 Unlock FF As shown in Figure 15-8, the unlock FF detects the unlock status of the PLL frequency synthesizer in response to the UP or DOWN request signal output from the phase comparator. In the unlock status, either one of the UP or DOWN request signals goes low. Therefore, the unlock status can be detected when one of the request signals has gone low. In the unlock status, the unlock FF is set to 1. The status of the unlock FF is detected by the PLL unlock FF register. Figure 15-10 shows the configuration and function of the PLL unlock FF register. The unlock FF is set at the cycle of the selected reference frequency fr. The unlock FF is reset when the contents of the PLL unlock FF register is read by the instruction shown in Table 15-2 (Read & Reset). Therefore, the unlock FF must be detected at a cycle longer than the cycle of the reference frequency fr (which is 1/fr). The delay of the up and down request signals of the phase comparator is fixed to about 1 s. Figure 15-10. Configuration of PLL Unlock FF Register Flag symbol Name b3 b2 b1 b0 P L L U L (BANK1) 6DH Address Read/ Write R& Reset PLL unlock FF register 0 0 0 Detects unlock FF status 0 1 Unlock FF = 0: PLL lock status Unlock FF = 1: PLL unlock status Fixed to "0" Power-ON At Clock stop reset CE 0 0 0 U R R Remark U: Undefined R: Retained 137 PD17072,17073 Table 15-2. Instructions to Reset PLL Unlock FF Register Mnemonic ADD ADDC SUB SUBC AND OR XOR SKE SKEG SKLT SKNE Operand m, #n4 Mnemonic ADD ADDC SUB SUBC AND OR XOR LD SKT SKF MOV @r, m m, @rNote m, #n Operand r, m Note When the row address of m is 6H and 0DH is written to r. Remark m = 6DH 138 PD17072,17073 15.5 PLL Disable Status The PLL frequency synthesizer stops its operation (i.e., is disabled) while the CE pin is low. Similarly, the synthesizer stops when the "PLL disable status" is selected by the PLL reference frequency select register or PLL mode select register even the CE pin is high. Table 15-3 shows the operations of the respective blocks when the PLL synthesizer is disabled. The PLL reference frequency select register and PLL mode select register are not initialized on CE reset, but retains their previous contents; therefore, the original status of the synthesizer is restored when the CE pin goes high after the CE pin has gone low and the PLL disable status has been set. To set the PLL disable status after the CE reset has been effected, initialization must be performed through program. The PLL disable status is set on power-ON reset. Table 15-3. Operations of Respective Blocks in PLL Disable Status Condition CE pin = low (PLL disable) CE pin = high PLL reference frequency select register = 0110B, 0111B PLL mode select register = 0000B Block VCOL, VCOH pins Programmable divider Reference frequency generator Phase comparator Charge pump EO pin floated Floated Division stopped Output stopped 139 PD17072,17073 15.6 Use of PLL Frequency Synthesizer To control the PLL frequency synthesizer, the following data are necessary: (1) Division mode (2) Pin to be used (4) Division value : direct division (MF) or pulse swallow (HF, VHF) : VCOL or VCOH :N (3) Reference frequency : fr The following paragraphs 15.6.1 through 15.6.3 describe how to set the above data in each division mode (MF, HF, or VHF). 15.6.1 Direct Division Mode (MF) (1) Selecting division mode Select the direct division mode by the PLL mode select register. (2) Pin to be used The VCOL pin is enabled when the direct division mode is selected. (3) Setting of reference frequency fr Set the reference frequency by using the PLL reference frequency select register. (4) Calculating division value N Calculate as follows: N= where, fVCOL : input frequency of VCOL pin fr : reference frequency fVCOL fr (5) Example of PLL data setting Suppose that broadcasting in the following MW band is to be received: Receive frequency Reference frequency Intermediate frequency The division value N is: N= fVCOL fr = 1422 + 450 3 = 624 (decimal) = 270H (hexadecimal) : 1422 kHz (MW band) : 3 kHz : +450 kHz Then set the PLL data register, PLL mode select register, and PLL reference frequency select register as follows: PLL data register PLL mode select register 0 don't care 0 0 0 1 PLL reference frequency select register 0 0 0 1 0 0 2 1 0 0 1 7 1 1 0 0 0 0 MF 3 kHz 140 PD17072,17073 15.6.2 Pulse swallow mode (HF) (1) Selecting division mode Select the pulse swallow mode by the PLL mode select register. (2) Pin to be used The VCOL pin is enabled when the pulse swallow mode is selected. (3) Setting reference frequency fr Set the reference frequency by using the PLL reference frequency select register. (4) Calculating division value N Calculate as follows: N= where, fVCOL : input frequency of VCOL pin fr : reference frequency fVCOL fr (5) Example of PLL data setting Suppose that broadcasting in the following SW band is to be received: Receive frequency Reference frequency Intermediate frequency The division ratio N is: N= fVCOL = fr 25500 + 450 5 = 5190 (decimal) = 1446H (hexadecimal) Then set the PLL data register, PLL mode select register, and PLL reference frequency select register as follows: : : : 25.50 MHz (SW band) 5 kHz +450 kHz PLL data register PLL mode select register 0 4 0 0 1 6 1 0 0 0 1 1 PLL reference frequency select register 0 0 1 0 0 0 0 1 0 1 0 1 4 0 0 0 1 HF 5 kHz 141 PD17072,17073 15.6.3 Pulse swallow mode (VHF) (1) Selecting division mode Select the pulse swallow mode by the PLL mode select register. (2) Pin to be used The VCOH pin is enabled when the pulse swallow mode is selected. (3) Setting of reference frequency fr Set the reference frequency by using the PLL reference frequency select register. (4) Calculating division value N Calculate as follows: N= where, fVCOH : input frequency of VCOH pin fr : reference frequency fVCOH fr x 1 Note 2 (5) Example of PLL data setting Suppose that broadcasting in the following FM band is to be received: Receive frequency Reference frequency Intermediate frequency The division ratio N is: N= fVCOH 1Note 100.0 + 10.7 1 Note x = x = 2214 (decimal) 2 0.025 2 fr = 08A6 (hexadecimal) : : : 100.0 MHz (FM band) 25 kHz +10.7 MHz Then set the PLL data register, PLL mode select register, and PLL reference frequency select register as follows: PLL data register PLL mode select register 1 0 0 1 6 1 0 0 0 1 0 PLL reference frequency select register 0 1 0 1 0 0 0 0 0 0 1 0 8 0 0 1 0 A VHF 25 kHz Note The signal input from VCOH pin is divided by two immediately before input to the programmable divider. 142 PD17072,17073 15.7 Status on Reset 15.7.1 On power-ON reset The PLL mode select register is initialized to 0000B; therefore, the PLL disable status is set. 15.7.2 On clock stop The PLL disable status is set when the CE pin goes low. 15.7.3 On CE reset (1) Transition from clock stop to CE reset status The PLL mode select register has been initialized to 0000B when the clock stop instruction has been executed; therefore, the PLL disable status is set. (2) On CE reset The PLL reference frequency select register retains the previous status; therefore, the previous status is restored when the CE pin goes high. 15.7.4 In halt status The set status is retained if the CE pin is high. 143 PD17072,17073 16. INTERMEDIATE FREQUENCY (IF) COUNTER 16.1 Outline of Intermediate Frequency (IF) Counter Figure 16-1 outlines the IF counter. The IF counter is mainly used to detect broadcasting stations, and is used to count the intermediate frequency (IF) output from a tuner. The IF counter counts the frequency input to the P0D3/FMIFC/AMIFC or P0D2/AMIFC pin for a fixed time (1 ms, 4 ms, 8 ms, or open), by using a 16-bit counter. Figure 16-1. Outline of Frequency Counter IFCMD0 flag IFCMD1 flag IFCCK1 flag IFCCK0 flag IFCSTRT flag DBF P0D3/FMIFC/AMIFC IF counter input select block P0D2/AMIFC Gate time control block Start control block IF counter (16 bits) IFCG flag IFCRES flag Remarks 1. IFCMD1 and IFCMD0 (bits 3 and 2 of IF counter mode select register. Refer to Figure 16-3) select the IF counter function. 2. IFCCK1 and IFCCK0 (bits 1 and 0 of IF counter mode select register. Refer to Figure 16-3) select the gate time of the IF counter. 3. IFCSTRT (bit 1 of IF counter control register. Refer to Figure 16-5) controls starting of the IF counter. 4. IFCG (bit 0 of IF counter gate status detection register. Refer to Figure 16-6) detects opening/closing of the gate of the IF counter. 5. IFCRES (bit 0 of IF counter control register. Refer to Figure 16-5) resets the count value of the IF counter. 144 PD17072,17073 16.2 IF Counter Input Select Block and Gate Time Control Block Figure 16-2 shows the configuration of the IF counter input select block and gate time control block. The IF counter input select block selects, by using the IF counter mode select register, whether the P0D3/FMIFC/ AMIFC and P0D2/AMFIC pin are used as IF counter function pins or general-purpose I/O port pins. When using the IF counter function, be sure to set the P0D3/FMIFC/AMIFC and P0D2/AMIFC pins in the input mode. These pins can be set in the input or output mode by using the port 0C bit I/O select register at address 6FH of BANK1 of RAM. For the configuration and function of the port 0C bit I/O select register, refer to 10.2.3 (2) Port 0C bit I/O select register. The gate time control block sets the gate time when the IF counter function is used, by using the IF counter mode select register. Figure 16-3 shows the configuration and function of the IF counter mode register. Figure 16-2. Configuration of IF Counter Input Select Block and Gate Time Control Block IFCMD1 flag IFCMD0 flag FMIFC mode P0D3/FMIFC/AMIFC AMIFC mode P0D2/AMIFC Pin select Operation mode select 1/2 To start control block Input port Gate signal generator IFCCK1 flag IFCCK0 flag 145 PD17072,17073 Figure 16-3. Configuration of IF Counter Mode Select Register Flag symbol Name b3 I F IF counter mode select register C M D 1 b2 I F C M D 0 b1 I F C C K 1 b0 I F C C K 0 (BANK1) 62H Address Read/ Write R/W Sets gate time of IF counter 0 0 1 1 0 1 0 1 1 ms 4 ms 8 ms Open Selects function of IF counter 0 0 1 1 0 1 0 1 IF counter OFF mode (general-purpose I/O port) FMIFC/AMIFC pin: FMIF count mode AMIFC pin: AMIF count mode FMIFC/AMIFC pin: AMIF count mode Power-ON 0 0 0 0 0 0 0 0 0 0 0 0 At reset Clock stop CE 146 PD17072,17073 16.3 Start Control Block and IF Counter 16.3.1 Configuration of start control block and IF counter Figure 16-4 shows the configuration of the start control block and IF counter. The start control block starts counting of the frequency counter and detects the end of counting. The counter is started by the IF counter control register. The end of counting is detected by the IF counter gate status detection register. Figure 16-5 shows the configuration and function of the IF counter control register. Figure 16-6 shows the configuration and function of the IF counter gate status detection register. The 16.3.2, describe the gate operations when the IF counter function is selected. The IF counter is a 16-bit binary counter that counts up the input frequency when the IF counter function is selected. When the IF counter function is used, the IF counter counts the frequency input to the pin while the gate is opened by an internal gate signal. Although this frequency is counted as is in the AMIF count mode, it is halved and then counted in the FMIF count mode. The IF counter is cleared to 0000H when its count value has reached FFFFH, and then continues counting. The count value is read via data buffer by the IF counter data register (IFC). The count value is reset by the IF counter control register. Figure 16-7 shows the configuration and function of the IF counter data register. Figure 16-4. Configuration of Start Control Block and IF Counter DBF 16 IFCSTRT flag IFCG flag IFCRES flag 16 From gate time selector Gate signal block RES Start control IF counter (16 bits) IF counter data register (IFC) 147 PD17072,17073 Figure 16-5. Configuration of IF Counter Control Register Flag symbol Name b3 b2 b1 I F C S T R T b0 I F C R E S Address Read/ Write IF counter control register 0 0 (BANK1) 64H W Controls count value of IF counter 0 1 Nothing is changed Resets counter Starts counting of IF counter 0 1 Nothing is changed Starts counting Fixed to "0" Power-ON At reset Clock stop CE 0 0 0 0 0 0 0 0 148 PD17072,17073 Figure 16-6. Configuration of IF Counter Gate Status Detection Register Flag symbol Name b3 b2 b1 b0 I F IF counter gate status detection register 0 0 0 C G (BANK1) 63H Address Read/ Write R Detects opening/closing of IF counter 0 1 Close Open Fixed to "0" Power-ON At reset Clock stop CE 0 0 0 0 0 0 Caution When the IFCG flag is set to 1 (the gate is open), do not read the contents of the IF counter data register (IFC) to the data buffer. 149 PD17072,17073 16.3.2 Gate operation of IF counter function (1) When gate time is set to 1, 4, or 8 ms As shown below, the gate is opened for 1, 4, or 8 ms starting from the rising edge of an internal 1-kHz signal after the IFCSTRT flag has been set. While the gate is open, the frequency of a signal input to a specific pin is counted by a 16-bit counter. When the gate is closed, the IFCG flag is cleared (0). The IFCG flag is automatically set to "1" as soon as the IFCSTRT flag has been set. Internal 1 kHz Gate time 1 ms 4 ms 8 ms H L OPEN CLOSE Count period (IFCG flag = 1) Actual gate open at this point IFCSTRT flag is set (IFCG flag is set by the instruction after IFCSTRT flag is set) Count ends IFCG flag is cleared (2) When gate time is open When the gate time is specified by the IFCCK1 and IFCCK0 flags to be open, the gate is immediately opened. If counting is started by the IFCSTRT flag while the gate is open, the gate is closed after an undefined time. Therefore, do not set the IFCSTRT flag to "1" when the gate time is open. However, the counter can be reset by the IFCRES flag. Internal 1 kHz Gate H L OPEN CLOSE Count period If IFCSTRT flag is set during this period, gate is closed after undefined time Sets IFCCK1 = IFCCK0 = 1 Gate is actually opened at this point. If gate is opened with IFCG flag set to 1, it is closed after undefined time When the gate time is open, the gate can be opened and closed by resetting the gate time other than open by using IFCCK1 and IFCCK0 flags. Gate OPEN CLOSE Count period Sets IFCCK1 = IFCCK0 = 1 Other than open is set by IFCCK1 and IFCCK0 flags 150 PD17072,17073 Figure 16-7. Configuration of IF Counter Data Register Data buffer DBF3 DBF2 DBF1 DBF0 Transfer data GET can be executed 16 Nothing changes when PUT is executed Peripheral register Name IF counter data register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFC Peripheral address 43H Valid data Measured value of IF counter 0 * FMIF counter Counts the rising edge of the signal input to the P0D3/FMIFC/AMIFC pin (in FMIF count mode) via a 1/2 divider. * AMIF counter X Counts the rising edge of the signal input to the P0D2/AMIFC pin (in AMIF count mode) or P0D3/FMIFC/AMIFC pin (in AMIF count mode). 216 - 1 (FFFFH) 151 PD17072,17073 16.4 Using IF Counter The following sections 16.4.1 through 16.4.3 describe how to use the hardware of the IF counter, program example, and count error. 16.4.1 Using hardware of IF counter Figure 16-8 shows the block diagram when the P0D2/AMIFC pin and P0D3/FMIFC/AMIFC pins are used. Table 16-1 shows the range of frequency that can be input to the P0D2/AMIFC pin and P0D3/FMIFC/AMIFC pin. As shown in Figure 16-8, the input pin of the IF counter is provided with an AC amplifier; therefore, cut off the DC component of the input signal with a capacitor C. When the P0D2/AMIFC or P0D3/FMIFC/AMIFC pin is selected for the IF counter function, switch SW turns ON and the voltage applied to the pin is about 1/2VDD. If the intermediate voltage does not rise sufficiently at this time, the AC amplifier is not in the normal operating range; consequently, the IF counter does not function normally. Therefore, provide a sufficient wait time after each pin has been specified to be used for the IF counter function, until counting is started. When using the IF counter function for the auto tuning function of a radio to detect broadcasting stations, it is recommended to use the function with the SD (Station Detection) output, and so on, of the tuner. Figure 16-8. Block Diagram of IF Count Function of Each Pin R SW C External frequency FMIFC AMIFC To internal counter Table 16-1. IF Counter Input Frequency Range Input pin Input frequency (MHz) 10 - 11 Input amplitude (VP-P) 0.1 P0D3/FMIFC/AMIFC FMIF mode P0D3/FMIFC/AMIFC AMIF mode P0D2/AMIFC AMIF mode 0.4 - 2 0.4 - 0.5 0.4 - 2 0.4 - 0.5 0.15 0.1 0.15 0.1 152 PD17072,17073 16.4.2 Program example of IF counter A program example of the IF counter is shown below. As shown in this example, make sure that a wait time of a certain length elapses after an instruction that specifies the P0D2/AMIFC or P0D3/FMIFC/AMIFC pin to be used for the IF counter has been executed, until the counter is actually started. This is because the internal AC amplifier is not ready for normal operation immediately after the pin has been selected for the IF counter function, as described in 16.4.1. Example To count frequency of P0D3/FMIFC/AMIFC pin (FMIF count mode) (gate time: 8 ms) BANK1 INITFLG Wait SET1 SET1 LOOP: SKT1 BR BR READ: GET 16.4.3 Error of IF counter DBF, IFC ; Reads value of IF counter data register to data buffer IFCG READ LOOP ; Detects opening/closing of gate ; Branches to READ: if gate is closed ; Do not read data of IF counter with this processing A. IFCRES IFCSTRT IFCMD1, NOT IFCMD0, IFCCK1, NOT IFCCK0 ; Selects FMIFC pin (FMIF count mode) and sets gate time to 8 ms ; Internal AC amplifier stabilization time ; Resets IF counter ; Starts IF count Processing A The IF counter has a gate time error and count error, as described in (1) and (2) below. (1) Gate time error The gate time of the IF counter is created by dividing the 75-kHz system clock frequency. Therefore, if this frequency has an error of "+x" ppm, the gate time accordingly has an error of "-x" ppm. (2) Count error The IF counter counts frequency at the rising edge of the input signal. Therefore, if a high-level signal is input to the pin when the gate is opened, one extra pulse is counted. However, this extra pulse may not be counted, depending on the status of the pin, when the gate is closed. Therefore, the count error is "+1, -0". 153 PD17072,17073 16.5 Status at Reset 16.5.1 Power-ON reset The P0D3/FMIFC/AMIFC and P0D2/AMIFC pins are set in the general-purpose input port mode. The contents of the output latch are "0". 16.5.2 On execution of clock stop instruction The P0D3/FMIFC/AMIFC and P0D2/AMIFC pins are set in the general-purpose input port mode. The contents of the output latch are retained. 16.5.3 At CE reset The P0D3/FMIFC/AMIFC and P0D2/AMIFC pins are set in the general-purpose input port mode. The contents of the output latch are retained. 16.5.4 In halt status The P0D3/FMIFC/AMIFC and P0D2/AMIFC pins retain the status immediately before the halt mode is set. 154 PD17072,17073 17. BEEP 17.1 Configuration and Function of BEEP Figure 17-1 outlines BEEP. BEEP outputs a clock of 1.5 kHz or 3 kHz from the BEEP pin. The output select block selects, by using the BEEP0CK0 and BEEP0CK1 flags of the BEEP clock select register, whether 1.5 kHz or 3 kHz is output from the BEEP pin, or whether the BEEP pin is used as a 1-bit general-purpose output port. The clock generation block generates the 1.5-kHz or 3-kHz clock to be output to the BEEP pin. Figure 17-2 shows the configuration and function of the BEEP clock select register. Figure 17-1. Outline of BEEP BEEP0CK0 flag BEEP0CK1 flag Output select BEEP block 1.5 kHz 3 kHz Output select block Clock generation block Figure 17-2. Configuration and Function of BEEP Clock Select Register Flag symbol Name b3 b2 b1 B E E P 0 C K 1 b0 B E E P 0 C K 0 Address Read/ Write BEEP clock select register 0 0 (BANK1) R/W 5BH Setting of BEEP pin 0 0 1 1 0 1 0 1 Used as general-purpose output port and outputs low level Used as general-purpose output port and outputs high level Outputs 1.5 kHz clock Outputs 3 kHz clock Fixed to "0" Power-ON At Clock stop reset CE 0 0 0 0 0 0 Retained 155 PD17072,17073 17.2 Output Wave Form of BEEP (1) Output wave of f = 1.5 kHz and f = 3 kHz BEEP (f = 1.5 kHz) 333.3 s 333.3 s BEEP (f = 3 kHz) 133.3 s 200 s Example Program to output 3-kHz clock from BEEP pin BANK1 MOV 5BH, #0011B ; Same as MOV BANK, #0001B ; Writes 0011B to data memory address 5BH ; Outputs 3 kHz from BEEP pin (2) Maximum time until clock is output from BEEP pin after instruction execution BEEP (f = 1.5 kHz) 325.8 s Instruction execution BEEP (f = 3 kHz) 325.8 s Instruction execution (3) Minimum time until clock is output from BEEP pin after instruction execution BEEP (f = 1.5 kHz) 133.3 s Instruction execution BEEP (f = 3 kHz) 133.3 s Instruction execution 156 PD17072,17073 17.3 Status at Reset 17.3.1 At power-ON reset The BEEP pin is set in the general-purpose output port mode, and outputs a low level. The value of the latch of the output port is "0". 17.3.2 On execution of clock stop instruction The BEEP pin is set in the general-purpose output port mode, and outputs a low level. The value of the latch of the output port is "0". 17.3.3 At CE reset The BEEP pin retains the previous output status. The contents of the latch are also retained. 17.3.4 In halt status The BEEP output pin retains the previous output status. 157 PD17072,17073 18. LCD CONTROLLER/DRIVER The LCD (Liquid Crystal Display) controller/driver can display an LCD of up to 60 dots by a combination of command signal and segment signal outputs. 18.1 Outline of LCD Controller/Driver Figure 18-1 outlines the LCD controller/driver. The LCD controller/driver can be used to display up to 60 dots by using a combination of common signal output pins (COM0 through COM3) and segment signal output pins (LCD0 through LCD14). The drive mode is 1/4 duty, 1/2 bias, the frame frequency is 62.5 Hz, and drive voltage is VLCD1. Figure 18-1. Outline of LCD Controller/Driver LCD0 pin Segment signal output timing control block LCD segment register (data memory space) ... LCD14 pin COM0 pin ... COM3 pin Common signal output timing control block Basic clock for timing control ... ... LCDEN flag REGLCD0 pin REGLCD1 pin CAPLCD0 pin CAPLCD1 pin LCD drive voltage generation block Remark LCDEN (bit 3 of LCD driver display start register: refer to Figure 18-6) turns ON/OFF all LCD display. 158 PD17072,17073 18.2 LCD Drive Voltage Generation Block The LCD drive voltage generation block generates a voltage to drive the LCD. The PD17073 supplies the LCD drive voltage from an external doubler circuit. To configure a doubler circuit, connect a capacitor to the REGLCD0, CAPLCD0, CAPLCD1, and REGLCD1 pins. Figure 18-2 shows an example of configuration of the doubler circuit. To use a voltage of 3.1 V (TYP.), connect as shown in Figure 18-2. To operate the doubler circuit, the LCDEN flag of the LCD display start register must be set to "1". Unless this flag is set to "1", the LCD drive voltage generation block does not operate. For the LCDEN flag, refer to 18.4 Common Signal Output and Segment Signal Output Timing Control Blocks. Figure 18-2. Configuration of Doubler Circuit C1 REGLCD1 CAPLCD1 C3 CAPLCD0 REGLCD0 C2 C1 = C2 = 0.1 F C3 = 0.01 F Remark ( ): pin number Note that, because of the configuration of the doubler circuit, the values of the LCD drive voltages (VLCD1 and VLCD0) differ if the values of C1, C2, and C3 are changed. 159 PD17072,17073 18.3 LCD Segment Register The LCD segment register sets dot data to turn on or turn off dots on the LCD. Figure 18-3 shows the location in the data memory and configuration of the LCD segment register. Because the LCD segment register is located in data memory, it can be controlled by all the data memory manipulation instructions. One nibble of the LCD segment register can set display data of 4 dots (data to turn dots on or off). If the LCD segment register is set to "1" at this time, the LCD display dot is on; the dot goes off if the register is set to "0". Figure 18-4 shows the relation between the LCD segment register and LCD display dot. Figure 18-3. Location on Data Memory and Configuration of LCD Segment Register Column address 0 0 1 2 3 4 5 6 7 Row address 1 2 3 4 5 6 7 8 9 A B C D E F DBF BANK0 B BANK1 Data memory LCD segment register C D E F 0 1 2 3 4 5 6 7 System register LCD segment register Address 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH Symbol LCDD14 LCDD13 LCDD12 LCDD11 LCDD10 LCDD9 LCDD8 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 LCDD14 b3 b2 b1 b0 160 Figure 18-4. Relation between LCD Segment Register and LCD Display Dot LCD segment register Address Symbol Bit 41H LCDD14 42H LCDD13 43H LCDD12 44H LCDD11 45H LCDD10 46H LCDD9 47H LCDD8 4EH LCDD1 4FH LCDD0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 B C D A B C D E F GH A B C D E F GH A B CD E F GH A B C D E F GH Display dot A COM3 pin A A E A E A E A E COM2 pin B B F B F B F B F COM1 pin C C G C G C G C G COM0 pin D D H D H D H D H LCD14 pin LCD13 pin LCD12 pin LCD11 pin LCD10 pin LCD9 pin LCD8 pin LCD1 pin LCD0 pin PD17072,17073 161 PD17072,17073 18.4 Common Signal Output and Segment Signal Output Timing Control Blocks Figure 18-5 shows the common signal output and segment signal output timing control blocks. The common signal output timing control block controls the common signal output timing of the COM0 through COM3 pins. The segment signal output timing control block controls the segment signal output timing of the LCD0 through LCD14 pins. The common and segment signals are output when the LCDEN flag of the LCD driver display start register is set to "1". When this flag is reset to "0", all the LCD display dots can be extinguished (refer to Figure 18-6). When LCD display is not carried out, the COM0 through COM3 and LCD0 through LCD14 pins output low level. Figure 18-5. Configuration of Common Signal Output and Segment Signal Output Timing Control Blocks b0 LCD0 | LCD14 Segment signal Segment signal output timing control block b1 b2 b3 LCDD0 | LCDD14 Basic clock for timing control LCDEN flag COM0 Common signal Common signal output | timing control block COM3 162 PD17072,17073 Figure 18-6. Configuration of LCD Driver Display Start Register Flag symbol Name b3 b2 b1 A D LCD driver display start register 0 0 C O N b0 L C (BANK1) D 50H E N Address Read/ Write R/W Sets ON/OFF of all LCD displays 0 1 Display OFF (all segment and common output pins output low level) Display ON Fixed to "0" Power-ON At Clock stop reset CE Remark R: Retained 0 0 0 0 0 0 0 R Cautions 1. Bit 3 of the LCD display start register is a test mode area. Therefore, do not write "1" to this bit. 2. For the function of the ADCON flag, refer to 13.2 Setting of A/D Converter Power Supply. 18.5 Common Signal and Segment Signal Output Waves Figure 18-7 shows an example of the common signal and segment signal output waves. The PD17073 outputs a signal with a frame frequency of 62.5 Hz using a 1/4 duty, 1/2 bias (voltage average method) drive mode. As the common signals, the COM0 through COM3 pins output three levels of voltages (GND, VLCD0, and VLCD1) each having a phase difference of 1/8 from the others. In other words, voltages of 1/2VDD are output with the VLCD0 as the reference. This display method is called the 1/2 bias drive method. As the segment signals, the segment signal output pins output voltages of two levels (GND and VLCD1) having a phase corresponding to each display dot. Because one segment pin can turn on or off four display dots (A, B, C, and D) as shown in figure 18-7, sixteen phases can be output by combining lighting and extinguishing of each dot. Each display dot turnd on when the potential difference between a common signal and a segment signal is VLCD1. In other words, the duty factor at which each display dot turns on is 1/4. This display method is called the 1/4 duty display method, and the frame frequency is 62.5 Hz. 163 PD17072,17073 Figure 18-7. Common Signal and Segment Signal Output Waves COM0 pin A COM1 pin B COM2 pin C COM3 pin D Each segment signal output pin (LCDn pin) Common signal 1 frame (16 ms) 4 ms VLCD1 COM0 pin VLCD0 GND VLCD1 COM1 pin VLCD0 GND VLCD1 COM2 pin VLCD0 GND VLCD1 COM3 pin VLCD0 GND Segment signal (example) A, B, C, D = extinguishes VLCD1 LCDn pin GND A, B, C, D = lights VLCD1 LCDn pin GND A, B, C = lights, D = extinguishes VLCD1 LCDn pin GND 164 PD17072,17073 18.6 Using LCD Controller/Driver Figure 18-8 shows an example of wiring of an LCD panel An example of a program that lights the 7 segments connected to LCD0 and LCD1 pins shown in Figure 18-8 is given below. Example PMN0 CH LCDDATA: DW DW DW DW DW DW DW DW DW DW MOV MOV MOV MOV LD LD LD LD ADD ADDC ADDC ADDC ST ST ST ST MOVT BANK1 ST ST SET1 SET1 LCDD0, DBF0 LCDD1, DBF1 CH LCDEN ; LCD ON 0000000000000000B 0000000000000110B 0000000010110101B 0000000010100111B 0000000001100110B 0000000011100011B 0000000011110011B 0000000010000110B 0000000011110111B 0000000011100111B MEM FLG 0.01H LCDD0.3 ; Preset number storage area ; Defines symbol with high-order 1 bit of LCD0 register for `CH' display ; LCD segment table data ; BLANK ;1 ;2 ;3 ;4 ;5 ;6 ;7 ;8 ;9 AR0, #.DL.LCDDATA SHR 12 AND 0FH AR1, #.DL.LCDDATA SHR 8 AND 0FH AR2, #.DL.LCDDATA SHR 4 AND 0FH AR3, #.DL.LCDDATA DBF0, AR0 DBF1, AR1 DBF2, AR2 DBF3, AR3 DBF0, PMN0 DBF1, #0 DBF2, #0 DBF3, #0 AR0, DBF0 AR1, DBF1 AR2, DBF2 AR3, DBF3 DBF, @AR ; Table reference instruction AND 0FH 165 166 A FM MW SW LW 1 e 1d 1 f 1g 1 c 1a 1 b Figure 18-8. Example of Wiring of LCD Panel B C D 2a 2 f 2g 2 e 2d 2 c 3 e 2 b 3 f 3a 3 b 3g 3 c 3d 4 e 4 f 4a 4 b 4g 4 c 4d E F G AM PM MHz kHz 5 e 5 f 5a 5 b 5g 5 c 5d CH COM0 COM1 COM2 COM3 COM3 COM2 COM1 COM0 Common LCD14 Segment Pin LCD13 LCD12 L C D 14 FM MW SW LW Correspondence of Segment and Common Pins, and LCD Panel Display L C D 13 L C D 12 L C D 11 L C D 10 L C D 9 L C D 8 L C D 7 L C D 6 L C D 5 L C D 4 L C D 3 L C D 2 L C D 1 L C D 0 LCD11 LCD10 B A LCD9 1a 1f 1g 1e LCD8 2a 1b 2f 1c 2g 1d 2e LCD7 2b 2c 2d ** LCD6 3a 3f 3g 3e LCD5 C 3b 3c 3d LCD4 4a 4f 4g 4e LCD3 D E 4b F 4c G 4d LCD2 AM PM MHz kHz 5a 5f 5g 5e LCD1 CH 5b 5c 5d LCD0 PD17072,17073 PD17072,17073 18.7 Status at Reset 18.7.1 At power-ON reset The LCD0 through LCD14 pins output a low level. The COM0 through COM3 pins also output a low level. Therefore, the LCD display is OFF. The contents of the LCD segment register are undefined. 18.7.2 On execution of clock stop instruction The LCD0 through LCD14 pins output a low level. The COM0 through COM3 pins also output a low level. Therefore, the LCD display is OFF. The LCD segment register retains the previous contents. 18.7.3 At CE reset The LCD0 through LCD14 pins output segment signals. The COM0 through COM3 pins output common signals. The LCD segment register retains the previous contents. 18.7.4 In halt status The LCD0 through LCD14 pins output segment signals. The COM0 through COM3 pins output common signals. The LCD segment register retains the previous contents. 167 PD17072,17073 19. STANDBY The standby function is used for the purpose of reducing the current consumption of the device when the device is in the backup status. 19.1 General Figure 19-1 shows the outline of the standby block.The standby function is to reduce the current consumption of the device by stopping part of or entire device, or slowing down the CPU clock. The standby function can be used in the following four modes, which can be selected according to the application: <1> Halt mode <2> Clock stop mode <3> Controlling device operation by CE pin <4> Low-speed function The halt mode is to reduce the current consumption of the device by stopping the operation of the CPU when a dedicated instruction, "HALT h", has been executed. The clock stop mode is to reduce the current consumption of the device by stopping the oscillation of the oscillator circuit when a dedicated instruction, "STOP s", has been executed. The CE pin is usually used to control the operation of the PLL frequency synthesizer and to reset the device. However, it can be said to be a mode of the standby function in that this pin controls operations. The low-speed function is to reduce the current consumption of the device by slowing down the CPU clock. 168 PD17072,17073 Figure 19-1. Outline of Standby Block Halt block Interrupt control block Basic timer 0 P1A3/AD1 P1A2/AD0 P1A1 P1A0 Clock stop block CE flag CE XOUT Clock stop control circuit STOP s ALU Halt control circuit HALT h Input latch CPU Program counter Instruction decoder System register Peripheral control register XIN Internal block Remark CE flag (bit 0 of CE pin status detection register. Refer to Figure 19-6) detects the status of the CE pin. 169 PD17072,17073 19.2 Halt Function 19.2.1 General The halt function is to stop the operation clock of the CPU by executing the "HALT h" instruction. When this instruction has been executed, the program is stopped and is not executed unless the halt status is released. Therefore, the current consumption of the device is reduced by the operating current of the CPU in the halt status. The halt status is released by key input, basic timer 0, or interrupt. The releasing condition is specified by the operand "h" of the HALT h instruction. The HALT h instruction is valid regardless of the input level of the CE pin. 19.2.2 Halt status In the halt status, all the operations of the CPU are stopped. In other words, the program execution is stopped by the "HALT h" instruction. However, the peripheral hardware retains the status set before the HALT h instruction is executed. For the operation of each peripheral hardware, refer to 19.4 Device Operations in Halt and Clock Stop Statuses. 19.2.3 Halt release condition Figure 19-2 shows the halt release conditions. The halt release condition is set by 4-bit data that is specified by the operand "h" of the HALT h instruction. The halt status is released when the condition specified as "1" in operand "h" is satisfied. When the halt status has been released, program execution is started from the instruction next to "HALT h" instruction. If two or more release conditions are specified, the halt status is released if any one of the specified conditions has been satisfied. When the device has been reset (by means of power-ON reset or CE reset), the halt status is released, and the appropriate reset operation is performed. If 0000B is set as the halt release condition "h", no release condition is set. In this case, the halt status is released when the device is reset (power-ON reset or CE reset). Figure 19-2. Halt Release Condition HALT h (4 bits) Operand b3 b2 b1 b0 0: Does not release halt status even if condition is satisfied 1: Releases halt status if condition is satisfied Sets halt status release condition Releases if high level is input to port 1A Releases if basic timer 0 carry FF is set (1) Undefined (Fix this bit to "0".) Releases when interrupt request flag and interrupt enable flag are set (When executing EI and DI instructions) 170 PD17072,17073 19.2.4 Releasing halt by key input To release the halt mode by key input, the HALT instruction is specified as "HALT 0001B". With the key input specified as the halt release condition, the halt mode is released when a high-level signal is input to any one of the P1A0, P1A1, P1A2/AD0, and P1A3/AD1 pin. However, halt mode cannot be released by a pin disconnected to the pull-down resistor. (1) When using general-purpose output port as key source signal P1A3/AD1 Latch P1A2/AD0 P1A1 Switch A P1A0 General-purpose output port To use a general-purpose output port as the key source signal, make the output port high-level, and execute the "HALT 0001B" instruction. When an alternate switch is used at this time as switch A in the above figure, a high-level is always input to the P1A0 pin while switch A is closed, and the halt mode is immediately released. Therefore, care must be exercised when key input is specified as the halt mode releasing condition and an alternate switch is used. (2) To release halt by other microcontroller Output port P1A3/AD1 Latch P1A2/AD0 Microcontroller, etc. P1A1 P1A0 General-purpose output port The P1A0, P1A1, P1A2/AD0, and P1A3/AD1 pins can also be used as general-purpose input ports with pulldown resistor. Therefore, other microcontrollers can also be used as shown above after the halt mode has been released. 171 PD17072,17073 19.2.5 Releasing halt status with basic timer 0 To release the halt condition by using the basic timer 0, use the "HALT 0010B" instruction. When it has been set that the halt status is to be released by the basic timer 0, the basic timer 0 carry FF is set to 1, and at the same time, the halt status is released. The basic timer 0 carry FF corresponds to the BTM0CY flag on a one-to-one basis and is set at fixed time intervals (125 ms). Therefore, the halt status can be released at specific time intervals. Example To release halt status every 125 ms and perform processing A every 1 second M1 HLTTMR LOOP: HALT BANK1 SKT1 BR BANK0 ADD SKT1 BR BR M1, #0010B CY LOOP LOOP ; Adds 0010B to contents of M1 ; Embedded macro ; Executes processing A if carry occurs BTM0CY LOOP ; Embedded macro ; Branches to LOOP if BTM0CY flag is not set HLTTMR ; Specifies that halt status is released by basic timer 0 carry FF, and sets halt status MEM DAT 0.10H 0010B ; 1-second counter ; Symbol definition Processing A 172 PD17072,17073 19.2.6 Releasing halt status by interrupt To release the halt status by interrupt, use the "HALT 1000B" instruction. There are three interrupt sources available as explained in 11. INTERRUPT. Therefore, the interrupt by which the halt status is to be released must be specified by software. The halt status is released if the following conditions (1) through (3) are satisfied: (1) The "HALT 1000B" instruction is set. (2) Each interrupt is enabled by the corresponding interrupt enable flag (IPxxx flag = 1). (3) An interrupt request is issued by the corresponding interrupt request flag (IRQxxx flag = 1). Depending on whether the EI or DI instruction is executed at this time, the operation to be performed after the halt status has been released differs. If the EI instruction is executed, the program branches to the vector address of the interrupt. If the RETI instruction is executed after the interrupt has been serviced, the program returns to the next instruction after the HALT instruction. If the DI instruction is executed, the program does not branch to a vector address, but the next instruction next after the HALT instruction is executed as soon as the halt status has been released. Examples of programs when the EI and DI instruction are executed, and notes on releasing the halt status by interrupt are described below. 173 PD17072,17073 Example 1. Example of program when EI instruction is executed HLTINT INTTM INTPIN START: BR ORG ORG INTTM BR INTPIN Processing A BR INTTIMER: Processing B EI_RETI: EI RETI MAIN: BANK1 SET2 SET1 LOOP: Processing C EI HALT ; <1> BR LOOP HLTINT ; Main routine processing ; Enables all interrupts ; Sets releasing halt mode by interrupt IPBTM, IP BTM1CK ; Embedded macro ; Sets time interval of basic timer 1 to 8 ms EI_RETI ; Interrupt service by basic timer 1 INTTIMER ; Interrupt service by INT pin MAIN ; Program address 0000H ; Basic timer 1 interrupt vector address DAT DAT DAT 1000B 0002H 0003H ; Symbol definition for halt mode ; Defines symbol of interrupt vector address ; Defines symbol of interrupt vector address In this example, the halt mode is released when an interrupt by basic timer 1 has been accepted, processing B is executed, and processing A is executed when an interrupt by INT pin has been accepted. Each time the halt mode is released, processing C is executed. If the interrupt request by INT pin and interrupt request by basic timer 1 are issued exactly at the same time in the halt mode, processing A of INT pin, which is assigned the higher hardware priority, is executed. When "RETI" is executed after execution of processing A, the execution is returned to the "BR LOOP" instruction in <1>. However, the "BR LOOP" instruction is not executed, but the basic timer 1 interrupt is accepted immediately, and processing B is executed. If the "RETI" instruction is executed after processing B, the "BR LOOP" instruction is executed. 174 PD17072,17073 Example 2. Example of program when DI instruction is executed HLTINT START: DI BANK1 SET2 SET1 IPBTM1, IP BTM1CK ; Embedded macro ; Sets time of interrupt by basic timer 1 to 8 ms ; Disables all interrupts DAT 1000B ; Symbol definition of halt condition LOOP: HALT SKT1 BR CLR1 INTBTM1: SKT1 BR CLR1 IRQBTM1 LOOP IRQBTM1 ; ; Interrupt service by basic timer 1 ; Detects halt release trigger HLTINT IRQ INTBTM1 IRQ ; ; Interrupt service by INT pin ; Sets releasing halt status by interrupt ; Detects halt release trigger Processing A Processing B BR LOOP Because the DI instruction is executed in the above example, the program does not branch to the respective vector addresses but executes the next instruction even if interrupt by basic timer 1 or INT pin is accepted. 175 PD17072,17073 Caution When executing the HALT instruction that is released when an interrupt request flag (IRQxxx), for which the corresponding interrupt enable flag (IPxxx) is set, is set, describe a NOP instruction immediately before the HALT instruction. When the NOP instruction is described immediately before the HALT instruction, time of one instruction is generated between the IRQxxx manipulation instruction and HALT instruction. In the case of the CLR1 IRQxxx instruction, for example, clearing IRQxxx correctly is reflected upon the HALT instruction (Example 1 below). If the NOP instruction is not described immediately before the HALT instruction, the CRL1 IRQxxx instruction is not correctly reflected on the HALT instruction, and the HALT mode is not set (Example 2). Examples 1. To execute HALT instruction correctly ... ... ... ; Sets IRQxxx CLR1 NOP HALT IRQxxx ; NOP instruction is described immediately before HALT instruction ; (Clearing IRQxxx is correctly reflected on HALT instruction) 1000B ... ... ; HALT instruction is executed correctly (HALT mode is set) 2. Program that does not set HALT mode ... ... ... ; Sets IRQxxx ; Clearing IRQxxx is not reflected on HALT instruction ; (It is reflected on instruction next to HALT instruction) HALT 1000B ... ... ; HALT instruction is ignored (HALT mode is not set) CLR1 IRQxxx 176 PD17072,17073 19.2.7 When two or more release conditions are specified When two or more halt release conditions are specified, the halt mode is released if any one of the specified conditions is satisfied. The following example shows how the condition is identified when two or more conditions are specified: Example HLTINT HLTTMR HLTKEY INTPIN START: BR ORG INTPIN Processing A EI RETI TMRUP: Processing B RET KEYDEC: Processing C RET MAIN: BANK1 MOV SET1 EI LOOP: HALT HLTINT OR HLTTMR OR HLTKEY ; ; SKT1 BR CALL BR KEYDEC: Key processing BR LOOP BTM0CY KEY_DEC TMRUP LOOP ; Basic timer 0 processing if set to "1" ; ; Specifies external interrupt (INT pin), basic timer 0, and key input as halt release condition Embedded macro Detects BTM0CY flag P1B, #1111B IP ; ; ; Outputs P1B3-P1B0 at high level as key source output Embedded macro Enables INT pin interrupt ; Key input processing ; Basic timer 0 processing ; INT pin interrupt service MAIN DAT 1000B DAT 0010B DAT 0001B DAT 0003H ; Vector address symbol definition of INT pin interrupt 177 PD17072,17073 19.3 Clock Stop Function The clock stop function stops the 75 kHz crystal resonator when the "STOP s" instruction (clock stop status) is executed. Therefore, the current dissipation of the device is reduced to 3 A maximum (TA = 25 C, VDD = 3.0 V). As the operand "s" of the "STOP s" instruction, "0000B" is specified. The "STOP s" instruction is valid only when the CE pin is at the low level, and is executed as a no-operation ("NOP") instruction when the CE is at the high level. Therefore, the "STOP s" instruction must be executed when the CE pin is at the low level. The clock stop mode can be released by CE reset rising the CE pin, or by power-ON reset with supply voltage VDD application. 19.3.1 Clock stop status In the clock stop status, the crystal resonator is stopped. As a result, the CPU and all the peripheral hardware stop their operations. For the operations of the CPU and peripheral hardware, refer to 19.4 Device Operations in Halt and Clock Stop Statuses. 19.3.2 Releasing clock stop status The clock stop status can be released in the following two ways. After the clock stop status has been released, the program is started from address 0000H, regardless of which of (1) and (2) has been used to release the clock stop status. (1) Raise the CE pin from low to high (CE reset). (2) Lower the supply voltage VDD of the device to 1.8 V or lessNote, and then raise it again to 1.8 V or higher (TA = -20 to +70 C, normal operation) (power-ON reset). Note This voltage is called power-ON clear voltage. The maximum value of the power-ON clear voltage is 1.8 V, and the actual value is in a range not exceeding this maximum value. For details, refer to 20.4.1 Power-ON clear voltage. 19.3.3 Releasing clock stop status by CE reset Figure 19-3 illustrates how the clock stop status is released by the CE reset. 178 PD17072,17073 Figure 19-3. Releasing Clock Stop by CE Reset 3V VDD 0V H CE pin L H XOUT pin L 125 ms or more STOP s instruction Program starts from address 0 (CE reset) 3V VDD 0V H CE pin L H XOUT pin L If the clock stop instruction is not used, the operation is performed as follows: 0-tSET Program starts from address 0 (CE reset) CE reset is effected in synchronization with next setting of basic timer 0 carry FF after CE pin goes high 19.3.4 Releasing clock stop status by power-ON reset Figure 19-4 illustrates how the clock stop status is released by power-ON reset. When the clock stop status is released by power-ON reset, the power failure detection circuit operates. Figure 19-4. Releasing Clock Stop by Power-ON Reset 3V VDD 0V H CE pin L H XOUT pin L 125 ms or more STOP s instruction Program starts from address 0 (power-ON reset) 1.8 VNote 3V VDD 0V H CE pin L H XOUT pin L If the clock stop instruction is not used, the operation is performed as follows: 1.8 VNote 125 ms or more Oscillation stops Program starts from address 0 (power-ON reset) Note This voltage is called power-ON clear voltage. The maximum value of the power-ON clear voltage is 1.8 V, and the actual value is in a range not exceeding this maximum value. For details, refer to 20.4.1 PowerON clear voltage. 179 PD17072,17073 19.3.5 Notes on using clock stop instruction The clock stop instruction ("STOP s") is valid only when the CE pin is at the low level. Therefore, it is necessary to design program taking into consideration the chance that the "STOP s" instruction is to be executed when the CE pin happens to be at the high level. Here is an example: Example XTAL CEJDG: ; <1> SKF1 BR CE MAIN Processing A ; <2> STOP ; <3> BR MAIN: Main processing BR CEJDG $-1 XTAL ; Clock stops ; Embedded macro ; Detects input level of CE pin ; Branches to main processing ; if CE = high level ; Processing when CE = low DAT 0000B ; Symbol definition of clock stop condition In this program example, the status of the CE pin is detected in <1>. If it is at the low level, the clock stop instruction "STOP XTAL" in <2> is executed after processing A has been performed. However, if the CE pin goes high while the "STOP XTAL" instruction is executed as shown below, the instruction is treated as a no-operation ("NOP") instruction. At this time, assuming that the branch instruction "BR $-1" in <3> is missing, the program execution enters the main processing, and malfunctioning may take place. Therefore, either insert the branch instruction as shown in <3>, or the program must be designed so that malfunctioning does not take place even after the execution enters the main processing. If the CE pin is at high level when the "STOP XTAL" instruction is executed, CE reset is effected when the basic timer 0 carry FF is set next time. 3V VDD 0V H CE pin L Main processing Processing A Program starts from address 0 in synchronization with setting of basic timer 0 carry FF (CE reset) <1> <1> <1> <2> STOP XTAL Treated as "NOP" CE pin is detected because CE pin is high 180 PD17072,17073 19.4 Device Operations in Halt and Clock Stop Statuses Table 19-1 shows the operations of the CPU and peripheral hardware in the halt and clock stop statuses. In the halt status, all the peripheral hardware continue the normal operation, except that instruction execution is stopped. In the clock stop status, all peripheral hardware stop. The peripheral control register that controls the operating status of the peripheral hardware operates normally (not initialized) in the halt status, but is initialized to a specified value in the clock stop status (when the "STOP s" instruction is executed). Each peripheral hardware continues the operation set in the peripheral control register in the halt status, and its operation status is determined by the initialized value of the peripheral control register in the clock stop status. For the value to which the peripheral control register is to be initialized, refer to chapter Table 8-1. Peripheral Hardware Functions of Peripheral Control Register. Here is an example: Example When P1C0/SO0 pin of port 1C is specified as output port pin, and P0B3/SI/SO1 pin and P0B2/SCK pins are used for serial interface HLTINT XTAL INITFLG ;<1> SET3 ;<2> BANK1 CLR1 INITFLG INITFLG SET1 EI ;<3> SET1 ;<4> HALT ;<5> STOP XTAL HLTINT SIOTS IRQSIO SIOCK1, SIOCK0 SIOSEL, NOT SIOHIZ IPSIO P0B3, P0B2 DAT DAT 1000B 0000B P0BBIO3,P0BBIO2 In the above example, the P0B3, P0B2 pins output high level in <1> , the condition of serial interface is set in <2> , and serial communication is started in <3>. When the "HALT" instruction is executed in <4>, the halt status is set, but the serial communication continues, and the halt status is released when the interrupt by the serial interface is accepted. If the "STOP" instruction in <5> is executed instead of the "HALT" instruction in <4>, the contents of all the peripheral control registers set in <1>, <2>, and <3> are initialized. Consequently, serial communication is stopped, and all the pins of the port 0B are set in the general-purpose input port mode. 181 PD17072,17073 Table 19-1. Device Operations in Halt and Clock Stop Statuses Status Hardware peripheral CE pin = high level In halt status Program counter Stops at address before HALT instruction Retained Retained Normal operation Normal operation In clock stop status CE pin = low level In halt status Stops at address before HALT instruction Retained Retained Normal operation Disabled In clock stop status Initialized to 0000H and stops InitializedNote Retained Stops Stops System register Peripheral register Timer PLL frequency synthesizer A/D converter BEEP Serial interface Frequency counter LCD controller/driver General-purpose I/O port General-purpose input port General-purpose output port Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation STOP instruction is invalid ("NOP") Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Stops Stops Stops Stops Stops Input port Normal operation Normal operation Normal operation Input port Normal operation Retained Note For the value to which these registers are initialized, refer to 4. DATA MEMORY (RAM), 5. SYSTEM REGISTER (SYSREG) and 8. PERIPHERAL CONTROL REGISTER. 19.5 Note on Processing of Each Pin in Halt and Clock Stop Statuses The halt status is used to reduce the current consumption of the device when, for example, only the watch is to be operated. The clock stop status is used to reduce the current consumption of the device to retain only the contents of the data memory. Therefore, the current consumption must be minimized in the halt and clock stop status. The current consumption may increase depending on the status of each pin and therefore, the points listed in Table 19-2 must be observed. 182 PD17072,17073 Table 19-2. Pin Status in Halt and Clock Stop Statuses and Notes (1/2) Pin status and note on processing Pin function Pin symbol Halt status Hold status immediately before halt status. (1) When specified as output pins Current consumption increases if any of these pins is externally pulled down while it outputs high level, or externally pulled up when it outputs low level. (2) When specified as input pins (Except P1A3/AD1, P1A2/AD0, P1A1, P1A0) Current consumption by noise does not increase if any of these pins is floated. (3) Port 1A (P1A3/AD1, P1A2/AD0, P1A1, P1A0) Current consumption increases if these pins externally pulled up when they selected pull-down resistors ON by program. When pull-down resistor OFF is selected, these pins are floated and current consumption by noise increases. (4) P0D3/FMIFC/AMIFC, P0D2/AMIFC When P0D3/FMIFC/AMIFC, P0D2/ AMIFC pins are used for frequency counter, current consumption increases because internal amplifier operates. Initialize frequency counter by program as necessary because it is not automatically disabled even when CE pin is low. Clock stop status All pins are specified as general-purpose input port pins. At this time, all input ports except port 1A (P1A3/AD1, P1A2/AD0, P1A1, P1A0) do not increase current consumption by noise, even if they are floated. Port 1A (P1A3/AD1, P1A2/AD0, P1A1, P1A0) is retained the status before clock stop. (1) When pull-down resistor ON is selected by program: Current consumption increases if these pins externally pulled up. (2) When pull-down resistor OFF is selected by program: These pins are floated and current consumption by noise increases. Port 0B P0B3/SI/SO1 P0B2/SCK P0B1 P0B0 Generalpurpose I/O port Port 0C P0C1 P0C0 Port 0D P0D3/FMIFC/AMIFC P0D2/AMIFC Generalpurpose input port Port 1A P1A3/AD1 P1A2/AD0 P1A1 P1A0 Port 0A P0A3 | P0A0 Generalpurpose output port Port 1B P1B3 | P1B0 These ports are specified as generalpurpose output ports. The output contents are retained as is. Therefore, current consumption increases if these ports are externally pulled down while they output high level, or pulled up while they output low level. Port 1C P1C0/SO0 Interrupt CE reset INT CE Current consumption increases by external noise if this pin is floated. Current consumption increases by external noise if this pin is floated. 183 PD17072,17073 Table 19-2. Pin Status in Halt and Clock Stop Statuses and Notes (2/2) Pin status and note on processing Pin function Pin symbol Halt status LCD segment LCD14 | LCD0 When these pins are used as general-purpose output port pins, the same points as those of the general-purpose output port described above must be observed. Current consumption increases when PLL operates. When PLL is disabled, VCOL, VCOH : floated EO : floated When CE pin goes low, PLL is automatically disabled. Current consumption changes with waveform oscillated by crystal oscillator circuit. The greater the oscillation amplitude, the lower the current consumption. Oscillation amplitude is varied depending on crystal resonator and load capacitor, and therefore must be evaluated. Clock stop status All pins are specified as LCD segment signal output pins and output low levels (display off). PLL frequency synthesizer VCOL VCOH EO PLL is disabled. Each pin is as follows: VCOL, VCOH : floated EO : floated Crystal oscillator circuit XIN XOUT XIN pin is internally pulled down and XOUT pin outputs high level 184 PD17072,17073 19.6 Device Control Function by CE Pin The CE pin has the following functions by using the input level and rising edge of a signal input from an external source: (1) PLL frequency synthesizer (2) Making clock stop instruction valid or invalid (3) Resets device 19.6.1 Controlling operation of PLL frequency synthesizer The PLL frequency synthesizer can operate only when the CE pin is high. When the CE pin is low, PLL is automatically disabled. When PLL is disabled, the VCOH and VCOL pins are floated, and the EO pin is also floated. The PLL frequency synthesizer can also be disabled through program even when the CE pin is high. 19.6.2 Making clock stop instruction valid or invalid The clock stop instruction ("STOP s") is valid only when the CE pin is low. The clock stop instruction executed when the CE pin is high is treated as an NOP (no operation) instruction. 19.6.3 Resetting device The device can be reset by raising the CE pin (CE reset). The device can also be reset by turning off supply voltage VDD (power-ON reset). For details, refer to 20. RESET. 185 PD17072,17073 19.6.4 Inputting signal to CE pin The CE pin does not accept a low- or high-level signal less than 200 s in order to protect the system from malfunctioning due to noise. The level of the signal input to the CE pin can be detected by using the CE flag of the CE pin status detection. Figure 19-5 shows the relations between the input signal and CE flag. Figure 19-5. Relations between Signal Input to CE Pin and CE Flag H L 1 CE flag 0 CE pin less than 200 s 200 s less than 200 s PLL disabled STOP s valid 200 s CE reset PLL disabled STOP s invalid (NOP) CE reset is effected in synchronization with next setting of basic timer 0 carry FF PLL enabled STOP s invalid (NOP) 19.6.5 Configuration and functions of CE pin status detection register The CE pin status detection register detects the level of the signal input to the CE pin. The configuration and functions of this register are illustrated below. Figure 19-6. Configuration of CE Pin Status Detection Register Flag symbol Name b3 CE pin status detection register b2 b1 b0 C E (BANK1) 52H Address Read/ Write 0 0 0 R Detects status of CE pin 0 1 Low level High level Fixed to "0" Power-ON At reset Clock stop CE 0 0 0 _ _ _ Remark -: Determined by status of pin The CE flag does not change even if a low or high level signal less than 200 s is input. 186 PD17072,17073 19.7 Low-Speed Mode Function The PD17073 can slow down the CPU clock when "1" is written to the SYSCK flag of the system clock select register. This function is called a low-speed mode function. The time required to execute one instruction in the low-speed mode is 106.6 s. However, the instruction that is executed immediately after the SYSCK flag has been set to "1" takes 103.3 s. By slowing down the CPU clock, the current consumption of the device can be lowered as compared with that during normal operation. Figure 19-7 shows the configuration and function of the system clock select register. Figure 19-7. Configuration of System Clock Select Register Flag symbol Name b3 b2 b1 b0 S Y System clock select register (BANK1) 0 0 0 S 55H C K Address Read/ Write R/W Selects system clock (one instruction execution time) 0 1 53.3 s 106.6 s Fixed to "0" Power-ON At Clock stop reset CE Remark R: Retained 0 0 0 0 R R 19.7.1 Releasing low-speed mode The low-speed mode is released when the SYSCK flag is reset to "0" by power-ON reset, or when "0" is written to the SYSCK flag. After the low-speed mode has been released, the CPU clock returns to the normal operation speed (one instruction execution time: 53.3 s). However, the instruction that is executed immediately after the SYSCK flag has been reset to "0" takes 56.6 s. 187 PD17072,17073 20. RESET The reset function is to initialize the device operation. 20.1 Configuration of Reset Block Figure 20-1 shows the configuration of the reset block. The device can be reset in two ways: by means of power-ON reset (or VDD reset) that is effected by applying supply voltage VDD, and CE reset that is effected by using the CE pin. The power-ON reset block consists of a voltage detector circuit that detects the voltage input to the VDD pin, a power failure detector circuit, and a reset control circuit. The CE reset block consists of a circuit that detects the rising of the signal input to the CE pin, and a reset control circuit. Figure 20-1. Configuration of Reset Block XOUT XIN BTM0CY flag read STOP s instruction Power failure detector block Timer FF block Divider R S Q Basic timer 0 carry Basic timer 0 carry disable FF Reset signal VDD Voltage detector circuit Rising detector circuit Power-ON clear signal (POC) Reset control circuit IRES RES RESET Forced halt by basic timer 0 carry Peripheral control register, system register, stack, program counter CE STOP instruction 188 PD17072,17073 20.2 Reset Function The power-ON reset is effected when supply voltage VDD has risen from a specific level, and the CE reset is effected when the CE pin goes high from low. The power-ON reset is to initialize the program counter, stack, system register, basic timer 0 carry FF and control register, and execute the program from address 0000H. The CE reset is to initialize part of the program counter, stack, system register, and peripheral control register, and execute the program from address 0000H. The main differences between the power-ON reset and CE reset are the contents of the peripheral control register to be initialized, and the operation of the power failure detector circuit, which is to be described in 20.6. The power-ON reset and CE reset are controlled by the reset signals IRES, RES, and RESET that are output from the reset control circuit shown in Figure 20-1. Table 20-1 shows the relations among the IRES, RES, and RESET signals, power-ON reset, and CE reset. The reset control circuit also operates when the clock stop instruction (STOP s) described in 19. STANDBY has been executed. The following 20.3 and 20.4 respectively describe the CE reset and power-ON reset. 20.5 describes the relations between the CE reset and power-ON reset. Table 20-1. Relations between Internal Reset Signal and Each Reset Output signal Internal reset signal At CE reset At powerON reset At clock stop Contents controlled by each reset signal IRES RES RESET x x Forcibly sets device in halt status, which is released by setting basic timer 0 carry FF. Initializes part of peripheral control register Initializes part of program counter, stack, system register, and peripheral control register. 189 PD17072,17073 20.3 CE Reset The CE reset is effected by making the CE pin high. When the CE pin goes high, the RESET signal is output in synchronization with the rising edge of the next basic timer 0 carry FF setting pulse, and the device is reset. When the CE reset has been effected, part of the program counter, stack, system register, and peripheral control register is initialized to an initial value by the RESET signal, and the program is executed from address 0000H. For the initial value, refer to the description of each register.The operation of the CE reset differs depending on whether the clock stop mode is used or not. This is described in 20.3.1 and 20.3.2. 20.3.3 describes the points to be noted when effecting the CE reset. 20.3.1 CE reset when clock stop mode (STOP s instruction) is not used Figure 20-2 shows the operation. When the clock stop mode (STOP s instruction) is not used, and after the CE pin has gone high, therefore, the RESET signal is output at the rising edge of the basic timer 0 carry FF setting pulse selected at that time (tSET = 125 ms), and reset is effected. Figure 20-2. CE Reset Operation When Clock Stop Mode Is Not Used 5V VDD 0V H CE L H XOUT L Basic timer 0 carry H FF setting pulse L H IRES Reset signals L H RES L H RESET L Normal operation Normal operation CE reset is effected at rising edge of basic timer 0 carry FF setting pulse. If basic timer 0 carry FF setting time tSET = 125 ms, 0 < t < 125 ms during this period because of the rising timing of the CE pin. During this period, the program continues operation. 190 PD17072,17073 20.3.2 CE reset when clock stop mode (STOP s instruction) is used Figure 22-3 shows the operation. When the clock stop mode is used, the IRES, RES, and RESET signals are output at the point where the "STOP s" instruction has been executed. While the CE pin is low, output of the IRES signal continues; therefore, the forced halt status, which is released by the basic timer 0 carry, is set. However, the device stops operation because the clock is stopped. When the CE pin goes high, the clock stop mode is released and oscillation is started. At this time, the halt status that is released by the basic timer 0 carry FF is set by the IRES signal. After the CE pin has risen, the oscillation stabilization status lasts (for 125 ms or longer). If the basic timer 0 carry FF setting pulse rises after that, the halt status is released, and program execution is started from address 0. Figure 20-3. CE Reset Operation When Clock Stop Mode Is Used 3V VDD 0V H CE L H XOUT L Basic timer 0 carry H FF setting pulse L H L H IRES Reset signals RES L H RESET L Normal operation Clock stop status Halt status 125 ms or more STOP 0000B instruction Clock stop released. Oscillation starts. CE reset Program starts from address 0. 20.3.3 Notes on CE reset Because CE reset is effected regardless of the instruction under execution, the following points (1) and (2) must be noted. (1) Time for executing timer processing such as watch To create a watch program by using the basic timer 0 or basic timer 1, the processing of the program must be completed within specific time. For details, refer to 12.2.5 Notes on using basic timer 0 and 12.3.4 Notes on using basic timer 1. (2) Processing of data or flag used in program Exercise care in rewriting data or flags that cannot be processed with one instruction and whose contents must not be changed even if CE reset is effected, such as security code. Here is an example: 191 PD17072,17073 Example 1. R1 R2 R3 R4 M1 M2 START: Key input processing R1 Key A contents R2 Key B contents SET2 SUB SUB SKT1 BR MAIN: Key input processing R3 Key C contents R4 Key D contents ST ST BR ERROR: Does not operate M1, R3 M2, R4 MAIN ; <2> ; <3> ; Security code rewriting mode ; Substitutes contents of ; pressed key into R3 and R4 ; Rewrites security code CMP, Z R1, M1 R2, M2 Z ERROR ; Input data is different from security code ; <1> ; Waits for key input of ; security code ; Substitutes contents of pressed code into R1 and R2 ; Compares security code with input data MEM MEM MEM MEM MEM MEM 0.01H 0.02H 0.03H 0.04H 0.11H 0.12H ; 1st digit of input data of security code ; 2nd digit of input data of security code ; Data of 1st digit when security code is changed ; Data of 2nd digit when security code is changed ; 1st digit of current security code ; 2nd digit of current security code Suppose the security code is "12H" in this example. Then the contents of the data memory addresses M1 and M2 are "1H" and "2H", respectively. When the CE reset is effected at this time, the contents of the key input in <1> are compared with the security code "12H", and if they are the same, the ordinary processing is performed. When the security code is changed by the main processing, the new code is rewritten to M1 and M2 in <2> and <3>. Suppose the security code is changed to "34H". Then "3H" and "4H" are written to M1 and M2 in <2> and <3>. However, if the CE reset happens to occur when <2> has been executed, the program is started from address 0000H without <3> executed. Consequently, the security code is changed to "32H", which is not intended, and security cannot be released. In this case, use the program shown in Example 2. 192 PD17072,17073 Example 2. R1 R2 R3 R4 M1 M2 CHANGE START: Key input processing R1 Key A contents R2 Key B contents SKT1 BR ST ST CLR1 SECURITY_CHK: SET2 SUB SUB SKT1 BR MAIN: Key input processing R3 Key C contents R4 Key D contents SET1 ST ST CLR1 BR ERROR: Does not operate CHANGE M1, R3 M2, R4 CHANGE MAIN ; Security code rewriting mode ; Substitutes contents of ; pressed key into R3 and R4 ; <5> ; Set CHANGE to "1" while security code is rewritten ; <2> ; Rewrites security code ; <3> ; Sets CHANGE flag to "0" after security code is rewritten CMP, Z R1, M1 R2, M2 Z ERROR ; Input data is different from security code ; <1> ; Compares security code with input data CHANGE SECURITY_CHK M1, R3 M2, R4 CHANGE ; rewrites M1 and M2 ; Waits for key input of ; security code ; Substitutes contents of pressed code into R1 and R2 ; <4> ; If CHANGE flag is 1, MEM MEM MEM MEM MEM MEM FLG 0.01H 0.02H 0.03H 0.04H 0.11H 0.12H 0.13H.0 ; 1st digit of input data of security code ; 2nd digit of input data of security code ; Data of 1st digit when security code is changed ; Data of 2nd digit when security code is changed ; 1st digit of current security code ; 2nd digit of current security code ; "1" while security code is changed In this example, the CHANGE flag is set to "1" in <5> before the security code is rewritten in <2> and <3>. Therefore, the security code is written again in <4> even if the CE reset is effected in <3>. 193 PD17072,17073 20.4 Power-ON Reset Power-ON reset is effected by raising the supply voltage VDD of the device from a specific level (called power-ON clear voltage). Power-ON clear voltage is described in 20.4.1. If the supply voltage VDD is lower than the power-ON clear voltage, a power-ON clear signal (POC) is detected from the voltage detector circuit shown in Figure 20-1. When the power-ON clear signal is output, the crystal oscillator circuit is stopped, and the device stops operation. While the power-ON clear signal is output, the IRES, RES, and RESET signals are output. When the supply voltage VDD exceeds the power-ON clear voltage, the power-ON clear signal is turned off, the crystal oscillator starts, and the IRES, RES, and RESET signals are also turned off. At this time, the halt status that is released by the basic timer 0 carry FF is set by the IRES signal. After the powerON clear signal is deasserted, the oscillation stabilization status lasts (for 125 ms or longer). If the basic timer 0 carry FF setting pulse rises after that, the halt status is released, and power-ON reset is effected. This operation is illustrated in Figure 20-4. At power-ON reset, the program counter, stack, system register, and peripheral control register are initialized as soon as the power-ON clear signal has been output. For the power-ON reset while the CPU is operating, refer to 20.4.2. For the power-ON reset in the clock stop status, refer to 20.4.3. For the power-ON reset when supply voltage VDD rises from 0 V, refer to 20.4.4. Figure 20-4. Operation of Power-ON Reset 3V VDD 0V H CE L H XOUT L Basic timer 0 carry H FF setting pulse Power-ON clear voltage Power-ON clear signal L H L H IRES Reset signals L H RES L H RESET L Normal operation Device operation stops Halt status 125 ms or more Power-ON clear released. Power-ON reset Oscillation starts. Program starts from address 0. 194 PD17072,17073 20.4.1 Power-ON clear voltage The power-ON clear voltage differs as follows, depending on the CPU operating temperature range and operating conditions: TA = 0 to +70 C : 1.6 V MAX. (when CPU is operating and PLL frequency synthesizer and A/D converter stop) TA = -10 to +70 C : 1.7 V MAX. (when CPU is operating and PLL frequency synthesizer and A/D converter stop) TA = -20 to +70 C : 1.8 V MAX. (when CPU, PLL frequency synthesizer, and A/D converter are operating) The above values are the maximum values, and the actual power-ON clear voltage must be in a range that does not exceed these maximum values. The power-ON clear voltage during the CPU operation is the same as that in the clock stop status. In the description below, the power-ON clear voltage is assumed to be 1.8 V. 20.4.2 Power-ON reset during normal operation Figure 20-5 (a) shows the operation. As shown in this figure, the power-ON clear signal is output regardless of the input level of the CE pin when the supply voltage VDD drops below 1.8 V (TA = -20 to +70 C, when CPU, PLL, A/D are operating), and the device operation is stopped. When the supply voltage VDD rises beyond 1.8 V again, the program starts from address 0000H after a halt status of 125 ms or more. The CPU operation includes when the clock stop instruction is not used, and power-ON clear voltage is 1.8 V during halt status set by the halt instruction. 20.4.3 Power-ON reset in clock stop mode Figure 20-5 (b) shows the operation. As shown in this figure, the power-ON clear signal is output and the device operation is stopped when the supply voltage VDD drops below 1.7 V (TA = -20 to +70 C, when CPU, PLL, A/D are operating). However, because the clock stop mode is set, the operation of the device seems not to be changed. When the supply voltage VDD rises beyond 1.8 V, the program starts from address 0000H after a halt of 125 ms or more. 20.4.4 Power-ON reset when supply voltage VDD rises from 0 V Figure 20-5 (c) shows the operation. As shown in this figure, the power-ON clear signal is output until the supply voltage VDD rises from 0 V to 1.8 V (TA = -20 to +70 C, CPU, PLL, A/D are operating). When the supply voltage VDD exceeds the power-ON clear voltage, the crystal oscillator circuit starts operating, and the program starts from address 0000H after a halt of 125 ms or more. 195 PD17072,17073 Figure 20-5. Power-ON Reset and Supply Voltage VDD (TA = -20 to +70 C, when CPU, PLL, A/D are operating) (a) During CPU operation (including halt status) 3V 1.8 V VDD 0V H CE XOUT Power-ON clear signal L H L H L Normal operation Device operation stops Power-ON clear voltage Halt status 125 ms or more Power-ON clear released. Power-ON reset Oscillation starts. Program starts from address 0. (b) In clock stop mode 3V 1.8 V VDD 0V CE XOUT Power-ON clear signal L H L Normal operation 1.7 V Power-ON clear voltage H L H Clock stop Device operation stops Halt status STOP s instruction 125 ms or more Power-ON clear released. Power-ON reset Oscillation starts. Program starts from address 0. (c) When supply voltage VDD rises from 0 V 3V VDD 0V H CE XOUT Power-ON clear signal L Device operation stops 1.8 V Power-ON clear voltage L H L H Halt status 125 ms or more Power-ON clear released. Power-ON reset Oscillation starts. Program starts from address 0. 196 PD17072,17073 20.5 Relations between CE Reset and Power-ON Reset There is a possibility that power-ON reset and CE reset are effected simultaneously when the supply voltage VDD is applied for the first time. The reset operations at this time are described in 20.5.1 through 20.5.3. 20.5.1 When VDD pin and CE pin rises simultaneously Figure 20-6 (a) shows the operation. At this time, the program starts from address 0000H because of power-ON reset. 20.5.2 When CE pin rises during forced halt status of power-ON reset Figure 20-6 (b) shows the operation. At this time, the program starts from address 0000H because of power-ON reset, in the same manner as 20.5.1 above. 20.5.3 When CE pin rises after power-ON reset Figure 20-6 (c) shows the operation. At this time, the program starts from address 0000H because of power-ON reset, and the program starts from address 0000H again at the rising edge of the next basic timer 0 carry FF setting signal because of CE reset. 197 PD17072,17073 Figure 20-6. Relations between Power-ON Reset and CE Reset (TA = -20 to +70 C, when CPU, PLL, A/D are operating) (a) When VDD and CE pins rises simultaneously 3V 1.8 V VDD 0V H CE L Basic timer 0 carry H FF setting pulse Power-ON clear voltage L Operation stops Halt status 125 ms or more Normal operation Power-ON reset Program starts. (b) When CE pin rises in halt status 3V 1.8 V VDD 0V H CE L Basic timer 0 carry FF setting pulse Power-ON clear voltage H L Operation stops Halt status 125 ms or more Normal operation Power-ON reset Program starts. (c) When CE pin rises after power-ON reset 3V 1.8 V VDD 0V H CE L Basic timer 0 carry FF setting pulse Power-ON clear voltage H L Operation stops Halt status 125 ms or more Normal operation Power-ON reset Program starts. CE reset Program starts. 198 PD17072,17073 20.6 Power Failure Detection The power failure detection feature is used to judge, when the device has been reset, whether the reset has been effected by application of supply voltage VDD or by the CE pin. Because the contents of the data memory and output ports are "undefined" on power application, the contents of these are initialized by detecting a power failure. The power failure can be detected by detecting the BTM0CY flag by using a power failure detector circuit. Figure 20-7. Power Failure Detection Flowchart Program starts Power failure Power failure detected Not power failure Initializes data memory and output ports 20.6.1 Power Failure Detector Circuit The power failure detector circuit consists of a voltage detector circuit as shown in Figure 20-1, basic timer 0 carry disable flip-flop that is reset by the output (power-ON clear signal) of the voltage detector circuit, and basic timer 0 carry. The basic timer 0 carry disable FF is set to 1 by the power-ON clear signal, and reset to 0 when an instruction that reads the BTM0CY flag has been executed. While the basic timer 0 carry disable FF is set to 1, the BTM0CY flag is not set to 1. If the power-ON clear signal is output (at power-ON reset), therefore, the program is started with the BTM0CY flag cleared, and setting of the BTM0CY flag is inhibited until an instruction that reads the BTM0CY flag is executed later. Once the instruction that reads the BTM0CY flag has been executed, the BTM0CY flag is set each time the basic timer 0 carry FF setting pulse rises. Therefore, whether power-ON reset (power failure) or CE reset (not power failure) has been effected can be judged by checking the content of the BTM0CY flag, when the device has been reset. That is, if the BTM0CY flag is cleared to 0, power-ON reset has been effected; if the flag is set to 1, CE reset has been effected. The voltage at which a power failure can be detected is the same voltage at which power-ON reset is effected. Figure 20-8 illustrates the status transition of the BTM0CY flag. Figure 20-9 shows the timing chart of Figure 20-8 and the operation of the BTM0CY flag. 199 PD17072,17073 Figure 20-8. Status Transition of BTM0CY Flag CE = low <1> CE = don't care VDD = low Operation stops CE = high VDD = L 1.8 VNote <2> Crystal oscillation starts. Forced halt (125 ms or more) <3> Setting BTM0CY flag inhibited <4> Clock stop STOP 0 <5> Normal operation CE = HL Power-ON reset CE = L CE = H <6> Normal operation <8> Normal operation. CE reset wait <9> Crystal oscillation starts. Forced halt (125 ms or more) Rising of basic timer 0 carry FF setting pulse BTM0CY = 0 <7> CE reset CE = LH CE = LH <10> SKT1 BTM0CY or SKF1 BTM0CY <11> SKT1 BTM0CY or SKF1 BTM0CY <12> Clock stop STOP 0 <13> Normal operation CE = HL <14> Normal operation <16> CE = LH BTM0CY = 1 <15> CE reset Rising of basic timer 0 carry FF setting pulse Setting BTM0CY flag enabled CE = LH Normal operation. CE reset wait <17> Crystal oscillation starts. Forced halt (125 ms or more) Note 1.8 V is the maximum value and the actual power-ON clear voltage is in a range that does not exceed this maximum value. For details, refer to 20.4.1 Power-ON clear voltage. 200 PD17072,17073 Figure 20-9. Operation of BTM0CY Flag (a) When BTM0CY flag is never detected (SKT1 BTM0CY or SKF1 BTM0CY is not executed) 3V VDD CE BTM0CY flag setting pulse 0V H L H L H L Operation in Figure 20-8 <1> <2> <6> <5> <8> <6> <5> <4> <9> <6> <1> BTM0CY <3> <7> <7> Timer time changed STOP 0000 B (b) To detect power failure with BTM0CY flag 3V VDD CE BTM0CY flag setting pulse 0V H L H L H L SKTI instruction <1> <2> <6> <14> <13> <16> <14> <13> <12> <17> <14> <1> BTM0CY Operation in Figure 20-8 <3> <11> <15> <15> Timer time changed BTM0CY = 0 Power failure BTM0CY = 1 Not power failure STOP 0000 B BTM0CY = 1 Not power failure 201 PD17072,17073 20.6.2 Notes on power failure detection with BTM0CY flag Keep in mind the following points when using the BTM0CY flag for watch counting: (1) Updating watch When creating a watch program by using the basic timer 0, it is necessary to update the watch after a power failure has been detected. This is because watch counting is skipped once because the BTM0CY flag is read when a power failure has been detected, and thus the BTM0CY flag is cleared to 0. (2) Watch updating processing time To update the watch, its processing must be completed before the next basic timer 0 carry FF setting pule rises. This is because CE reset is effected without the watch updating processing completed if the CE pin goes high while the watch updating processing is in progress. For further information on (1) and (2) above, refer to 12.2.5 (3) Adjusting basic timer 0 at CE reset. To perform power failure processing, the following points must be noted. (3) Power failure detection timing Watch counting with the BTM0CY flag must be completed before the next basic timer 0 carry FF setting pulse rises after the BTM0CY flag for power failure detection has been read and the program has been started from address 0000H. This is because, the basic timer 0 carry FF setting time is 125 ms, and if power failure detection is performed 126 ms after the program has been started, the BTM0CY flag is not detected once. For details, refer to 12.2.5 (3) Adjusting basic timer 0 at CE reset. Moreover, power failure detection and initial processing must be completed within the basic timer 0 carry FF setting time, as shown in the example on the next page. This is because, if he CE pin rises and CE reset is effected during power failure detection or initial processing, the processing is interrupted, resulting in troubles. To change the basic timer 0 carry FF setting time in the initial processing, one instruction must be used to change the setting time at the end of the initial processing. 202 PD17072,17073 Example Program example START: ;<1> Processing at reset ;<2> BANK1 SKT1 BR BACKUP: ;<3> Watch updating BR INITIAL: ;<4> Initial processing MAIN: Main processing SKT1 BR BR Operation example BTM0CY MAIN Watch updating MAIN MAIN BTM0CY INITIAL ; Power failure detection ; Program address 0000H 3V VDD 0V 125 ms H CE L 125 ms BTM0CY flag setting pulse H L <1> <4> < 2 > Power failure detection <1> <3> < 2 > Power failure detection If total processing time of If total processing time of < 1 > + < 4 > is 125 ms or longer, CE reset < 1 > + < 3 > is too long, CE reset is effected. is effected in the middle of processing. CE reset CE reset 203 PD17072,17073 21. PD17012 INSTRUCTIONS 21.1 Instruction Set Outline b15 b14-b11 BIN. 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 HEX. 0 1 2 3 4 5 6 ADD SUB ADDC SUBC AND XOR OR INC MOVT BR CALL RET RETSK EI DI RETI PUSH POP GET PUT RORC STOP HALT NOP LD SKE MOV SKNE BR BR r, m r, m r, m r, m r, m r, m r, m AR DBF, @AR @AR @AR ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 0 1 0 1 1 1 7 AR AR DBF, p p, DBF r s h 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 9 A B C D E F r, m m, #n4 @r, m m, #n4 addr (page 0) addr (page 1) ST SKGE MOV SKLT CALL MOV SKT SKF m, r m, #n4 m, @r m, #n4 addr (page 0) m, #n4 m, #n m, #n 204 PD17072,17073 21.2 Legend AR ASR addr BANK CMP CY DBF h INTEF INTR INTSK MP MPE m mR mC n n4 PAGE PC p pH pL r SP s (x) : Address register : Address stack register indicated by stack pointer : Program memory address (lower 11 bits) : Bank register : Compare flag : Carry flag : Data buffer : Halt release condition : Interrupt enable flag : Register automatically saved to stack when interrupt occurs : Interrupt stack register : Data memory row address pointer : Memory pointer enable flag : Data memory address indicated by mR, mC : Data memory row address (higher) : Data memory column address (lower) : Bit position (4 bits) : Immediate data (4 bits) : Page (bits 11 of program counter) : Program counter : Peripheral address : Peripheral address (higher 3 bits) : Peripheral address (lower 4 bits) : General register column address : Stack pointer : Stop release condition : Contents address by x 205 PD17072,17073 21.3 Instruction List Instruction group Instruction code Mnemonic Operand r, m ADD m, #n4 Addition ADDC m, #n4 INC SUB m, #n4 Subtraction r, m SUBC m, #n4 r, m OR m, #n4 Logical operation r, m AND m, #n4 r, m XOR m, #n4 SKT Judgment SKF SKE SKNE Compare SKGE SKLT Rotate RORC LD ST m, #n4 m, #n4 r r, m m, r @r, m Transfer MOV m, @r m, #n4 MOVT DBF, @AR (r) (m) (m) (r) if MPE = 1: (MP, (r)) (m) if MPE = 0: (BANK, mR, (r)) (m) if MPE = 1: (m) (MP, (r)) if MPE = 0: (m) (BANK, mR, (r)) (m) n4 SP SP -1, ASR PC, PC AR, DBF PC, PC ASR, SP SP + 1 (m) -n4, skip if not borrow (m) -n4, skip if borrow CY (r)b3 (r)b2 (r)b1 (r)b0 00111 01000 11000 01010 000 mR mR mR 0111 mC mC mC r r r r 11001 11011 mR mR mC mC n4 n4 m, #n m, #n4 m, #n4 m, #n AR r, m r, m (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY AR AR + 1 (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY (r) (r) v (m) (m) (m) v n4 v (r) (r) (m) v n4 Operation OP code 00000 10000 00010 10010 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 v n = n, then skip n = 0, then skip 11110 11111 01001 01011 mR mR mR mR 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR Operand mC mC mC mC r n4 r n4 1001 0000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC r n4 r n4 r n4 r n4 r n4 n n n4 n4 (m) (m) (r) (r) v (m) (m) (m) v n4 CMP 0, if (m) CMP 0, if (m) (m) -n4, skip if zero (m) -n4, skip if not zero 206 v 11010 11101 00111 mR mR 000 mC mC r n4 0001 0000 PD17072,17073 Instruction code Mnemonic PUSH POP Transfer GET PUT DBF, p p, DBF addr Branch BR @AR addr CALL @AR Subroutine RET RETSK RETI EI Interrupt DI STOP Others HALT NOP s h Operand AR AR Operation OP code SP SP - 1, ASR AR AR ASR, SP SP + 1 DBF (p) (p) DBF PC10-0 addr, PAGE 0 PC10-0 addr, PAGE 1 PC AR SP SP - 1, ASR PC, PC10-0 addr, PAGE 0 SP SP - 1, ASR PC, PC AR PC ASR, SP SP + 1 PC ASR, SP SP + 1 and skip PC ASR, INTR INTSK, SP SP + 1 INTEF 1 INTEF 0 STOP HALT No operation 00111 00111 00111 00111 01100 addr 01101 00111 11100 00111 00111 00111 00111 00111 00111 00111 00111 00111 000 000 001 010 000 001 010 011 100 000 0100 0000 addr 0101 0000 1110 0000 1110 0000 1110 0000 1111 0000 1111 0000 1111 1111 s h 000 000 pH pH Operand 1101 0000 1100 0000 1011 1010 pL pL Instruction group 1111 0000 21.4 Assembler (AS17K) Embedded Macroinstructions Legend flag n : FLG type symbol <> : Item in < > can be omitted. Mnemonic SKTn SKFn SETn Embedded macro NOTn flag 1, ...flag n INITFLG 207 PD17072,17073 22. PD17073 RESERVED WORDS 22.1 Data Buffer (DBF) Symbol name DBF3 DBF2 DBF1 DBF0 Attribute MEM MEM MEM MEM Value 0.0CH 0.0DH 0.0EH 0.0FH R/W R/W R/W R/W R/W Bits 15-12 of DBF Bits 11-8 of DBF Bits 7-4 of DBF Bits 3-0 of DBF Description 22.2 System Register (SYSREG) Symbol name AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE Attribute MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG Value 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0 R/W R R/W R/W R/W R R/W R R R R R R R R/W R/W R/W R/W R/W R/W R Description Bits 15-12 of address register (fixed to "0") Bits 11-8 of address register Bits 7-4 of address register Bits 3-0 of address register Window register (fixed to "0") Bank register (Only lower 1 bit is valid) Index register, high Memory pointer, high Memory pointer enable flag Index register, middle Memory pointer, low Index register, low General register pointer, high General register pointer, low (only lower 1 bit is valid) Program status word BCD operation flag Compare flag Carry flag Zero flag Index enable flag (fixed to "0") (fixed to "0") 208 PD17072,17073 22.3 LCD Segment Register Symbol name LCDD14 LCDD13 LCDD12 LCDD11 LCDD10 LCDD9 LCDD8 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 Attribute MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM Value 1.41H 1.42H 1.43H 1.44H 1.45H 1.46H 1.47H 1.48H 1.49H 1.4AH 1.4BH 1.4CH 1.4DH 1.4EH 1.4FH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LCD segment register Description 209 PD17072,17073 22.4 Port Register Symbol name P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 P0C1 P0C0 P0D3 P0D2 P1A3 P1A2 P1A1 P1A0 P1B3 P1B2 P1B1 P1B0 P1C0 Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.70.3 0.70H.2 0.70H.1 0.70H.0 0.71H.3 0.71H.2 0.71H.1 0.71H.0 0.72H.1 0.72H.0 0.73H.3 0.73H.2 1.70H.3 1.70H.2 1.70H.1 1.70H.0 1.71H.3 1.71H.2 1.71H.1 1.71H.0 1.72H.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 3 of port 0A Bit 2 of port 0A Bit 1 of port 0A Bit 0 of port 0A Bit 3 of port 0B Bit 2 of port 0B Bit 1 of port 0B Bit 0 of port 0B Bit 1 of port 0C Bit 0 of port 0C Bit 3 of port 0D Bit 2 of port 0D Bit 3 of port 1A Bit 2 of port 1A Bit 1 of port 1A Bit 0 of port 1A Bit 3 of port 1B Bit 2 of port 1B Bit 1 of port 1B Bit 0 of port 1B Bit 0 of port 1C Description ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- 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------------------------------------------------------------------------------------------------------------- 210 PD17072,17073 22.5 Peripheral Control Register Symbol name ADCON LCDEN BTM0CY CE P1APLD3 P1APLD2 P1APLD1 P1APLD0 SP SYSCK INT BTM1CK IEG IPSIO IPBTM1 IP IRQ IRQBTM1 IRQSIO BEEP0CK1 BEEP0CK0 ADCCH3 ADCCH2 ADCCH1 ADCCH0 ADCRFSEL3 ADCRFSEL2 ADCRFSEL1 ADCRFSEL0 ADCSTRT ADCCMP SIOSEL SIOHIZ SIOTS SIOCK3 SIOCK2 SIOCK0 SIOCK0 IFCMD1 Attribute FLG FLG FLG FLG FLG FLG FLG FLG MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLGQ FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 1.50H.1 1.50H.0 1.51H.0 1.52H.0 1.53H.3 1.53H.2 1.53H.1 1.53H.0 1.54H 1.55H.0 1.56H.2 1.56H.1 1.56H.0 1.57H.2 1.57H.1 1.57H.0 1.58H.0 1.59H.0 1.5AH.0 1.5BH.1 1.5BH.0 1.5CH.3 1.5CH.2 1.5CH.1 1.5CH.0 1.5DH.3 1.5DH.2 1.5DH.1 1.5DH.0 1.5EH.0 1.5FH.0 1.60H.2 1.60H.1 1.60H.0 1.61H.3 1.61H.2 1.61H.1 1.61H.0 1.62H.3 R/W R/W R/W Description A/D converter control signal power setting flag LCD driver display start flag ------------------------------------------------------------------------------------------------------------- R&Res Basic timer 0 carry FF status detection flag R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R R R/W R/W R/W IF counter mode select flag (10, 11: AMIF) Serial interface I/O clock select flag A/D converter compare start flag A/D converter compare result detection flag Serial in/serial out pin select flag Serial interface/general-purpose port select flag Serial interface transmit/receive start flag Serial interface I/O clock select flag (fixed to "0") A/D converter reference voltage setting flag A/D converter channel select flag A/D converter channel select flag (fixed to "0") CE pin status detection flag P1A3 pin pull-down resistor select flag P1A2 pin pull-down resistor select flag P1A1 pin pull-down resistor select flag P1A0 pin pull-down resistor select flag Stack pointer System clock select flag INT pin status detection flag Basic timer 1 clock select flag INT pin interrupt request detection edge direction select flag Serial interface interrupt enable flag Basic timer 1 interrupt enable flag INT pin interrupt enable flag INT pin interrupt request detection flag Basic timer 1 interrupt request detection flag Serial interface interrupt request detection flag BEEP clock select flag ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- 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-------------------------------------------- 211 PD17072,17073 Symbol name IFCMD0 INCCK1 IFCCK0 IFCG IFCSTRT IFCRES PLLMD3 PLLMD2 PLLMD1 PLLMD0 PLLRFCK3 PLLRFCK2 PLLRFCK1 PLLRFCK0 PLLR17 PLLR16 PLLR15 PLLR14 PLLR13 PLLR12 PLLR11 PLLR10 PLLR9 PLLR8 PLLR7 PLLR6 PLLR5 PLLR4 PLLR3 PLLR2 PLLR1 PLLPUT PLLUL P0BBIO3 P0BBIO2 P0BBIO1 P0BBIO0 P0DBIO3 P0DBIO2 P0CBIO1 P0CBIO0 Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 1.62H.2 1.62H.1 1.62H.0 1.63H.0 1.64H.1 1.64H.0 1.65H.3 1.65H.2 1.65H.1 1.65H.0 1.66H.3 1.66H.2 1.66H.1 1.66H.0 1.67H.3 1.67H.2 1.67H.1 1.67H.0 1.68H.3 1.68H.2 1.68H.1 1.68H.0 1.69H.3 1.69H.2 1.69H.1 1.69H.0 1.6AH.3 1.6AH.2 1.6AH.1 1.6AH.0 1.6BH.3 1.6CH.0 1.6DH.0 1.6EH.3 1.6EH.2 1.6EH.1 1.6EH.0 1.6FH.3 1.6FH.2 1.6FH.1 1.6FH.0 R/W R/W R/W R/W R W W R R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W PLL data set flag PLL data flag PLL reference frequency select flag (fixed to "0") PLL reference frequency select flag PLL mode select flag IF counter gate status detection flag (1: open, 0: close) IF counter count start flag IF counter reset flag PLL mode select flag (fixed to "0") Description IF counter mode select flag (00: general-purpose I/O port, 01: FMIF) IF counter clock select flag ------------------------------------------------------------------------------------------------------------- -------------------------------------------- ------------------------------------------------------------------------------------------------------------- -------------------------------------------- ------------------------------------------------------------------------------------------------------------- -------------------------------------------- ------------------------------------------------------------------------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- -------------------------------------------- R&Res PLL unlock FF flag R/W R/W R/W R/W R/W R/W R/W R/W P0B3 input/output select flag P0B2 input/output select flag P0B1 input/output select flag P0B0 input/output select flag P0D3 input/output select flag P0D2 input/output select flag P0C1 input/output select flag P0C0 input/output select flag ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------- 212 PD17072,17073 22.6 Peripheral Hardware Register Symbol name SIOSFR AR IFC Attribute DAT DAT DAT Value 03H 40H 43H R/W R/W R/W R Description Serial interface presettable shift register Address register of GET/PUT/PUSH/CALL/BR/MOVT instruction Intermediate frequency (IF) counter data register 22.7 Others Symbol name DBF Attribute DAT Value 0FH Description Fixed operand value of PUT, GET, and MOVT instructions 213 PD17072,17073 23. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Symbol VDD VI CE pin Other than CE pin Output voltage Output current, high VO fOH 1 pin Total of all pins Output current, low IOL 1 pin Total of all pins Operating ambient temperature Storage temperature TA Tstg Condition Rating -0.3 to +4.0 -0.3 to VDD +0.6 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -3.0 -20.0 3.0 20.0 -20 to +70 -55 to +125 Unit V V V V mA mA mA mA C C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the absolute maximum ratings specify the values exceeding which the product may be physically damaged. Be sure to use the product with these ratings never exceeded. Recommended Operating Range Parameter Supply voltage Symbol VDD1 Condition With CPU, PLL, and AD operating TA = -20 to +70 C VDD2 With CPU operating and PLL and AD stopped Supply voltage rise time trise VDD: 0 1.8 V TA = -10 to +70 C TA = 0 to +70 C 1.7 1.6 3.0 3.0 3.6 3.6 500 V V mS MIN. 1.8 TYP. 3.0 MAX. 3.6 Unit V 214 PD17072,17073 DC Characteristics (TA = -20 to +70 C, VDD = 1.8 to 3.6 V) Parameter Supply voltage Symbol VDD1 Condition With CPU, PLL, and AD operating TA = -20 to +70 C With CPU operating, and PLL and AD stopped Supply current IDD1 TA = -10 to +70 C TA = 0 to +70 C MIN. 1.8 TYP. 3.0 MAX. 3.6 Unit V VDD2 1.7 1.6 3.0 3.0 6.5 3.6 3.6 10 V V mA With CPU and PLL operating Sine wave input to VCOH pin (fIN = 230 MHz, VIN = 0.2 VP-P) VDD = 3 V, TA = 25 C With CPU operating and PLL stopped (IF counter stopped) Sine wave input to XIN pin (fIN = 75 kHz, VIN = VDD) VDD = 3 V, TA = 25 C With CPU and PLL stopped (with HALT instruction used) Sine wave input to XIN pin (fIN = 75 kHz, VIN = VDD) LCD display OFF, VDD = 3 V, TA = 25 C On power failure detection When crystal oscillation stopped TA = 25 C, VDD = 3.0 V CE, INT, P0B0-P0B3, P0C0, P0C1, P0D2, P0D3 0.8 VDD P1A0-P1A3 CE, INT, P0B0-P0B3, P0C0, P0C1, P0D2, P0D3 P1A0-P1A3 P0A0-P0A3, P0B0-P0B3, P1B0-P1B3, P0C0, P0C1, P0D2, P0D3, P1C0, BEEP VOH = VDD - 0.5 V EO LCD0-LCD14 VOH = VDD - 0.5 V VOH = VDD - 0.5 V -0.5 0.5 VDD 1.7 IDD2 35 45 A IDD3 10 18 A Data retention voltage Data retention current VDDR IDDR V 3 A V V Input voltage, high VIH1 VIH2 Input voltage, low VIL1 VIL2 0.2 VDD 0.05 VDD V V mA Output current, high IOH1 IOH2 IOH3 Output current, low IOL1 -0.2 -20 0.5 mA A mA P0A0-P0A3, P0B0-P0B3, P0C0, P0C1, P0D2, P0D3, P1C0, BEEP VOL = 0.5 V EO P1B0-P1B3 LCD0-LCD14 With P1A0-P1A3 pulled down VIH = VDD = 1.8 V VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V IOL2 IOL3 IOL4 Input current, high IIH1 0.2 5 20 3 30 mA A A A A 3.1 3.3 V IIH2 With XIN pulled down VIH = VDD = 1.8 V 40 LCD drive voltage VLCD1 With LCD0-LCD14 output open C1 = 0.1 F, C2 = 0.01 F TA = 25 C EO 2.8 Output off leakage current IL 1 A 215 PD17072,17073 AC Characteristics (TA = -20 to +70 C, VDD = 1.8 to 3.6 V) Parameter Operating frequency Symbol fIN1 Condition VCOL pin, MF mode Sine wave input, VIN = 0.2 VP-P VCOL pin, HF mode Sine wave input, VIN = 0.3 VP-P VCOH pin, VHF mode Sine wave input, VIN = 0.2 VP-P AMIFC pin, FMIFC pin, AMIF count mode Sine wave input, VIN = 0.1 VP-P AMIFC pin, FMIFC pin, AMIF count mode Sine wave input, VIN = 0.15 VP-P FMIFC pin, FMIF count mode Sine wave input, VIN = 0.1 VP-P MIN. 0.3 TYP. MAX. 8 Unit MHz fIN2 5 130 MHz fIN3 40 230 MHz fIN4 400 500 kHz fIN5 0.4 2 MHz fIN6 10 11 MHz A/D Converter Characteristics (TA = 25 C, VDD = 1.8 V) Parameter A/D converter Symbol 4-bit resolution Condition MIN. TYP. MAX. 1.5 Unit LSB 216 PD17072,17073 24. PACKAGE DRAWINGS 56 PIN PLASTIC QFP (10 10) A B 42 43 29 28 detail of lead end CD S Q R 56 1 15 14 F J G P H I M K M N NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 12.80.4 10.00.2 10.00.2 12.80.4 0.8 0.8 0.300.10 0.13 0.65 (T.P.) 1.40.2 0.60.2 0.15 +0.10 -0.05 0.10 1.7 0.1250.075 55 2.0 MAX. INCHES 0.5040.016 0.3940.008 0.3940.008 0.5040.016 0.031 0.031 0.0120.004 0.005 0.026 (T.P.) 0.0550.008 0.024 +0.008 -0.009 0.006 +0.004 -0.003 0.004 0.067 0.0050.003 55 0.079 MAX. S56GB-65-1A7-3 217 PD17072,17073 64 PIN PLASTIC TQFP (FINE PITCH) ( A B 10) 48 49 33 32 detail of lead end C D S 64 F 17 1 16 G H I M J K P N NOTE L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 12.00.2 10.00.2 10.00.2 12.00.2 1.25 1.25 0.22 +0.055 -0.045 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.00.1 0.10.05 3 +7 -3 1.27 MAX. INCHES 0.472 +0.009 -0.008 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.472 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.039 +0.005 -0.004 0.0040.002 3 +7 -3 0.050 MAX. S64GB-50-9EU-1 Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 218 M Q R PD17072,17073 25. RECOMMENDED SOLDERING CONDITIONS Solder the PD17073 under the following recommended conditions. For the details of the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 25-1. Soldering Conditions for Surface-Mount Type (1) PD17072GB-xxx-1A7: 56-pin plastic QFP (10 x 10 mm, 0.65-mm pitch) PD17073GB-xxx-1A7: 56-pin plastic QFP (10 x 10 mm, 0.65-mm pitch) Soldering Method Soldering Condition Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.) Number of times: 2 MAX. Package peak temperature: 215 C, Time: 40 seconds MAX. (200 C MIN.) Number of times: 2 MAX. Soldering bath temperature: 260 C MAX., Time: 10 seconds MAX., Number of times: 1, Preheating temperature: 120 C MAX. (package surface temperature) Pin partial heating Pin temperature: 300 C MAX., Time: 3 seconds MAX. (per side of device) -- Symbol of Recommended Soldering IR35-00-2 Infrared reflow VPS VP15-00-2 Wave soldering WS60-00-1 (2) PD17072GB-xxx-9EU: 64-pin plastic TQFP (10 x 10 mm, 0.5-mm pitch) PD17073GB-xxx-9EU: 64-pin plastic TQFP (10 x 10 mm, 0.5-mm pitch) Soldering Method Soldering Condition Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.) Number of times: 1, Number of days: 2Note (after that, prebaking at 125 C for 10 hours is necessary) Package peak temperature: 215 C, Time: 40 seconds MAX. (200 C MIN.) Number of times: 1, Number of days: 2Note (after that, prebaking at 125 C for 10 hours is necessary) Pin temperature: 300 C MAX., Time: 3 seconds (per side of device) Symbol of Recommended Soldering IR35-102-1 Infrared reflow VPS VP15-102-1 Pin partial heating -- Note The number of days for which the device can be stored after the dry pack is opened, at 25 C, 65%RH MAX. Caution Do not use two or more soldering methods in combination (except pin partial heating). 219 PD17072,17073 APPENDIX A. NOTES ON CONNECTING CRYSTAL RESONATOR When connecting a crystal resonator to the PD17073, connect the part enclosed by dotted line in Figure A-1 below as follows to avoid adverse influence of wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of lines through which a high current flows. * The ground of the capacitors of the oscillation circuit must be always at the same potential as GND. Do not ground to a ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. To connect the capacitors or to adjust the oscillation frequency, keep in mind the following points (1) through (3): (1) If the values of C1 and C2 are too high, the oscillation characteristics may be degraded or the current consumption increases. (2) A trimmer capacitor for oscillation frequency adjustment is generally connected to the XIN pin. Depending on the crystal resonator to be used, however, the oscillation stability may be degraded as a result of connecting a trimmer capacitor to the XIN pin (in this case, connect the trimmer capacitor to the XOUT pin). Therefore, evaluate oscillation by using the crystal resonator to be actually used. (3) Adjust the oscillation frequency while measuring the LCD drive waveform (62.5 Hz) or VCO oscillation frequency. If a probe is connected to the XOUT or XIN pin, accurate adjustment cannot be made due to the capacitance of the probe. Figure A-1. Connecting Crystal Resonator PD17073 XOUT XIN 75 kHz crystal resonator C2 C1 220 PD17072,17073 APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for development of the program of the PD17073: Hardware Name Outline In-circuit emulator IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators common to 17K series. [IE-17K, IE-17K-ETNote1, IE-17K and IE-17K-ET are connected to host machine such as PC-9800 series or IBM PC/ATTM EMU-17KNote2] with RS-232-C. EMU-17K is mounted in expansion slot of host machine, PC-9800 series. By using these in-circuit emulators in combination with system evaluation board (SE board) dedicated to each model of microcontroller, they operate as emulators dedicated to that microcontroller. When SIMPLEHOST (R), which is man-machine interface, is used, more sophisticated debugging environment can be created. EMU-17K also has function that allows you to monitor contents of data memory real-time. SE board (SE-17072) SE-17072 is SE board for PD17072 and 17073. It may be used alone to evaluate system, or in combination with in-circuit emulator for debugging. EP-17K56GB is an emulation probe for the 17K series 56-pin QFP (10 x 10 mm). By using this emulation probe with the EV-9500GB-56Note 3, the SE board and target system are connected. Emulation probe (EP-17K56GB) EP-17K56GB-1: Bend lead package EP-17K56GB-2: Inverted lead package Emulation probe (EP-17K64GB: bend lead package) Conversion adapter (EV-9500GB-56) Conversion adapter (EV-9500GB-64) EP-17K64GB is an emulation probe for the 17K series 64-pin TQFP (10 x 10 mm). By using this emulation probe with the EV-9500GB-64Note 3, the SE board and target system are connected. EV-9500GB-56 is a conversion adapter for a 56-pin QFP (10 x 10 mm). It is used to connect the EP-17K56GB and target system. EV-9500GB-64 is a conversion adapter for a 64-pin TQFP (10 x 10 mm). It is used to connect the EP-17K64GB and target system. Notes 1. Low-cost model: External power supply type 2. This is a product from I.C. For details, contact I.C Corp. ((03) 3447-3793). 3. One EV-9500GB-56 is supplied with the EP-17K56GB. Five EV-9500GB-56 are also available as a set. One EV-9500GB-64 is supplied with the EP-17K64GB. Five EV-9500GB-64 are also available as a set. 221 PD17072,17073 Software Name 17K-Series Assembler (AS17K) Outline AS17K is an assembler that can be commonly used with the 17K series products. To develop the program of the PD17072 and 17073, AS17K and a device file (AS17071) are used. AS17071 is a device file for PD17072 and 17073, and is used with 17K series assembler (AS17K). Host Machine PC-9800 series OS MS-DOSTM Supply Media 5"2HD 3.5"2HD IBM PC/AT PC DOSTM 5"2HC 3.5"2HC PC-9800 series MS-DOS 5"2HD 3.5"2HD IBM PC/AT PC DOS 5"2HC 3.5"2HC Support SIMPLEHOST is software that Software serves as a man-machine (SIMPLEHOST) interface on WindowsTM when a program is developed with an in-circuit emulator and a personal computer. PC-9800 series MS-DOW Windows 5"2HD 3.5"2HD IBM PC/AT PC DOS 5"2HC 3.5"2HC Order Code S5A10AS17K S5A13AS17K S7B10AS17K S7B13AS17K S5A10AS17071 S5A13AS17071 S7B10AS17071 S7B13AS17071 S5A10IE17K S5A13IE17K S7B10IE17K S7B13IE17K Device File (AS17071) Remark Supported OS versions are listed below. OS MS-DOS PC DOS Windows Version Ver. 3.30 to Ver. 5.00ANote Ver. 3.1 to Ver. 5.0Note Ver. 3.0 to Ver. 3.1 Note Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but it is not supported by this software product. 222 PD17072,17073 [MEMO] 223 PD17072,17073 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 224 PD17072,17073 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 225 PD17072,17073 SIMPLEHOST is a registerd trademark of NEC Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 226 |
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