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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78CP18(A)
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD78CP18(A) is a version of the PD78C18(A) in which the internal mask ROM is replaced by one-time PROM. The one-time PROM version can be programmed once only by users, and is ideally suited for small-scall of many differnt products, and rapid development and time-to-market of a new product. The detailed functions are descrived in the following user's manual. Read this manual before starting design work. 87AD series PD78C18 user's manual: IEU-1314
FEATURES
* High reliability compared to the PD78CP18 * Compatible with the PD78C11A(A), 78C12A(A), 78C14(A), 78C18(A) * Internal PROM: 32768 W x 8 * Internal PROM capacity can be changed by software to conform to the PD78C11A(A), 78C12A(A), 78C14(A), 78C18(A). * PROM programming characteristics: PD27C256A compatible * Power supply voltage range: 5 V 10 % * Supports QTOPTM microcomputer Remark QTOP microcomputer is the generic name of NEC's single-chip microcomputers for which NEC provides total service including writing, marking, screening, and inspection. 5
ORDERING INFORMATION
Part Number Package 64-pin plastic QFP (14 x 20 mm) 64-pin plastic QUIP Internal ROM One-time PROM One-time PROM
PD78CP18GF(A)-3BE PD78CP18GQ(A)-36
QUALITY GRADE
Part Number Quality Grade Special Special
PD78CP18GF(A)-3BE PD78CP18GQ(A)-36
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. The mark Document No. IC-3233A (O. D. No. IC-8702A) Date Published March 1995 P Printed in Japan
5
shows major revised points.
(c)
1994 1993
PD78CP18(A)
PIN CONFIGURATION (TOP VIEW)
A0/PA0 A1/PA1 A2/PA2 A3/PA3 A4/PA4 A5/PA5 A6/PA6 A7/PA7 PB0 PB1 PB2 PB3 PB4 PB5 CE/PB6 OE/PB7 PC0/TXD PC1/RXD PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 A9/NMI INT1 MODE1 RESET MODE0 X2 X1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD STOP/VPP PD7/O7 PD6/O6 PD5/O5 PD4/O4 PD3/O3 PD2/O2 PD1/O1 PD0/O0 PF7 PF6/A14 PF5/A13 PF4/A12 PF3/A11 PF2/A10 PF1 PF0/A8 ALE WR RD AVDD VAREF AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS
PD78CP18GQ(A)-36
2
PD78CP18(A)
PF6/A14
PF5/A13
PF4/A12
PF3/A11
PF2/A10
PD2/O2
PD1/O1
PD0/O0
PF0/A8
VAREF
AVDD
AN7
AN6
O3/PD3 O4/PD4 O5/PD5 O6/PD6 O7/PD7 VPP/STOP VDD A0/PA0 A1/PA1 A2/PA2 A3/PA3 A4/PA4 A5/PA5
51 52 53 54 55 56 57 58 59 60 61 62 63 64 1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33 32 31 30 29 28 27
AN5
ALE
PF7
PF1
WR
RD
AN4 AN3 AN2 AN1 AN0 AVSS VSS X1 X2 MODE0 RESET MODE1 INT1
PD78CP18GF(A)-3BE
26 25 24 23 22 21
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20 19
A6/PA6
A7/PA7
PB0
PC0/TXD
PC3/INT2
PC4/TO
PC6/CO0
PC7/CO1
PC2/SCK
PC5/CI
PC1/RXD
A9/NM1
PB1
PB2
PB3
PB4
PB5
CE/PB6
OE/PB7
3
PORT F
MAIN G.R 10 PROM (32-KBYTE) ALT G.R
Note
16 8
PORT D
4
8
PORT C
8 PC5/CI PC6/CO0 PC7/CO1 TIMER/EVENT COUNTER 16 8 LATCH 16 LATCH
INTERNAL DATA BUS 6 PSW 8 INST. REG
8
8
PORT B
AN7 to AN0 VAREF AVDD AVSS
8 A/D CONVERTER 8
16
16 8 ALU (8/16) INST. DECODER
PORT A
4
X1 OSC X2 16 LATCH INC/DEC PC SP EA V B D H 8 INT1 INT. CONTROL EA' V' B' D' H' BUFFER PC3/INT2/TI TIMER PC4/TO 8 8/16 A' C' E' L' A C E L 8 PF7/AB15 5 PF6/A14/AB14 to PF2/A10/AB10 PF1/AB9 PF0/A8/AB8 8 15 8 PC0/TXD PC1/RXD PC2/SCK SERIAL I/O 8 8 PD7/O7/AD7 to PD0/O0/AD0 A9/NMI DATA MEMORY (1-KBYTE) 8 PC7 to PC0 8 8 OE/PB7 CE/PB6 6 PB5 to PB0 8 PA7/A7 to PA0/A0 16 READ/WRITE CONTROL SYSTEM CONTROL STANDBY CONTROL RD WR ALE MODE1 MODE0 RESET VPP/STOP VDD VSS
BLOCK DIAGRAM
PD78CP18(A)
Note Can be used only when RAE bit of MM register is 1. External memory is needed in case of 0.
PD78CP18(A)
DIFFERENCES BETWEEN THE PD78CP18(A) AND PD78CP18
Product Name Item Quality grade Electrical specifications Package Special Input leakage current AN7 to AN0: 1 A (MAX.) * 64-pin plastic QFP (14 x 20 mm) * 64-pin plastic QUIP Standard Input leakage current AN7 to AN0; 10 A (MAX.) 64-pin plastic shrink DIP (750 mil) 64-pin plastic QUIP 64-pin plastic QFP (14 x 20 mm) 64-pin ceramic shrink DIP with window (750 mil) * 64-pin ceramic WQFN * * * *
PD78CP18(A)
PD78CP18
5
PD78CP18(A)
CONTENTS 1. LIST OF PORT FUNCTIONS .......................................................................................................................7
1.1 1.2 1.3 1.4 PORT FUNCTIONS ...............................................................................................................................................7 NON-PORT FUNCTIONS (IN NORMAL OPERATION) ..................................................................................... 8 NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ) .....................................................10 HANDLING OF UNUSED PINS .........................................................................................................................10
2. 3.
MEMORY CONFIGURATION ....................................................................................................................11 MEMORY EXTENSION .............................................................................................................................16
3.1 3.2 MODE PINS ........................................................................................................................................................16 MEMORY MAPPING REGISTER (MM) ............................................................................................................17
4.
PROM PROGRAMMING ...........................................................................................................................20
4.1 4.2 4.3 PROM PROGRAMMING OPERATING MODES ...............................................................................................21 PROM WRITING PROCEDURE .........................................................................................................................22 PROM READING PROCEDURE .........................................................................................................................23
5. 6. 7. 8. 9.
SCREENING OF ONE-TIME PROM VERSIONS ......................................................................................24 ELECTRICAL SPECIFICATIONS ................................................................................................................25 CHARACTERISTIC CURVES (REFERENCE VALUE) ..............................................................................39 PACKAGE DRAWINGS .............................................................................................................................42 RECOMMENDED SOLDERING CONDITIONS ........................................................................................44
10. DIFFERENCES BETWEEN THE PD78CP18(A) AND PD78C18(A) .....................................................45 APPENDIX. DEVELOPMENT TOOLS ..........................................................................................................46
6
PD78CP18(A)
1. LIST OF PORT FUNCTIONS
1.1 PORT FUNCTIONS
Pin Name PA7 to PA0 (Port A) PB7 to PB0 (Port B) PC7 to PC0 (Port C) PD7 to PD0 (Port D) PF7 to PF0 (Port F) 8-bit input-output port, which can specify input/output in byte units. I/O Input/Output
Function 8-bit input-output port, which can specify input/output bit-wise.
8-bit input-output port, which can specify input/output bit-wise.
Remark
These port pins have alternate function pins as shown in 1.2 "NON-PORT FUNCTIONS (IN NORMAL OPERATION)" and 1.3 "NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ)".
7
PD78CP18(A)
1.2
NON-PORT FUNCTIONS (IN NORMAL OPERATION)
Alternate Function Pin PC0 PC1 Serial data output pin
Pin Name TXD (Transmit Data) RXD (Receive Data) SCK (Serial Clock)
I/O Output
Function
Input
Serial data input pin
Input/output
PC2
Serial clock input/output pin. Output when internal clock is used, input when external clock is used. Edge trigger (falling edge) maskable interrupt input pin
INT2 Input (Interrupt Request) TI (Timer Input) Zero-cross TO (Timer Output) CI (Counter Input) CO0 and CO1 (Counter Output 0, 1) AD7 to AD0 (Address/Data Bus 7 to 0) AB15 to AB8 (Address Bus 15 to 8) WR (Write Strobe) Input
PC3
Timer external clock input pin
Input Output PC4
AC input zero-cross detection pin During timer count time, square wave with one internal clock cycle as one half cycle is output. Timer/event counter external pulse input pin
Input
PC5
Output
PC6 and PC7
Square wave output programmable by timer/event counter.
Input/output
PD7 to PD0
Multiplexed address/data bus when external memory is used
Output
PF7 to PF0
Address bus when external memory is used
Output
Strobe signal which is output for write operation of external memory. It becomes high in any cycle other than the data write machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes high-impedance. Strobe signal which is output for read operation of external memory. It becomes high in any cycle other than the data read machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance. Strobe signal to latch externally the lower address information which is output to PD7 to PD0 pins to access external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes highimpedance. Set MODE0 pin to "0" (low level), and MODE1 pin to "1" (high level)Note
RD (Read Strobe)
Output
Output ALE (Address Latch Enable) MODE0 MODE1 (Mode) NMI (Non-Maskable Interrupt) Input Input/output
Input
Non-maskable interrupt input pin of the edge trigger (falling edge)
Note Pull-up. Pull-up resister R is 4 [k] R 0.4 tCYC [k] (tCYC is ns unit).
8
PD78CP18(A)
Pin Name INT1 (Interrupt Request) AN7 to AN0 (Analog Input) VAREF (Reference Voltage) AVDD (Analog VDD) AVSS (Analog VSS) X1, X2 (Crystal) Input
I/O
Alternate Function Pin
Function A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a zero-cross detection pin for AC input. 8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection (falling edge) input. A common pin serving both as a reference voltage input pin for A/D converter and as a control pin for A/D converter operation. Power supply pin for A/D converter. GND pin for A/D converter. Crystal connection pins for system clock oscillation. X1 should be input when a clock is supplied from outside. Inverted clock of X1 should be input in X2.
Input Input
RESET (Reset) STOP (Stop) VDD VSS
Input
Low-level active system reset input.
Input
Hardware STOP mode control signal input pin. When the low level is input to this pin, the oscillation stops. Positive power supply pin. GND pin.
9
PD78CP18(A)
1.3
NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ)
Alternate Function Pin PA7 to PA0 PB6 PB7 PD7 to PD0 PF6 to PF2 PF0 Input Input NMI Set MODE0 pin to "1" (high level), and MODE1 pin to "0" (low level). Address lower 8 bit input pins Chip enable signal input pin Output enable signal input pin Data input/output pins Address higher 7 bit input pins Function
Pin Name A7 to A0 CE OE O7 to O0 A14 to A10 A8 A9 MODE0 MODE1 RESET VPP Input Input Input
I/O
Input/output Input
Input STOP
Set to "0" (low level). High-voltage application pin "1" (high level) is input when EPROM is read.
1.4
HANDLING OF UNUSED PINS
Pin PA7 PB7 PC7 PD7 PF7 to to to to to PA0 PB0 PC0 PD0 PF0 Recommended Connection
Connect to VSS or VDD via resistor.
RD WR ALE STOP INT1, NMI AVDD VAREF AVSS AN7 to AN0
Leave open.
Connect to VDD. Connect to VSS or VDD. Connect to VDD. Connect to VSS. Connect to AVSS or AVDD.
10
PD78CP18(A)
2. MEMORY CONFIGURATION
The PD78CP18(A) memory can operate in the following 4 modes according to the mode specification. q q q q
PD78C11A mode (see Figure 2-1) PD78C12A mode (see Figure 2-2) PD78C14 mode (see Figure 2-3) PD78C18 mode (see Figure 2-4)
In addition, the internal PROM and internal RAM address ranges can be specified for efficient mapping of external memory (excluding PROM) (see 3.2 "MEMORY MAPPING REGISTER (MM)"). The vector area and call table area are common to all modes. Setting the hardware/software STOP mode or HALT mode enables internal RAM data to be retained at a low consumption current.
11
PD78CP18(A)
Figure 2-1. Memory Map (PD78C11A Mode)
0000H
0000H RESET
Internal PROM 4096W x 8
0004H NMI
0008H INTT0/INTT1 0FFFH 1000H
0010H INT1/INT2
External Memory 61184W x 8 Vector Area
0018H INTE0/INTE1
0020H INTEIN/INTAD FEFFH FF00H Internal RAM 256W x 8 FFFFH 0028H INTSR/INTST
0060H SOFTI
0080H 0081H Call Table Area 0082H 0083H
LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS
t=0 t=1
00BEH 00BFH 00C0H
LOW ADRS HIGH ADRS
t = 31
USER'S AREA
0FFFH
12
PD78CP18(A)
Figure 2-2. Memory Map (PD78C12A Mode)
0000H
0000H RESET
Internal PROM 8192W x 8
0004H NMI
0008H INTT0/INTT1 1FFFH 2000H
0010H INT1/INT2
External Memory 57088W x 8 Vector Area
0018H INTE0/INTE1
0020H INTEIN/INTAD FEFFH FF00H Internal RAM 256W x 8 FFFFH 0028H INTSR/INTST
0060H SOFTI
0080H 0081H Call Table Area 0082H 0083H
LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS
t=0 t=1
00BEH 00BFH 00C0H
LOW ADRS HIGH ADRS
t = 31
USER'S AREA
1FFFH
13
PD78CP18(A)
Figure 2-3. Memory Map (PD78C14 Mode)
0000H
0000H RESET
Internal PROM 16384W x 8
0004H NMI
0008H INTT0/INTT1 3FFFH 4000H
0010H INT1/INT2
External Memory 48896W x 8 Vector Area
0018H INTE0/INTE1
0020H INTEIN/INTAD FEFFH FF00H Internal RAM 256W x 8 FFFFH 0028H INTSR/INTST
0060H SOFTI
0080H 0081H Call Table Area 0082H 0083H
LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS
t=0 t=1
00BEH 00BFH 00C0H
LOW ADRS HIGH ADRS
t = 31
USER'S AREA
3FFFH
14
PD78CP18(A)
Figure 2-4. Memory Map (PD78C18 Mode)
0000H
0000H RESET
Internal PROM 32768W x 8
0004H NMI
0008H INTT0/INTT1 7FFFH 8000H
0010H INT1/INT2
External Memory 31744W x 8 Vector Area
0018H INTE0/INTE1
0020H INTEIN/INTAD FBFFH FC00H Internal RAM 1024W x 8 FFFFH 0028H INTSR/INTST
0060H SOFTI
0080H 0081H Call Table Area 0082H 0083H
LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS
t=0 t=1
00BEH 00BFH 00C0H
LOW ADRS HIGH ADRS
t = 31
USER'S AREA
7FFFH
15
PD78CP18(A)
3. MEMORY EXTENSION
The PD78CP18(A) allows external memory extension by means of the MEMORY MAPPING register (MM) or the MODE0 and MODE1 pins. Also, the internal PROM and internal RAM access areas can be specified by means of bits MM7, MM6 and MM5 of the MEMORY MAPPING register. 3.1 MODE PINS The PD78CP18(A) can be switched between programming mode and normal operation mode according to the specification of the MODE0 and MODE1 pins. Table 3-1 shows the modes set by the MODE pins. Table 3-1. Modes Set By MODE Pins
MODE1 L L H H MODE2 L H L H Operating Mode Setting prohibited Programming modeNote Normal operation mode Setting prohibited
Note See 4. "PROM PROGRAMMING". When MODE0 and MODE1 are driven high, a 4 [k] R 0.4 tCYC [k] pull-up resistor should be used (tCYC: ns units).
16
PD78CP18(A)
3.2
MEMORY MAPPING REGISTER (MM)
The MEMORY MAPPING register is an 8-bit register which performs the following controls: * Port/extension mode specification for PD7 to PD0 and PF7 to PF0 * Enabling/disabling of internal RAM accesses * Specification of internal PROM and RAM access areas The configuration of the MEMORY MAPPING register is shown in Figure 3-1. (1) Bits MM2 to MM0 These bits control the PD7 to PD0 port/extension mode specification, input/output specification, and the PF7 to PF0 address output specification. As shown in Figure 3-1, there is a choice of four capacities for the connectable external memory: * 256 bytes * 4 Kbytes * 16 Kbytes * 32 K/48 K/56 K/60 Kbytes (set by bits MM7 to MM5) Ports of PF7 to PF0 not used as address outputs can be used as general-purpose ports. When RESET signal is input or in the hardware STOP mode, these bits are reset to (0) and PD7 to PD0 are set to input port mode (high-impedance). (2) MM3 bit (RAE) This bit enables (RAE = 1) and disables (RAE = 0) internal RAM access. This bit should be set to "0" during standby operation and when externally connected RAM, not internal RAM, is used. In normal operation this bit retains its value when RESET signal is input. However, the RAE bit is undefined after a power-on reset, and must therefore be initialized by an instruction. (3) Bits MM7 to MM5 These bits specify the access area of the internal PROM. When STOP or RESET signal is input, these bits are reset, selecting the 32-Kbyte mode (PD78C18 mode). These bits are only valid in the PD78CG14, 78CP14, 78CP18, 78CP14(A), and 78CP18(A); if data is written to these bits in the PD78C11A(A), 78C12A(A), 78C14(A), or 78C18(A), it will be ignored. Therefore, a program developed on the PD78CP18(A) can be directly ported to mask ROM.
17
PD78CP18(A)
Figure 3-1. MEMORY MAPPING Register Format
7 MM7 6 5 4 3 RAE 2 MM2 1 MM1 0 MM0
MM6 MM5
0 0 0 Port Single chip mode 001 0 1 0 Exten- 256 bytes sion mode 100 4 Kbytes
110
16 Kbytes
111
32 K/48 K/ 56K/60KNote bytes
PD7 to PD0 = Input port PF7 to PF0 = Port mode PD7 to PD0 = Output port PF7 to PF0 = Port mode PD7 to PD0 = Extension mode PF7 to PF0 = Port mode PD7 to PD0 = Extension mode PF3 to PF0 = PF7 to PF4 = Port mode PD7 to PD0 = Extension mode PF5 to PF0 = PF7 & PF6 = Port mode PD7 to PD0 = Extension mode PF7 to PF0 =
Note
Depends on MM7 to MM5 bit-setting
Internal RAM Access 0 1 Disable Enable
Internal PROM/RAM Access Areas MM7 0 MM6 0 MM5 0 Internal PROM Access Area 0000H to 7FFFH (32 Kbytes: PD78C18 mode) 0000H to 3FFFH (16 Kbytes: PD78C14 mode) 0000H to 1FFFH (8 Kbytes: PD78C12A mode) 0000H to 0FFFH (4 Kbytes: PD78C11A mode) Internal RAM Access Area FC00H to FFFFH (1 Kbyte) FF00H to FFFFH (256 bytes) FF00H to FFFFH (256 bytes) FF00H to FFFFH (256 bytes)
0
0
1
0
1
1
1
0
1
Other than above
Setting Prohibited
18
PD78CP18(A)
Figure 3-2. External Extension Modes Set by MEMORY MAPPING Register
Port Mode 0 0 256-Byte Extension Mode 0 4-KByte Extension Mode
Internal PROM (4/8/16/32 KBytes)
Internal PROM (4/8/16/32 KBytes)
Internal PROM (4/8/16/32 KBytes)
Not Used

Not Used External Memory(4 KBytes) External Memory(256 Bytes) Not Used Not Used Internal RAM Internal RAM Internal RAM 64K 64K 64K 16-KByte Extension Mode 32-/48-/56-/60-KByte Extension Mode 0 0 Internal PROM (4/8/16/32 KBytes) Internal PROM (4/8/16/32 KBytes) External Memory (16 KBytes) 64K
Not Used
Caution
The internal PROM and internal RAM access areas are determined by MM7 to MM5.

Not Used Internal RAM Internal RAM 64K
External Memory (32/48/56/ 60 KBytes)
19
PD78CP18(A)
4. PROM PROGRAMMING
The PD78CP18(A) incorporates 32768 x 8-bit PROM as a program memory. The pins shown in Table 4-1 are used for write/verify operations on this PROM. PD78CP18(A) program timing is compatible with the PD27C256A. Please read the following in conjunction with documentation of the PD27C256A. Table 4-1. Pins Used in PROM Programming
Pin Name RESET MODE0 MODE1 VPP CE
Note
Function Low-level input (at write/verify and read) High-level input (at write/verify and read) Low-level input (at write/verify and read) High-voltage input (at write/verify), high-level input (at read) Chip enable input Output enable input
Note
OE
Note Note
A14 to A0 O7 to O0 VDD
Address input Data input (at write), data output (at verify, read) Supply voltage input
Note
Note
Note These pins correspond to the PD27C256A. Caution The PD78CP18(A) one-time PROM version is not equipped with an erasure window, and therefore ultraviolet erasure cannot be performed on it.
20
PD78CP18(A)
4.1
PROM PROGRAMMING OPERATING MODES
The PROM programming operating mode is set as shown in Table 4-2. Pins not used for programming should be handled as shown in Table 4-3. Table 4-2. PROM Programming Modes
Operating Mode Program Program verify Program inhibit Read Output disable Standby Note CENote OENote L H H L L H H L H L H L/H +5 V +5 V VPPNote +12.5 V VDDNote +6 V RESET L MODE0 H MODE1 L
These pins correspond to the PD27C256A.
Caution When +12.5 V is applied to VPP and +6 V is applied to VDD, setting both CE and OE to "L" is prohibited.
Table 4-3. Recommended Connection of Unused Pins (in PROM Programming Mode)
Pin INT1 X1 AN0 to AN7 VAREF AVDD AVSS Pins other than the above X2 Connect to VSS via individual resistor. Leave open. Recommended Connection Connect to VSS.
21
PD78CP18(A)
4.2
PROM WRITING PROCEDURE
The PROM writing procedure is as shown below, allowing high-speed writing. (1) Connect unused pins to VSS via a pull-down resistor, and supply +6 V to VDD and +12.5 V to VPP. (2) Provide the initial address. (3) Provide the write data. (4) Provide a 1-ms program pulse (active low) to the CE pin. (5) Verify mode. If written, go to (7); if not written, repeat (3) to (5). If the write operation has failed 25 times, go to (6). (6) Halt write operation due to defective device. (7) Provide write data and program pulse of X times x 3 ms (X; repeated times from (3) to (5)) (additional write). (8) Increment the address. (9) Repeat (3) to (8) until the final address. Figure 4-1. PROM Write/Verify Timing
Repeated X Times
Write
Verify
Additional Write
A14/PF6-A10/PF2 A9/NMI A8/PF0 Address (Higher 7 Bits)
A7/PA7-A0/PA0
Address (Lower 8 Bits)
O7/PD7-O0/PD0
Data Input
Data Output
Data Input
VPP VPP VIH
VDD + 1 VDD VDD
VIH CE/PB6 VIL VIH OE/PB7 VIL
22
PD78CP18(A)
4.3
PROM READING PROCEDURE
PROM contents can be read onto the external data bus (O7 to O0) using the following procedure. (1) Connect unused pins to VSS via a pull-down resistor. (2) Supply +5 V to the VDD and VPP pins. (3) Input address of data to be read to pins A14 to A0. (4) Read mode (5) Output data to pins O7 to O0. Timing for steps (2) to (5) above is shown in Figure 4-2. Figure 4-2. PROM Read Timing
A14/PF6-A10/PF2 A9/NMI A8/PF0 Address Input
CE/PB6
OE/PB7
O7/PD7-O0/PD0
Data Output
23
PD78CP18(A)
5. SCREENING OF ONE-TIME PROM VERSIONS
Because of their construction, one-time PROM versions cannot be fully tested by NEC before shipment. After the necessary data has been written, it is recommended that screening be implemented in which PROM verification is performed after high-temperature storage under the following conditions.
Storage Temperature 125 C
Storage Time 24 hours
5
NEC provides writing, marking, screening, and inspection services for single-chip microcomputers labeld QTOP microcomputers. For details, consult NEC.
24
PD78CP18(A)
6. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
PARAMETER
SYMBOL VDD AVDD
TEST CONDITIONS
RATINGS -0.5 to +7.0 AVSS to VDD + 0.5 -0.5 to +0.5 -0.5 to +13.5
UNIT V V V V V V V mA mA mA mA V C C
Power supply voltage AVSS VPP Other than NMI/A9 pin Input voltage VI NMI/A9 pin Output voltage VO All output pins Output current low IOL Total of all output pins All output pins Output current high IOH Total of all output pins A/D converter reference input voltage Ambient operating temperature Storage temperature VAREF TA Tstg -50 -0.5 to AVDD + 0.3 -40 to +85 -65 to +150 100 -2.0 -0.5 to +13.5 -0.5 to VDD + 0.5 4.0
-0.5 to VDD + 0.5
5
Caution
If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product with these rated values never exceeded.
5
25
PD78CP18(A)
(TA = -40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V, VDD -0.8 V AVDD VDD, 3.4 V VAREF AVDD)
OSCILLATOR CHARACTERISTICS
RESONATOR
RECOMMENDED CIRCUIT
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
X1
X2
A/D converter not used Oscillator frequency (fXX)
4
15
Ceramic or crystal resonator
C1 C2
MHz
A/D converter used
5.8
15
A/D converter not used
X1 X2
4
15 MHz
X1 input frequency (fX) A/D converter used 5.8 15
External clock X1 rise time, fall time (tr, tf)
HCMOS Inverter
0
20
ns
X1 input high-, lowlevel width (tH, tL)
20
250
ns
Cautions
1. Place the oscillator as close as possible to the X1 and X2 pins. 2. Ensure that no other signal lines pass through the shaded area.
26
PD78CP18(A)
CAPACITANCE (TA = 25 C, VDD = VSS = 0 V)
PARAMETER Input capacitance Output capacitance Input-output capacitance
SYMBOL CI CO CIO
TEST CONDITIONS
MIN.
TYP.
MAX. 10
UNIT pF pF pF
fC = 1 MHz Unmeasured pins returned to 0 V
20 20
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V)
PARAMETER
SYMBOL VIL1
TEST CONDITIONS All except RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7 RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7 All except RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7, X1, X2 RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7, X1, X2 IOL = 2.0 mA IOH = -1.0 mA
MIN. 0
TYP.
MAX. 0.8
UNIT V
Input voltage low VIL2 0 0.2VDD V
VIH1 Input voltage high VIH2 Output voltage low VOL
2.2
VDD
V
0.8 VDD
VDD 0.45
V V V
VDD - 1.0 VDD - 0.5 200 10 1 10 0.5 10 16 7 2.5 1 10 15 50 1.3 20 35 13
Output voltage high
VOH IOH = -100 A V
Input current
II
INT1Note1, TI(PC3)Note2 ; 0 V VI VDD All except INT1, TI (PC3), AN7 to AN0; 0 V VI VDD AN7 to AN0; 0 V VI VDD
A A A A
mA
Input leakage current
ILI
Output leakage current AVDD power supply current
ILO AIDD1 AIDD2 IDD1 IDD2 VDDDR
0 V VO VDD Operating mode fXX = 15 MHz STOP mode Operating mode fXX = 15 MHz HALT mode fXX = 15 MHz Hardware/software STOP mode Hardware/softwareNote3 VDDDR = 2.5 V VDDDR = 5 V 10 %
A
mA mA V
VDD power supply current Data retention voltage Data retention current
A A
IDDDR STOP mode
5
Notes 1. If self-bias should be generated by ZCM register. 2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register. 3. If self-bias is not generated.
27
PD78CP18(A)
AC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V) READ/WRITE OPERATION:
PARAMETER X1 input cycle time Address setup time (to ALE ) Address hold time (from ALE ) RD delay time from address Address float time from RD Data input time from address Data input time from ALE Data input time from RD RD delay time from ALE Data hold time (from RD ) ALE delay time from RD
SYMBOL tCYC tAL tLA tAR tAFR tAD tLDR CL = 150 pF
TEST CONDITIONS
MIN. 66 30
MAX. 167
UNIT ns ns ns ns
fXX = 15 MHz, CL = 150 pF
35 100 20 250 135
ns ns ns ns ns ns ns ns
fXX = 15 MHz, CL = 150 pF tRD tLR tRDH tRL CL = 150 pF fXX = 15 MHz, CL = 150 pF In data read fXX = 15 MHz, CL = 150 pF RD low-level width tRR In OP code fetch fXX = 15 MHz, CL = 150 pF ALE high-level width WR delay time from address Data output time from ALE Data output time from WR WR delay time from ALE Data setup time (to WR ) Data hold time (from WR ) ALE delay time from WR WR low-level width tLL tAW fXX = 15 MHz, CL = 150 pF tLDW tWD tLW tDW tWDH tWL tWW fXX = 15 MHz, CL = 150 pF CL = 150 pF 15 127 60 80 215 197 140 ns ns ns ns ns ns ns fXX = 15 MHz, CL = 150 pF 415 90 100 ns ns ns 15 0 80 215 120
ZERO-CROSS CHARACTERISTICS :
PARAMETER Zero-cross detection input Zero-cross accuracy Zero-cross detection input frequency SYMBOL VZX AZX fZX AC coupling 60-Hz sine wave 0.05 TEST CONDITIONS MIN. 1 MAX. 1.8 135 1 UNIT VACP-P mV kHz
28
PD78CP18(A)
SERIAL OPERATION :
PARAMETER SYMBOL TEST CONDITIONS Note1 SCK input SCK cycle time tCYK SCK output Note1 SCK input SCK low-level width tKKL SCK output Note1 SCK input SCK high-level width tKKH SCK output RXD setup time (to SCK ) RXD hold time (from SCK ) TXD delay time from SCK tRXK tKRX tKTX Note1 Note1 Note1 Note2 160 700 80 80 210 ns ns ns ns ns Note2 160 700 335 ns ns ns Note2 400 1.6 335 ns MIN. 800 MAX. UNIT ns
s
ns
Notes 1. If clock rate is x 1 in asynchronous mode, synchronous mode, or I/O interface mode. 2. If clock rate is x 16 or x 64 in asynchronous mode. Remark The numeric values in the table are those when fXX = 15 MHz, CL = 100 pF.
OTHER OPERATION :
PARAMETER TI high-, low-level width SYMBOL tTIH, tTIL * Event counter mode tCI1H, tCI1L * Frequency test mode CI high-, low-level width tCI2H, tCI2L * Pulse width test mode * ECNT latch and clear input * INTEIN set input NMI high-, low-level width INT1 high-, low-level width INT2 high-, low-level width AN4 to AN7, low-level width RESET high-, low-level width tNIH, tNIL tI1H, tI1L tI2H, tI2L tANH, tANL tRSH, tRSL 10 36 36 36 10 48 tCYC 6 tCYC TEST CONDITIONS MIN. 6 MAX. UNIT tCYC
s
tCYC tCYC tCYC
s
29
PD78CP18(A)
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = +5.0 V 10 %, VSS = AVSS = 0 V, VDD - 0.5 V AVDD VDD, 3.4 V VAREF AVDD)
PARAMETER Resolution
SYMBOL
TEST CONDITIONS
MIN. 8
TYP.
MAX.
UNIT Bits
3.4 V VAREF AVDD, 66 ns tCYC 167 ns Absolute accuracyNote 4.0 V VAREF AVDD, 66 ns tCYC 167 ns TA = -10 to +70 C, 4.0 V VAREF AVDD, 66 ns tCYC 167 ns 66 ns tCYC 110 ns Conversion time tCONV 110 ns tCYC 167 ns 66 ns tCYC 110 ns Sampling time tSAMP 110 ns tCYC 167 ns 576 432 96 72 -0.3 50 3.4 Operating mode STOP mode Operating mode fXX = 15 MHz STOP mode 1.5 0.7 0.5 10
0.8 % 0.6 % 0.4 %
FSR FSR FSR tCYC tCYC tCYC tCYC
Analog input voltage
VIAN RAN VAREF IAREF1
VAREF + 0.3
V M
5
Analog input impedance Reference voltage
AVDD 3.0 1.5 1.3 20
V mA mA mA
VAREF current IAREF2 AVDD power supply current AIDD1 AIDD2
A
Note Quantization error (1/2 LSB) is not included.
AC Timing Test Point
VDD - 1.0 V 0.45 V
2.2 V 0.8 V
Test Points
2.2 V 0.8 V
30
PD78CP18(A)
tCYC-Dependent AC Characteristics Expression
PARAMETER tAL tLA tAR tAD tLDR tRD tLR tRL 2T - 100 T - 30 3T - 100 7T - 220 5T - 200 4T - 150 T - 50 2T - 50 4T - 50 (In data read) tRR 7T - 50 (In OP code fetch) tLL tAW tLDW tLW tDW tWDH tWL tWW 2T - 40 3T - 100 T + 130 T - 50 4T - 140 2T - 70 2T - 50 4T - 50 12T tCYK 6T 24T 5T + 5 tKKL 2.5T + 5 (SCK input)Note1 (SCK input)Note2 (SCK output) (SCK input)Note1 (SCK input)Note2 MIN. ns MIN. ns MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. ns ns ns ns ns ns ns ns MIN. ns EXPRESSION MIN./MAX. MIN. MIN. MIN. MAX. MAX. MAX. MIN. MIN. UNIT ns ns ns ns ns ns ns ns
12T - 100 (SCK output) 5T + 5 tKKH 2.5T + 5 (SCK input)Note1 (SCK input)Note2 MIN. ns
12T - 100 (SCK output)
Notes 1. If clock rate is x1, in asynchronous mode, synchronous mode, or I/O interface mode. 2. If clock rate is x16, x64 in asynchronous mode. Remarks 1. 2. T = tCYC = 1/fXX Other items which are not listed in this table are not dependent on oscillator frequency (fXX).
31
PD78CP18(A)
Timing Waveforms Read Operation
tCYC X1
PF7 to PF0 tAD PD7 to PD0 Address (Lower) tLL ALE tAL RD tLR tAR tLA tAFR tLDR
Address (Higher)
Read Data
tRDH tRL
tRD tRR
Write Operation
X1
PF7 to PF0 tLDW PD7 to PD0 Address (Lower) tLL ALE tAL WR tLW tAW tLA tWD
Address (Higher)
Write Data tDW tWDH
tWW
tWL
32
PD78CP18(A)
Serial Operation
tCYK tKKL SCK tKTX TXD tKKH
RXD tRXK tKRX
Timer Input Timing
tTIH
tTIL
TI
Timer/Event Counter Input Timing
Event Counter Mode tCI1H tCI1L
CI
Pulse Width Test Mode tCI2H tCI2L
CI
33
PD78CP18(A)
Interrupt Input Timing
tNIH tNIL
NMI
tI1L
tI1H
INT1
tI2H
tI2L
INT2
Reset Input Timing
tRSH tRSL
RESET
0.8VDD 0.2VDD
External Clock Timing
tH
0.8VDD X1 0.8 V tr tCYC tf tL
34
PD78CP18(A)
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85 C)
PARAMETER Data retention power supply voltage Data retention power supply current VDD rise/fall time STOP setup time (to VDD) STOP hold time (from VDD) SYMBOL VDDDR VDDDR = 2.5 V IDDDR VDDDR = 5 V 10 % 200 12T + 0.5 Note 12T + 0.5 Note TEST CONDITIONS MIN. 2.5 1 10 TYP. MAX. 5.5 15 50 UNIT V
A A s s s
5
tRVD, tFVD tSSTVD
tHVDST
Note T= tCYC = 1/fXX
Data Retention Timing
90 % VDD 10 % tFVD tSSTVD STOP VDDDR tRVD tHVDST VIH2 VIL2
35
PD78CP18(A)
DC PROGRAMMING CHARACTERISTICS (TA = 25 5 C, MODE1 = VIL, MODE0 = VIH, VSS = 0 V)
PARAMETER Input voltage high Input voltage low Input leakage current Output voltage high Output voltage low Output leakage current VDDP supply voltage SYMBOL VIH VIL ILIP VOH VOL ILO SYMBOLNote VIH VIL ILI VOH VOL
--
TEST CONDITIONS
MIN. 2.4 -0.3
TYP.
MAX. VDDP + 0.3 0.8 10
UNIT V V
0 VI VDDP; except INT1, TI (PC3) IOH = -1.0 mA IOL = 2.0 mA 0 VO VDDP, OE = VIH EPROM programming mode 5.75 4.5 12.2 6.0 5.0 12.5 VPP = VDDP 5 5 VDD - 1.0
A
V
0.45 10 6.25 5.5 12.8
V
A
V V V V
VDDP
VDD EPROM read mode
VPP supply voltage
VPP
VPP
EPROM programming mode EPROM read mode EPROM programming mode
50 50
mA mA
VDDP supply current
IDD
IDD
EPROM read mode CE = VIL, VI = VIH EPROM programming mode CE = VIL, OE = VIH EPROM read mode
VPP supply current
IPP
IPP
5 1
30 100
mA
A
Note Corresponding PD27C256A symbol
36
PD78CP18(A)
AC PROGRAMMING CHARACTERISTICS (TA = 25 5 C, MODE1 = VIL, MODE0 = VIH, VSS = 0 V)
PARAMETER Address setup time (to CE) OE delay time from data Input data setup time (to CE) Address hold time (from CE) Input data hold time (from CE) Output data hold time (from OE) VPP setup time (to CE) VDDP setup time (to CE) Initial program pulse width Additional program pulse width EPROM programming/read mode setup time (to CE)Note2 Data output time from address Data output time from CE Data output time from OE Data hold time (from OE) Data hold time (from address) SYMBOL tSAC tDDOO tSIDC tHCA tHCID tHOOD tSVPC tSVDC tWL1 tWL2 tSMC tDAOD tDCOD tDOOD tHCOD tHAOD SYMBOLNote1 tAS tOES tDS tAH tDH tDF tVPS tVDS tPW tOPW -- tACC tCE tOE tDF tOH OE = VIL 0 0 OE = VIL TEST CONDITIONS MIN. 2 2 2 2 2 0 2 2 0.95 2.85 2 1 1 1 130 1.0 1.05 78.75 130 TYP. MAX. UNIT
s s s s s
ns
s s
ms ms
s s s s
ns ns
Notes 1. Corresponding PD27C256A symbol 2. Indicates state in which MODE1 = VIL and MODE0 = VIH.
37
PD78CP18(A)
PROM Programming Mode Timing
A12 to A0 tSAC
Effective Address tHOOD tHCA
D7 to D0
Data Input tSIDC tHCID
Data Output
Data Input tSIDC MODE1 = VIL MODE0 = VIH tHCID
VIH MODE1 MODE0 VIL VPP VPP VDDP tSVPC tSMC
VDDP
VDDP + 1 VDDP tSVDC
VIH CE VIL tWL1 VIH VIL tDDOO tDOOD tWL2
OE
Cautions
1. Ensure that VDDP is applied before VPP, and cut after VPP. 2. Ensure that VPP does not exceed +13 V including overshoot.
PROM Read Mode Timing
A12 to A0
Effective Address
CE tDCOD
OE tDAOD Hi-Z D7 to D0 Data Output tDOOD tHCOD tHAOD Hi-Z
Cautions
1. If you wish to read within the tDAOD range, the OE input delay time from the fall of CE should be a maximum of tDAOD - tDOOD. 2. tHCOD is the time from the point at which OE or CE (whichever is first) reaches VIH.
38
PD78CP18(A)
7. CHARACTERISTIC CURVES (REFERENCE VALUE)
IDD1, IDD2 vs. VDD
30 (TA = 25 C, fXX = 15 MHz)
25 IDD1 (TYP.)
VDD Power Supply Current IDD1, IDD2 [mA]
20
15
10
5
IDD2 (TYP.)
0 0 4.5 5.0 Power Supply Voltage VDD [V] 5.5 6.0
IDD1, IDD2 vs. fXX
30 (TA = 25 C, VDD = 5 V)
VDD Power Supply Current IDD1, IDD2 [mA]
IDD1 (TYP.) 20
10
IDD2 (TYP.)
0 0 5 10 Oscillator Frequency fXX [MHz] 15
39
PD78CP18(A)
IOL vs. VOL
(TA = 25 C, VDD = 5 V) 2.5 TYP.
2.0 Output Current Low IOL [mA]
1.5
1.0
0.5
0 0 0.1 0.2 0.3 0.4 0.5
Output Voltage Low VOL [V]
IOH vs. VOH
(TA = 25 C, VDD = 5 V) -1.5
TYP.
Output Current High IOH [mA]
-1.0
-0.5
0 0 0.1 0.2 0.3 0.4 0.5
Power Supply Voltage - Output Voltage High VDD - VOH [V]
40
PD78CP18(A)
IDDDR vs. VDDDR
(TA = 25 C) 10
Data Retention Power Supply Current IDDDR [ A]
8
6
TYP. 4
2
0 0 2 3 4 5 6
Data Retention Power Supply Voltage VDDDR [V]
41
PD78CP18(A)
8. PACKAGE DRAWINGS
64 PIN PLASTIC QUIP
A
64
33
1
32 W X
P
S
M H I M J K N
C
P64GQ-100-36 NOTE Each lead centerline is located within 0.25 mm (0.010 inch) of its true position (T.P.) at maximum material condition. ITEM A C H I J K M N P S W X MILLIMETERS 41.5 16.5
- 0.50 +0.10 +0.3 -0.2
INCHES 1.634+0.012 -0.008 0.650 0.020 +0.004 -0.005 0.010 0.100 (T.P.) 0.050 (T.P.) 0.043+0.011 -0.006 0.010 +0.004 -0.003 0.157+0.013 -0.012 0.142 -0.005 0.950 -
+0.042 +0.042 +0.004
0.25 2.54 (T.P.) 1.27 (T.P.) 1.1 +0.25 -0.15
+0.10 0.25 -0.05 +0.3
4.0 - 3.6 -
+0.1
- 24.13 +1.05 - 19.05 +1.05
0.750 -
42
PD78CP18(A)
64 PIN PLASTIC QFP (14x20)
A B
51 52
33 32
detail of lead end
C
D
S
64 1
20 19
F
G
H
IM
J K
P
N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.40 0.10 0.20 1.0 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.12 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.071-0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.005 0.106 0.004 0.004 0.119 MAX.
+0.008
M
55
Q
43
PD78CP18(A)
5
9. RECOMMENDED SOLDERING CONDITIONS
The PD78CP18(A) should be soldered and mounted under the following recommended conditions. For details of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual (IEI-1207)". For soldering methods and conditions other than those recommended below, contact an NEC representative. Table 9-1. Surface Mount Type Soldering Conditions
PD78CP18GF(A)-3BE: 64-Pin Plastic QFP (14 x 20 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or higher), Count: Twice or less (1) (2) VPS Perform the second reflow at the time the device temperature is lowered to the room temperature from the heating by the first reflow. Do not wash the soldered portion with the flux following the first reflow. VP15-00-2 Recommended Condition Symbol IR35-00-2
Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or higher), Count: Twice or less (1) (2) Perform the second reflow at the time the device temperature is lowered to the room temperature from the heating by the first reflow. Do not wash the soldered portion with the flux following the first reflow.
Wave soldering
Solder bath temperature: 260 C max., Duration: 10 sec. max., Count: Once Preheating temperature: 120 C max. (package surface temperature) Pin temperature: 300 C max., Duration: 3 sec. max. (per device side row of pins)
WS60-00-1
Partial heating
----
Caution
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Table 9-2. Through-Hole Type Soldering Conditions
PD78CP18GQ(A)-36: 64-Pin Plastic QUIP
Soldering Method Wave soldering (pin part only) Partial heating Soldering Conditions Solder bath temperature: 260 C max., Duration: 10 sec. max. Pin temperature: 300 C max., Duration: 3 sec. max. (per pin)
Caution
Wave soldering is used on the pin only, and care must be taken to prevent solder from coming into direct contact with the body.
44
PD78CP18(A)
10. DIFFERENCES BETWEEN THE PD78CP18(A) AND PD78C18(A)
Part Number Item Internal ROM
PD78CP18(A)
32 K x 8 bits (PROM) 1 K x 8 bits PB7/OE PB6/CE STOP/VPP NMI/A9 PA7/A7 to PA0/A0 PF6/A14 to PF2/A10 PF0/A8 PD7/O7 to PD0/O0
PD78C18(A)
32 K x 8 bits (mask ROM) 1 K x 8 bits PB7 PB6 STOP NMI PA7 to PA0 PF6 to PF2 PF0 PD7 to PD0 * Operates as the PD78C17(A) (ROM-less mode) * External memory 16 K extension mode Input/output No
Internal RAM Pin connection
Mode set by MODE pins (when MODE0 is set to 1, and MODE1 to 0)
PROM programming mode
MODE0 pin input/output function Internal memory access area setting by MM register Port A to Port C
Input onlyNote Yes
Pull-up resistors not incorporated
Pull-up resistor incorporation selectable bit-wise by mask option
Note An emulation control signal is not output even if the MODE0 pin is pulled high.
45
PD78CP18(A)
5
APPENDIX DEVELOPMENT TOOLS
The following development tools are available to develop a system which uses the PD78CP18(A). Language Processor
87AD series relocatable assembler (RA87) This is a program which converts a program written in mnemonic to an object code for which microcomputer execution is possible. Moreover, it contains a function to automatically create a symbol/table, and optimize branch instructions.
Host Machine PC-9800 series
OS MS-DOSTM Ver. 2.11 to Ver. 5.00ANote
Supply Medium 3.5-inch 2HD
Ordering Code (Product Name)
S5A13RA87
5-inch 2HD
S5A10RA87
3.5-inch 2HC IBM PC/ATTM PC DOSTM (Ver. 3.1) 5-inch 2HC
S7B13RA87
S7B10RA87
PROM Write Tools
PG-1500 With a provided board and an optional programmer adapter connected, this PROM programmer can manipulate from a stand-alone or host machine to perform programming on a single-chip microcomputer which incorporates PROM. It is also capable of programming a typical PROM ranging from 256 K to 4 M bits. PA-78CP14GF/ GQ PA-78CP14GF PA-78CP14GQ PG-1500 controller PROM programmer adapter for the PD78CP18(A). Used by connecting to the PG-1500.
Hardware
For the PD78CP18GF(A)-3BE For the PD78CP18GQ(A)-36 Connects the PG-1500 to a host machine by using serial and parallel interface, to control the PG1500 on a host machine.
Host Machine Software PC-9800 series
OS MS-DOS Ver. 2.11 to Ver. 5.00ANote PC DOS (Ver. 3.1)
Supply Medium 3.5-inch 2HD
Ordering Code (Product Name)
S5A13PG1500
5-inch 2HD
S5A10PG1500
IBM PC/AT
5-inch 2HC
S7B10PG1500
Note Versions 5.00 and 5.00A have a task swap function, but this function cannot be used with this software. Remark The operations of the assembler and the PG-1500 controller are guaranteed only on the above host machines and operating systems.
46
PD78CP18(A)
Debugging Tools An in-circuit emulator (IE-78C11-M) is available as a program debugging tool for the PD78CP18(A). The following table shows its system configuration.
Hardware
IE-78C11-M
The IE-78C11-M is an in-circuit emulator which works with the 87AD series. It can be connected to a host machine to perform efficient debugging.
IE-78C11-M control program (IE controller)
Connects the IE-78C11-M to host machine by using the RS-233C, to control the IE-78C11-M on host machine.
Software
Host Machine PC-9800 series
OS MS-DOS Ver. 2.11 to Ver. 3.30D PC DOS (Ver. 3.1)
Supply Medium 3.5-inch 2HD
Ordering Code (Product Name)
S5A13IE78C11
5-inch 2HD
S5A10IE78C11
IBM PC/AT
5-inch 2HC
S7B10IE78C11
Remark
The operations of the IE controller are guaranteed only on the above host machines and operating systems.
47
PD78CP18(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards wiht semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
48
PD78CP18(A)
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11
QTOP is a trademark of NEC Corporation. MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.

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