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| a FEATURES Automatically Senses Sample Frequencies No Programming Required Attenuates Sample Clock Jitter 3.3 V-5 V Input and 3.3 V Core Supply Voltages Accepts 16-/18-/20-/24-Bit Data Up to 192 kHz Sample Rate Input/Output Sample Ratios from 7.75:1 to 1:8 Bypass Mode Multiple AD1895 TDM Daisy-Chain Mode 128 dB Signal-to-Noise and Dynamic Range (A-Weighted, 20 Hz-20 kHz BW) Up to -122 dB THD + N Linear Phase FIR Filter Hardware Controllable Soft Mute Supports 256 fS, 512 fS or 768 fS Master Mode Clock Flexible Three-Wire Serial Data Port with Left-Justified, I2S, Right-Justified (16-, 18-, 20-, 24-Bits), and TDM Serial Port Modes Master/Slave Input and Output Modes 28-Lead SSOP Plastic Package APPLICATIONS Home Theater Systems, Automotive Audio Systems, DVD, DVD-R, CD-R, Set-Top Boxes, Digital Audio Effects Processors 192 kHz Stereo Asynchronous Sample Rate Converter AD1895* FUNCTIONAL BLOCK DIAGRAM RESET VDD_IO VDD_CORE MUTE_I SDATA_I SCLK_I LRCLK_I SMODE_IN_0 SMODE_IN_1 SMODE_IN_2 BYPASS MUTE_O CLOCK DIVIDER ROM WLNGTH_O_0 WLNGTH_O_1 SERIAL INPUT DIGITAL PLL FIR FILTER SERIAL OUTPUT FIFO FSOUT FSIN AD1895 SDATA_O SCLK_O LRCLK_O TDM_IN SMODE_O_0 SMODE_O_1 MCLK_I MSMODE_0 MSMODE_2 MCLK_O MSMODE_1 a digital signal processor. The serial output data is dithered down to 20, 18 or 16 bits when 20-, 18- or 16-bit output data is selected. The AD1895 sample rate converts the data from the serial input port to the sample rate of the serial output port. The sample rate at the serial input port can be asynchronous with respect to the output sample rate of the output serial port. The master clock to the AD1895, MCLK, can be asynchronous to both the serial input and output ports. MCLK can either be generated off-chip or on-chip by the AD1895 master clock oscillator. Since MCLK can be asynchronous to the input or output serial ports, a crystal can be used to generate MCLK internally to reduce noise and EMI emissions on the board. When MCLK is synchronous to either the output or input serial port, the AD1895 can be configured in a master mode where MCLK is divided down and used to generate the left/right and bit clocks for the serial port that is synchronous to MCLK. The AD1895 supports master modes of 256 x fS, 512 x fS, and 768 x fS for both input and output serial ports. Conceptually, the AD1895 interpolates the serial input data by a rate of 220 and samples the interpolated data stream by the output sample rate. In practice, a 64-tap FIR filter with 220 polyphases, a FIFO, a digital servo loop that measures the time difference between input and output samples within 5 ps, and a digital circuit to track the sample rate ratio are used to perform the interpolation and output sampling. Refer to the Theory of Operation section. The digital servo loop and sample rate ratio circuit automatically track the input and output sample rates. (Continued on page 15) PRODUCT OVERVIEW The AD1895 is a 24-bit, high-performance, single-chip, secondgeneration asynchronous sample rate converter. Based upon Analog Devices, Inc. experience with its first asynchronous sample rate converter, the AD1890, the AD1895 offers improved performance and additional features. This improved performance includes a THD + N range of -115 dB to -122 dB depending on sample rate and input frequency, 128 dB (A-Weighted) dynamic range, 192 kHz sampling frequencies for both input and output sample rates, improved jitter rejection, and 1:8 upsampling and 7.75:1 downsampling ratios. Additional features include more serial formats, a bypass mode, and better interfacing to digital signal processors. The AD1895 has a 3-wire interface for the serial input and output ports that supports left-justified, I2S, and right-justified (16-, 18-, 20-, 24-bit) modes. Additionally, the serial output port supports TDM mode for daisy chaining multiple AD1895s to *Patents pending. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001 AD1895-SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages VDD_CORE VDD_IO Ambient Temperature Input Clock Input Signal Measurement Bandwidth Word Width Load Capacitance Input Voltage HI Input Voltage LO 3.3 V 5.0 V or 3.3 V 25C 30.0 MHz 1.000 kHz, 0 dBFS 20 to fS_OUT/2 Hz 24 Bits 50 pF 2.4 V 0.8 V Specifications subject to change without notice. DIGITAL PERFORMANCE (VDD_CORE = 3.3 V 5%, VDD_IO = 5.0 V 10%) Parameter Resolution Sample Rate @ MCLK_I = 30 MHz Sample Rate (@ Other Master Clocks)1 Sample Rate Ratios Upsampling Downsampling Dynamic Range2 (20 Hz to fS_OUT/2, 1 kHz, -60 dBFS Input) A-Weighted 44.1 kHz: 48 kHz 48 kHz: 44.1 kHz 48 kHz: 96 kHz 44.1 kHz: 192 kHz 96 kHz: 48 kHz 192 kHz: 32 kHz (20 Hz to fS_OUT/2, 1 kHz, -60 dBFS Input) No Filter 44.1 kHz: 48 kHz 48 kHz: 44.1 kHz 48 kHz: 96 kHz 44.1 kHz: 192 kHz 96 kHz: 48 kHz 192 kHz: 32 kHz Total Harmonic Distortion + Noise2 (20 Hz to fS_OUT/2, 1 kHz, 0 dBFS Input) No Filter Worst-Case (48 kHz:96 kHz)3 44.1 kHz: 48 kHz 48 kHz: 44.1 kHz 48 kHz: 96 kHz 44.1 kHz: 192 kHz 96 kHz: 48 kHz 192 kHz: 32 kHz Interchannel Gain Mismatch Interchannel Phase Deviation Mute Attenuation (24 Bits Word Width) Min Typ Max Unit Bits kHz kHz 24 6 215 MCLK_I/5000 fS_OUT MCLK_I/138 1:8 7.75:1 128 128 128 128 127 127 125 125 125 125 124 124 dB dB dB dB dB dB dB dB dB dB dB dB -115 -120 -119 -118 -120 -122 -122 0.0 0.0 -127 dB dB dB dB dB dB dB dB Degrees dB NOTES 1 Lower sampling rates than given by this formula are possible, but the jitter rejection will decrease. 2 Refer to the Typical Performance Characteristics section for DNR and THD+N numbers over wide range of Input and Output Sample Rates. 3 For any other ratio, minimum THD+N will be better than -115 dB. Please refer to detailed performance plots. Specifications subject to change without notice. -2- REV. A DIGITAL TIMING (-40 C < TA < +105 C, VDD_CORE = 3.3 V 5%, VDD_IO = 5.0 V 10%) AD1895 Max 30.02, 3 Unit ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter1 tMCLKI fMCLK tMPWH tMPWL MCLK_I Period MCLK_I Frequency MCLK_I Pulsewidth High MCLK_I Pulsewidth Low Min 33.3 8 12 8 8 8 8 3 3 3 Input Serial Port Timing tLRIS LRCLK_I Setup to SCLK_I tSIH SCLK_I Pulsewidth High tSIL SCLK_I Pulsewidth Low SDATA_I Setup to SCLK_I Rising Edge tDIS tDIH SDATA_I Hold from SCLK_I Rising Edge Output Serial Port Timing TDM_IN Setup to SCLK_O Falling Edge tTDMS tTDMH TDM_IN Hold from SCLK_O Falling Edge SDATA_O Propagation Delay from SCLK_O, LRCLK_O tDOPD SDATA_O Hold from SCLK_O tDOH tLROS LRCLK_O Setup to SCLK_O (TDM Mode Only) LRCLK_O Hold from SCLK_O (TDM Mode Only) tLROH tSOH SCLK_O Pulsewidth High tSOL SCLK_O Pulsewidth Low tRSTL RESET Pulsewidth LO 20 3 5 3 10 5 200 NOTES 1 Refer to Timing Diagram Section. 2 The maximum possible sample rate is: FSMAX = fMCLK /138. 3 fMCLK of up to 34 MHz is possible under the following conditions: 0C < TA < 70C, 45/55 or better MCLK_I duty cycle. Specifications subject to change without notice. TIMING DIAGRAMS MCLK I LRCLK_I t LRIS SCLK I t SIH RESET t DIS SDATA I t SIL t RSTL Figure 2. RESET Timing t DIH LRCLK O t MPWH tSOH SCLK O tDOPD SDATA O tSOL t MPWL tDOH tLROS Figure 3. MCLK_I Timing LRCLK O tLROH SCLK O tTDMS TDM IN tTDMH Figure 1. Input and Output Serial Port Timing (SCLK I/O, LRCLK I/O, SDATA I/O, TDM_IN) REV. A -3- AD1895-SPECIFICATIONS DIGITAL FILTERS (VDD_CORE = 3.3 V 5%, VDD_IO = 5.0 V 10%) Parameter Passband Passband Ripple Transition Band Stop Band Stop Band Attenuation Group Delay Specifications subject to change without notice. Min Typ Max 0.4535 fS_OUT 0.016 0.5465 fS_OUT Unit Hz dB Hz Hz dB 0.4535 fS_OUT 0.5465 fS_OUT -125 Refer to the Group Delay Equations Section DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V 5%, VDD_IO = 5.0 V 10%) Parameter Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 5 V) Input Leakage (IIL @ VIL = 0 V) Input Capacitance Output Voltage HI (VOH @ IOH = -4 mA) Output Voltage LO (VOL @ IOL = +4 mA) Output Source Current HI (IOH) Output Sink Current LO (IOL) Specifications subject to change without notice. Min 2.4 Typ Max 0.8 2 -2 10 0.5 -4 +4 Unit V A A pF V V mA mA VDD_CORE - 0.5 5 VDD_CORE - 0.4 0.2 POWER SUPPLIES Parameter Supply Voltage VDD_CORE VDD_IO* Active Supply Current I_ CORE_ACTIVE 48 kHz: 48 kHz 96 kHz: 96 kHz 192 kHz: 192 kHz I_IO_ACTIVE Power-Down Supply Current: (All Clocks Stopped) I_CORE_PWRDN I_IO_PWRDN Specifications subject to change without notice. Min 3.135 VDD_CORE Typ 3.3 3.3/5.0 20 26 43 2 0.5 10 Max 3.465 5.5 Unit V V mA mA mA mA mA A *For 3.3 V tolerant Inputs, VDD_IO supply should be set to 3.3 V; however, VDD_CORE supply voltage should not exceed VDD_IO. -4- REV. A AD1895 POWER SUPPLIES (VDD_CORE = 3.3 V 5%, VDD_IO = 5.0 V 10%) Parameter Total Active Power Dissipation 48 kHz: 48 kHz 96 kHz: 96 kHz 192 kHz: 192 kHz Total Power Down Dissipation: (RESET LO) Specifications subject to change without notice. Min Typ 65 85 132 2 Max Unit mW mW mW mW TEMPERATURE RANGE Parameter Specifications Guaranteed Functionality Guaranteed Storage Thermal Resistance, JA (Junction-to-Ambient) Specifications subject to change without notice. Min -40 -55 Typ 25 Max +105 +150 Unit C C C C/W 109 ABSOLUTE MAXIMUM RATINGS* Parameter Power Supplies VDD_CORE VDD_IO Digital Inputs Input Current Input Voltage Ambient Temperature (Operating) Min -0.3 -0.3 DGND - 0.3 -40 Max +3.6 +6.0 10 VDD_IO + 0.3 +105 Unit V V mA V C *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model AD1895YRS AD1895YRSRL Temperature Range -40C to +105C -40C to +105C Package Description 28-Lead SSOP 28-Lead SSOP Package Option RS-28 RS-28 on 13" Reel CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1895 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A -5- AD1895 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IN/OUT IN IN OUT IN IN/OUT IN/OUT IN IN IN IN IN IN IN IN OUT IN IN IN IN IN IN IN OUT IN/OUT IN/OUT IN IN IN Mnemonic NC MCLK_IN MCLK_OUT SDATA_I SCLK_I LRCLK_I VDD_IO DGND BYPASS SMODE_IN_0 SMODE_IN_1 SMODE_IN_2 RESET MUTE_IN MUTE_OUT WLNGTH_OUT_1 WLNGTH_OUT_0 SMODE_OUT_1 SMODE_OUT_0 TDM_IN DGND VDD_CORE SDATA_O LRCLK_O SCLK_O MMODE_0 MMODE_1 MMODE_2 Description No Connect Master Clock or Crystal Input Master Clock Output or Crystal Output Input Serial Data (at Input Sample Rate) Master/Slave Input Serial Bit Clock Master/Slave Input Left/Right Clock 3.3 V/5 V Input/Output Digital Supply Pin Digital Ground Pin ASRC Bypass Mode, Active High Input Port Serial Interface Mode Select Pin 0 Input Port Serial Interface Mode Select Pin 1 Input Port Serial Interface Mode Select Pin 2 Reset Pin, Active Low Mute Input Pin-- Active HI Normally Connected to MUTE_OUT Output Mute Control - Active HI Hardware Selectable Output Wordlength--Select Pin 1 Hardware Selectable Output Wordlength--Select Pin 0 Output Port Serial Interface Mode Select Pin 1 Output Port Serial Interface Mode Select Pin 0 Serial Data Input* (Only for Daisy-Chain Mode). Ground when not used. Digital Ground Pin 3.3 V Digital Supply Pin Output Serial Data (at Output Sample Rate) Master/Slave Output Left/Right Clock Master/Slave Output Serial Bit Clock Master/Slave Clock Ratio Mode Select Pin 0 Master/Slave Clock Ratio Mode Select Pin 1 Master/Slave Clock Ratio Mode Select Pin 2 *Also used to input matched-phase mode data. PIN CONFIGURATION NC 1 MCLK_IN 2 MCLK_OUT 3 SDATA_I 4 SCLK_I 5 LRCLK_I 6 VDD_IO 7 DGND 8 BYPASS 9 SMODE_IN_0 10 SMODE_IN_1 11 SMODE_IN_2 12 RESET 13 MUTE_IN 14 NC = NO CONNECT 28 MMODE_2 27 MMODE_1 26 MMODE_0 25 SCLK_O TOP VIEW 24 LRCLK_O (NOT TO SCALE) 23 SDATA_O 22 VDD_CORE 21 DGND 20 TDM_IN 19 SMODE_OUT_0 18 SMODE_OUT_1 17 WLNGTH_OUT_0 16 WLNGTH_OUT_1 15 MUTE_OUT AD1895 -6- REV. A Typical Performance Characteristics-AD1895 0 -20 -40 -60 -80 dBFS 0 -20 -40 -60 -80 dBFS -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 -100 -120 -140 -160 -180 -200 0 10 20 30 40 50 60 FREQUENCY - kHz 70 80 90 TPC 1. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz (Asynchronous) TPC 4. Wideband FFT Plot (16k Points) 44.1 kHz:192 kHz, 0 dBFS 1 kHz Tone 0 -20 -40 -60 -80 dBFS 0 -20 -40 -60 -80 dBFS -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 TPC 2. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz (Asynchronous) TPC 5. Wideband FFT Plot (16k Points) 48 kHz:44.1 kHz, 0 dBFS 1 kHz Tone 0 -20 -40 -60 -80 0 -20 -40 -60 -80 dBFS dBFS -100 -120 -140 -160 -180 -200 0 5 10 15 20 25 30 FREQUENCY - kHz 35 40 45 -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 TPC 3. Wideband FFT Plot (16k Points) 48 kHz:96 kHz, 0 dBFS 1 kHz Tone TPC 6. Wideband FFT Plot (16k Points) 96 kHz:48 kHz, 0 dBFS 1 kHz Tone REV. A -7- AD1895 0 -20 -40 -60 -80 -50 -60 -70 -80 -90 -100 -110 dBFS 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 dBFS -100 -120 -140 -160 -180 -200 -120 -130 -140 -150 -160 -170 -180 -190 -200 0 5 10 15 20 25 30 FREQUENCY - kHz 35 40 45 TPC 7. Wideband FFT Plot (16k Points) 192 kHz:48 kHz, 0 dBFS 1 kHz Tone TPC 10. Wideband FFT Plot (16k Points) 48 kHz:96 kHz, -60 dBFS 1 kHz Tone -50 -60 -70 -80 -90 -100 -110 -50 -60 -70 -80 -90 -100 -110 dBFS 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 dBFS -120 -130 -140 -150 -160 -170 -180 -190 -200 -120 -130 -140 -150 -160 -170 -180 -190 -200 0 10 20 30 40 50 60 FREQUENCY - kHz 70 80 90 TPC 8. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:48 kHz (Asynchronous) TPC 11. Wideband FFT Plot (16k Points) 44.1 kHz:192 kHz, -60 dBFS 1 kHz Tone -50 -60 -70 -80 -90 -100 -110 -50 -60 -70 -80 -90 -100 -110 dBFS dBFS -120 -130 -140 -150 -160 -170 -180 -190 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 -120 -130 -140 -150 -160 -170 -180 -190 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 TPC 9. Wideband FFT Plot (16k Points) 44.1 kHz:48 kHz, -60 dBFS 1 kHz Tone TPC 12. Wideband FFT Plot (16k Points) 48 kHz:44.1 kHz, -60 dBFS 1 kHz Tone -8- REV. A AD1895 -50 -60 -70 -80 -90 -100 -110 0 -20 -40 -60 -80 dBFS -120 -130 -140 -150 -160 -170 -180 -190 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 dBFS -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 TPC 13. Wideband FFT Plot (16k Points) 96 kHz:48 kHz, -60 dBFS 1 kHz Tone TPC 16. IMD, 10 kHz and 11 kHz 0 dBFS Tone 96 kHz:48 kHz -50 -60 -70 -80 -90 -100 -110 0 -20 -40 -60 -80 dBFS -120 -130 -140 -150 -160 -170 -180 -190 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 dBFS -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 TPC 14. Wideband FFT Plot (16k Points) 192 kHz:48 kHz, -60 dBFS 1 kHz Tone TPC 17. IMD, 10 kHz and 11 kHz 0 dBFS Tone 48 kHz:44.1 kHz 0 -20 -40 -60 -80 0 -20 -40 -60 -80 dBFS -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 dBFS -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 TPC 15. IMD, 10 kHz and 11 kHz 0 dBFS Tone 44:1 kHz:48 kHz TPC 18. Wideband FFT Plot (16k Points) 44.1 kHz:48 kHz, 0 dBFS 20 kHz Tone REV. A -9- AD1895 0 -20 -40 -60 -80 0 -20 -40 -60 -80 dBFS dBFS -100 -120 -140 -160 -180 -200 0 10 20 30 40 50 60 FREQUENCY - kHz 70 80 90 -100 -120 -140 -160 -180 -200 0 5 10 15 20 25 30 FREQUENCY - kHz 35 40 45 TPC 19. Wideband FFT Plot (16k Points) 192 kHz:192 kHz, 0 dBFS 80 kHz Tone TPC 22. Wideband FFT Plot (16k Points) 48 kHz:96 kHz, 0 dBFS 20 kHz Tone 0 -20 -40 -60 -80 0 -20 -40 -60 -80 dBFS -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 dBFS -100 -120 -140 -160 -180 -200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 22.5 TPC 20. Wideband FFT Plot (16k Points) 48 kHz:48 kHz, 0 dBFS 20 kHz Tone TPC 23. Wideband FFT Plot (16k Points) 96 kHz:48 kHz, 0 dBFS 20 kHz Tone 0 -20 -40 -60 -80 THD + N - dBFS 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY - kHz 17.5 20.0 -119 -121 -123 -125 -127 -129 -131 -133 -135 30000 dBFS -100 -120 -140 -160 -180 -200 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 TPC 21. Wideband FFT Plot (16k Points) 48 kHz:44:1 kHz, 0 dBFS 20 kHz Tone TPC 24. THD + N vs. Output Sample Rate, fS_IN = 192 kHz, 0 dBFS 1 kHz Tone -10- REV. A AD1895 -119 -121 -123 THD + N - dBFS THD + N - dBFS -119 -121 -123 -125 -127 -129 -131 -133 -135 30000 -125 -127 -129 -131 -133 -135 30000 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 TPC 25. THD + N vs. Output Sample Rate, fS_IN = 48 kHz, 0 dBFS 1 kHz Tone TPC 28. THD + N vs. Output Sample Rate, fS_IN = 96 kHz, 0 dBFS 1 kHz Tone -119 -121 -123 -119 -121 -123 THD + N - dBFS -125 -127 -129 -131 -133 -135 30000 DNR - dBFS 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 -125 -127 -129 -131 -133 -135 30000 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 TPC 26. THD + N vs. Output Sample Rate, fS_IN = 44.1 kHz, 0 dBFS 1 kHz Tone TPC 29. DNR vs. Output Sample Rate, fS_IN = 192 kHz, -60 dBFS 1 kHz Tone -119 -119 -121 -121 -123 -123 THD + N - dBFS DNR - dBFS -125 -127 -129 -131 -133 -135 30000 -125 -127 -129 -131 -133 -135 30000 55000 80000 105000 130000 155000 180000 OUTPUT SAMPLE RATE - Hz 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 TPC 27. THD + N vs. Output Sample Rate, fS_IN = 32 kHz, 0 dBFS 1 kHz Tone TPC 30. DNR vs. Output Sample Rate, fS_IN = 32 kHz, -60 dBFS 1 kHz Tone REV. A -11- AD1895 -119 -121 -123 DNR - dBFS -119 -121 -123 DNR - dBFS -125 -127 -129 -131 -133 -135 30000 -125 -127 -129 -131 -133 -135 30000 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 TPC 31. DNR vs. Output Sample Rate, fS_IN = 96 kHz, -60 dBFS 1 kHz Tone TPC 34. DNR vs. Output Sample Rate, fS_IN = 44.1 kHz, -60 dBFS 1 kHz Tone 5 -15 192 kHz:96 kHz -35 -55 -75 192 kHz:32 kHz -95 -115 -135 0 10000 20000 30000 40000 FREQUENCY - Hz 50000 60000 192 kHz:48 kHz 0.00 -0.01 -0.02 -0.03 -0.04 dBFS dBFS -0.05 -0.06 -0.07 -0.08 -0.09 -0.10 0 4000 8000 12000 16000 FREQUENCY - Hz 20000 24000 TPC 32. Digital Filter Frequency Response TPC 35. Passband Ripple, 192 kHz:48 kHz 5 -119 4 -121 -123 3 LINEARITY ERROR - dBr 55000 80000 105000 130000 155000 OUTPUT SAMPLE RATE - Hz 180000 2 1 0 -1 -2 -3 DNR - dBFS -125 -127 -129 -131 -133 -135 30000 -4 -5 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 TPC 33. DNR vs. Output Sample Rate, fS_IN = 48 kHz, -60 dBFS 1 kHz Tone TPC 36. Linearity Error, 48 kHz:48 kHz, 0 dBFS to -140 dBFS Input, 200 Hz Tone -12- REV. A AD1895 5 4 3 LINEARITY ERROR - dBr 5 4 3 LINEARITY ERROR - dBr 2 1 0 -1 -2 -3 -4 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 -5 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 2 1 0 -1 -2 -3 -4 -5 -140 TPC 37. Linearity Error, 48 kHz:44.1 kHz, 0 dBFS to -140 dBFS Input, 200 Hz Tone TPC 40. Linearity Error, 48 kHz:96 kHz, 0 dBFS to -140 dBFS Input, 200 Hz Tone 5 4 3 LINEARITY ERROR - dBr LINEARITY ERROR - dBr 5 4 3 2 1 0 -1 -2 -3 -4 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 -5 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 2 1 0 -1 -2 -3 -4 -5 -140 TPC 38. Linearity Error, 96 kHz:48 kHz, 0 dBFS to -140 dBFS Input, 200 Hz Tone TPC 41. Linearity Error, 44.1 kHz:192 kHz, 0 dBFS to -140 dBFS Input, 200 Hz Tone 5 4 3 LINEARITY ERROR - dBr LINEARITY ERROR - dBr 2 1 0 -1 -2 -3 -4 -5 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 5 4 3 2 1 0 -1 -2 -3 -4 -5 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 TPC 39. Linearity Error, 44.1 kHz:48 kHz, 0 dBFS to -140 dBFS Input, 200 Hz Tone TPC 42. Linearity Error, 192 kHz:44:1 kHz, 0 dBFS to -140 dBFS Input, 200 Hz Tone REV. A -13- AD1895 -110 -112 -114 -116 -118 -120 -122 dBr dBr -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 -124 -126 -128 -130 -132 -134 -136 -138 -140 -140 -110 -112 -114 -116 -118 -120 -122 -124 -126 -128 -130 -132 -134 -136 -138 -140 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 TPC 43. THD + N vs. Input Amplitude, 48 kHz:44.1 kHz, 1 kHz Tone TPC 46. THD + N vs. Input Amplitude, 48 kHz:96 kHz, 1 kHz Tone -110 -112 -114 -116 -118 -120 -122 dBr -126 -128 -130 -132 -134 -136 -138 -140 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 dBr -124 -110 -112 -114 -116 -118 -120 -122 -124 -126 -128 -130 -132 -134 -136 -138 -140 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 TPC 44. THD + N vs. Input Amplitude, 96 kHz:48 kHz, 1 kHz Tone TPC 47. THD + N vs. Input Amplitude, 44.1 kHz:192 kHz, 1 kHz Tone -110 -112 -114 -116 -118 -120 -122 dBr -110 -112 -114 -116 -118 -120 -122 dBr -124 -126 -128 -130 -132 -134 -136 -138 -140 -140 -124 -126 -128 -130 -132 -134 -136 -138 -140 -140 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 -120 -100 -80 -60 -40 INPUT LEVEL - dBFS -20 0 TPC 45. THD + N vs. Input Amplitude, 44.1 kHz:48 kHz, 1 kHz Tone TPC 48. THD + N vs. Input Amplitude, 192 kHz:48 kHz, 1 kHz Tone -14- REV. A AD1895 -110 -115 -120 -125 -130 -135 -140 -110 -115 -120 -125 -130 -135 -140 dBr 2.5 5.0 7.5 10.0 12.5 FREQUENCY - kHz 15.0 17.5 20.0 -145 -150 -155 -160 -165 -170 -175 -180 2.5 5.0 7.5 10.0 12.5 FREQUENCY - kHz 15.0 17.5 20.0 dBr -145 -150 -155 -160 -165 -170 -175 -180 TPC 49. THD + N vs. Frequency Input, 48 kHz:44.1 kHz, 0 dBFS TPC 51. THD + N vs. Frequency Input, 48 kHz:96 kHz, 0 dBFS -110 -115 -120 -125 -130 -135 -140 dBr -145 -150 -155 -160 -165 -170 -175 -180 2.5 5.0 7.5 10.0 12.5 FREQUENCY - kHz 15.0 17.5 20.0 dBr -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 -165 -170 -175 -180 2.5 5.0 7.5 10.0 12.5 FREQUENCY - kHz 15.0 17.5 20.0 TPC 50. THD + N vs. Frequency Input, 44.1 kHz:48 kHz, 00 dBFS TPC 52. THD + N vs. Frequency Input, 96 kHz:48 kHz, 0 dBFS (Continued from page 1) The digital servo loop measures the time difference between input and output sample rates within 5 ps. This is necessary in order to select the correct polyphase filter coefficient The digital servo loop has excellent jitter rejection for both input and output sample rates as well as the master clock. The jitter rejection begins at less than 1 Hz. This requires a long settling time whenever RESET is deasserted or when the input or output sample rate changes. To reduce the settling time, upon deassertion of RESET or a change in a sample rate, the digital servo loop enters the fast settling mode. When the digital servo loop has adequately settled in the fast mode, it switches into the normal or slow settling mode and continues to settle until the time difference measurement between input and output sample rates is within 5 ps. During fast mode, the MUTE_OUT signal is asserted high. Normally, the MUTE_OUT is connected to the MUTE_IN pin. The MUTE_IN signal is used to softly mute the AD1895 upon assertion and softly unmute the AD1895 when it is deasserted. The sample rate converter of the AD1895 can be bypassed altogether using the bypass mode. In bypass mode, the AD1895's serial input data is directly passed to the serial output port without any dithering. This is useful for passing through nonaudio data or when the input and output sample rates are synchronous to one another and the sample rate ratio is exactly 1 to 1. The AD1895 is a 3.3 V, 5 V input tolerant part and is available in a 28-lead SSOP SMD package. The AD1895 is 5 V inputtolerant only when the VDD_IO supply pin is supplied with 5 V. REV. A -15- AD1895 ASRC FUNCTIONAL OVERVIEW THEORY OF OPERATION Asynchronous sample rate conversion is converting data from one clock source at some sample rate to another clock source at the same or different sample rate. The simplest approach to asynchronous sample rate conversion is the use of a zero-order hold between two samplers shown in Figure 4. In an asynchronous system T2 is never equal to T1 nor is the ratio between T2 and T1 rational. As a result, samples at fS_OUT will be repeated or dropped producing an error in the resampling process. The frequency domain shows the wide side lobes that result from this error when the sampling of fS_OUT is convolved with the attenuated images from the sin(x)/x nature of the zero-order hold. The images at fS_IN, dc signal images, of the zero-order hold are infinitely attenuated. Since the ratio of T2 to T1 is an irrational number, the error resulting from the resampling at fS_OUT can never be eliminated. However, the error can be significantly reduced through interpolation of the input data at fS_IN. The AD1895 is conceptually interpolated by a factor of 220. IN ZERO-ORDER HOLD OUT between each fS_IN sample and convolving this interpolated signal with a digital low-pass filter to suppress the images. In the time domain it can be seen that fS_OUT selects the closest fS_IN x 220 sample from the zero-order hold as opposed to the nearest fS_IN sample in the case of no interpolation. This significantly reduces the resampling error. IN INTERPOLATE BY N fS_IN LOW-PASS FILTER ZERO-ORDER HOLD OUT fS_OUT TIME DOMAIN OF fS_IN SAMPLES TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER fS_IN = 1/T1 ORIGINAL SIGNAL fS_OUT = 1/T2 TIME DOMAIN OF fS_OUT RESAMPLING SAMPLED AT fS_IN TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT SIN(X)/X OF ZERO-ORDER HOLD SPECTRUM OF ZERO-ORDER HOLD OUTPUT Figure 5. Time Domain of the Interpolation and Resampling SPECTRUM OF fS_OUT SAMPLING 2 fS_OUT fS_OUT FREQUENCY RESPONSE OF fS_OUT CONVOLVED WITH ZERO-ORDER HOLD SPECTRUM Figure 4. Zero-Order Hold Being Used by fS_OUT to Resample Data from fS_IN THE CONCEPTUAL HIGH INTERPOLATION MODEL In the frequency domain shown in Figure 6 the interpolation expands the frequency axis of the zero-order hold. The images from the interpolation can be sufficiently attenuated by a good low-pass filter. The images from the zero-order hold are now pushed by a factor of 220 closer to the infinite attenuation point of the zero-order hold, which is fS_IN x 220. The images at the zero-order hold are the determining factor for the fidelity of the output at fS_OUT. The worst-case images can be computed from the zero-order hold frequency response, maximum image = sin ( x F/fS_INTERP)/( x F/fS_INTERP). F is the frequency of the worst-case image which would be 220 x fS_IN fS_IN/2 , and fS_INTERP is fS_IN x 220. The following worst-case images would appear for fS_IN = 192 kHz: Image at fS_INTERP - 96 kHz = -125.1 dB Image at fS_INTERP + 96 kHz = -125.1 dB Interpolation of the input data by a factor of 220 involves placing (220 -1) samples between each fS_IN sample. Figure 5 shows both the time domain and the frequency domain of interpolation by a factor of 220. Conceptually, interpolation by 220 would involve the steps of zero-stuffing (220 -1) number of samples -16- REV. A AD1895 IN INTERPOLATE BY N fS_IN LOW-PASS FILTER ZERO-ORDER HOLD OUT fS_OUT FREQUENCY DOMAIN OF SAMPLES AT fS_IN fS_IN rate, fS_IN, the ROM starting address, input data and the length of the convolution must be scaled. As the input sample rate rises over the output sample rate, the antialiasing filter's cutoff frequency has to be lowered because the Nyquist frequency of the output samples is less than the Nyquist frequency of the input samples. To move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (fS_IN/fS_OUT). This technique is supported by the Fourier transform property that if f(t) is F(), then f(k x t) is F(/k). Thus, the range of decimation is simply limited by the size of the RAM. THE SAMPLE RATE CONVERTER ARCHITECTURE FREQUENCY DOMAIN OF THE INTERPOLATION 220 fS_IN SIN(X)/X OF ZERO-ORDER HOLD FREQUENCY DOMAIN OF fS_OUT RESAMPLING 220 fS_IN FREQUENCY DOMAIN AFTER RESAMPLING 220 fS_IN Figure 6. Frequency Domain of the Interpolation and Resampling HARDWARE MODEL The architecture of the sample rate converter is shown in Figure 7. The sample rate converter's FIFO block adjusts the left and right input samples and stores them for the FIR filter's convolution cycle. The fS_IN counter provides the write address to the FIFO block and the ramp input to the digital servo loop. The ROM stores the coefficients for the FIR filter convolution and performs a high-order interpolation between the stored coefficients. The sample rate ratio block measures the sample rate for dynamically altering the ROM coefficients and scaling of the FIR filter length as well as the input data. The digital servo loop automatically tracks the fS_IN and fS_OUT sample rates and provides the RAM and ROM start addresses for the start of the FIR filter convolution. RIGHT DATA IN LEFT DATA IN ROM A FIFO ROM B ROM C ROM D fS_IN COUNTER DIGITAL SERVO LOOP SAMPLE RATE RATIO FIR FILTER fS_IN fS_OUT SAMPLE RATE RATIO EXTERNAL RATIO L/R DATA OUT HIGH ORDER INTERP The output rate of the low-pass filter of Figure 5 would be the interpolation rate, 220 x 192000 kHz = 201.3 GHz. Sampling at a rate of 201.3 GHz is clearly impractical, not to mention the number of taps required to calculate each interpolated sample. However, since interpolation by 220 involves zero-stuffing 220-1 samples between each fS_IN sample, most of the multiplies in the low-pass FIR filter are by zero. A further reduction can be realized by the fact that since only one interpolated sample is taken at the output at the fS_OUT rate, only one convolution needs to be performed per fS_OUT period instead of 220 convolutions. A 64-tap FIR filter for each fS_OUT sample is sufficient to suppress the images caused by the interpolation. The difficulty with the above approach is that the correct interpolated sample needs to be selected upon the arrival of fS_OUT. Since there are 220 possible convolutions per fS_OUT period, the arrival of the fS_OUT clock must be measured with an accuracy of 1/201.3 GHz = 4.96 ps. Measuring the fS_OUT period with a clock of 201.3 GHz frequency is clearly impossible; instead, several coarse measurements of the fS_OUT clock period are made and averaged over time. Another difficulty with the above approach is the number of coefficients required. Since there are 220 possible convolutions with a 64-tap FIR filter, there need to be 220 polyphase coefficients for each tap, which requires a total of 226 coefficients. To reduce the number of coefficients in ROM, the AD1895 stores a small subset of coefficients and performs a high-order interpolation between the stored coefficients. So far the above approach works for the case of fS_OUT > fS_IN. However, in the case when the output sample rate, fS_OUT, is less than the input sample Figure 7. Architecture of the Sample Rate Converter The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the RAM. The input data is scaled by the sample rate ratio because as the FIR filter length of the convolution increases, so does the amplitude of the convolution output. To keep the output of the FIR filter from saturating, the input data is scaled down by multiplying it by (fS_OUT/fS_IN) when fS_OUT < fS_IN. The FIFO also scales the input data for muting and unmuting of the AD1895. The RAM in the FIFO is 512 words deep for both left and right channels. A small offset of 16 is added to the write address provided by the fS_IN counter to prevent the RAM read pointer from ever overlapping the write address. The maximum decimation rate can be calculated from the RAM word depth as (512-16)/64 taps = 7.75 and a small offset. REV. A -17- AD1895 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 -210 -220 0.01 SLOW MODE FAST MODE 0.1 1 10 100 1e3 1e4 1e5 FREQUENCY - Hz Figure 8. Frequency Response of the Digital Servo Loop. fS_IN is the X-Axis, fS_OUT = 192 kHz, Master Clock Frequency Is 30 MHz The digital servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution. The RAM pointer is the integer output of the ramp filter while the ROM is the fractional part. The digital servo loop must be able to provide excellent rejection of jitter on the fS_IN and fS_OUT clocks as well as measure the arrival of the fS_OUT clock within 4.97 ps. The digital servo loop will also divide the fractional part of the ramp output by the ratio of fS_IN/fS_OUT for the case when fS_IN > fS_OUT, to dynamically alter the ROM coefficients. The digital servo loop is implemented with a multirate filter. To settle the digital servo loop filter quicker upon start-up or a change in the sample rate, a "fast mode" was added to the filter. When the digital servo loop starts up or the sample rate is changed, the digital servo loop kicks into "fast mode" to adjust and settle on the new sample rate. Upon sensing the digital servo loop settling down to some reasonable value, the digital servo loop will kick into "normal" or "slow mode." During "fast mode" the MUTE_OUT signal of the sample rate converter is asserted to let the user know that they should mute the sample rate converter to avoid any clicks or pops. The frequency response of the digital servo loop for "fast mode" and "slow mode" are shown in Figure 8. The FIR filter is a 64-tap filter in the case of fS_OUT fS_IN and is (fS_IN/fS_OUT) x 64 taps for the case when fS_IN > fS_OUT. The FIR filter performs its convolution by loading in the starting address of the RAM address pointer and the ROM address pointer from the digital servo loop at the start of the fS_OUT period. The FIR filter then steps through the RAM by decrementing its address by 1 for each tap, and the ROM pointer increments its address by the (fS_OUT/fS_IN) x 220 ratio for fS_IN > fS_OUT or 220 for fS_OUT fS_IN. Once the ROM address rolls over, the convolution is completed. The convolution is performed for both the left and right channels, and the multiply accumulate circuit used for the convolution is shared between the channels. The fS_IN/fS_OUT sample rate ratio circuit is used to dynamically alter the coefficients in the ROM for the case when fS_IN > fS_OUT. The ratio is calculated by comparing the output of an fS_OUT counter to the output of an fS_IN counter. If fS_OUT > fS_IN, the ratio is held at one. If fS_IN > fS_OUT, the sample rate ratio is updated if it is different by more than two fS_OUT periods from the previous fS_OUT to fS_IN comparison. This is done to provide some hysteresis to prevent the filter length from oscillating and causing distortion. -18- REV. A AD1895 OPERATING FEATURES RESET and Power Down When RESET is asserted low, the AD1895 will turn off the master clock input to the AD1895, MCLK_I, initialize all of its internal registers to their default values, and three-state all of the I/O pins. While RESET is active low, the AD1895 is consuming minimum power. For the lowest possible power consumption while RESET is active low, all of the input pins to the AD1895 should be static. When RESET is deasserted, the AD1895 begins its initialization routine where all locations in the FIFO are initialized to zero, MUTE_OUT is asserted high, and any I/O pins configured as outputs are enabled. The mute control counter, which controls the soft mute attenuation of the input samples, is initialized to maximum attenuation, -127 dB (see Mute Control section). When asserting RESET and deasserting RESET, the RESET should be held low for a minimum of 5 MCLK_I cycles. During power-up the RESET should be held low until the power supplies have stabilized. Power Supply and Voltage Reference Upon RESET, or a change in the sample rate between LRCLK_I and LRCLK_O, the MUTE_OUT pin will be asserted high. The MUTE_OUT pin will remain asserted high until the digital servo loop's internal fast settling mode has completed. When the digital servo loop has switched to slow settling mode, the MUTE_OUT pin will deassert. While MUTE_OUT is asserted, the MUTE_IN pin should be asserted as well to prevent any major distortion in the audio output samples. Master Clock The AD1895 is designed for three-volt operation with five-volt input tolerance on the input pins. VDD_CORE is the three-volt supply that is used to power the core logic of the AD1895 and to drive the output pins. VDD_IO is used to set the input voltage tolerance of the input pins. In order for the input pins to be five-volt input tolerant, VDD_IO must be connected to a fivevolt supply. If the input pins do not have to be five-volt input tolerant, then VDD_IO can be connected to VDD_CORE. VDD_IO should never be less than VDD_CORE. VDD_CORE and VDD_IO should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize power supply and ground bounce caused by inductance in the traces. A bulk aluminium electrolytic capacitor of 47 F should also be provided on the same PC board as the AD1895. Digital Filter Group Delay A digital clock connected to the MCLK_I pin or a fundamental or third overtone crystal connected between MCLK_I and MCLK_O can be used to generate the master clock, MCLK_I. The MCLK_I pin can be five-volt input-tolerant just like any of the other AD1895 input pins. A fundamental mode crystal can be inserted between MCLK_I and MCLK_O for master clock frequency generation up to 27 MHz. For master clock frequency generation with a crystal beyond 27 MHz it is recommended that the user use a third overtone crystal and to add an LC filter at the output of MCLK_O to filter out the fundamental, do not notch filter the fundamental. Please refer to your quartz crystal supplier for values for external capacitors and inductor components. AD1895 MCLK_I MCLK_O R = 45 C1 C2 Figure 9a. Fundamental-Mode Circuit Configuration The filter group delay is given by the equation: GD = GD = 16 fS _ IN 16 fS _ IN + 32 fS _ IN seconds for fS _ OUT > fS _ IN AD1895 MCLK_I MCLK_O R = 45 32 fS _ IN + seconds for fS _ OUT < fS _ IN x fS _ IN fS _ OUT 1nF C1 C2 L1 Mute Control When the MUTE_IN pin is asserted high, the MUTE_IN control will perform a soft mute by linearly decreasing the input data to the AD1895 FIFO to almost zero, -127 dB attenuation. When MUTE_IN is deasserted low, the MUTE_IN control will linearly decrease the attenuation of the input data to 0 dB. A 12-bit counter, clocked by LRCLK_I is used to control the mute attenuation. Therefore, the time it will take from the assertion of MUTE_IN to -127 dB full mute attenuation is 4096/LRCLK_I seconds. Likewise, the time it will take to reach 0 dB mute attenuation from the deassertion of MUTE_IN is 4096/ LRCLK_I seconds. Figure 9b. Third-Overtone Circuit Configuration There are, of course, maximum and minimum operating frequencies for the AD1895 master clock. The maximum master clock frequency at which the AD1895 is guaranteed to operate is 30 MHz. 30 MHz is more than sufficient to sample rate convert sampling frequencies of 192 kHz + 12%. The minimum required frequency for the master clock generation for the AD1895 depends upon the input and output sample rates. The master clock has to be at least 138 times greater than the maximum input or output sample rate. REV. A -19- AD1895 Serial Data Ports--Data Format The serial data input port mode is set by the logic levels on the SMODE_IN_0/1/2 pins. The serial data input port modes available are Left Justified, I2S and Right Justified (RJ), 16, 18, 20, or 24 bits as defined in Table I. Table I. Serial Data Input Port Mode 24 bits, dither is added to the truncated bits. The Right Justified serial data out mode assumes 64 SCLK_O cycles per frame, divided evenly for left and right. Table II. Serial Data Output Port Mode SMODE_OUT_[0:2] 1 0 0 1 0 1 Interface Format Left Justified (LJ) I2 S TDM Mode Right Justified (RJ) SMODE_IN_[0:2] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Interface Format Left Justified I2 S Undefined Undefined Right Justified, 16 Bits Right Justified, 18 Bits Right Justified, 20 Bits Right Justified, 24 Bits 0 0 1 1 Table III. Word Width WLNGTH_OUT_[0:1] 1 0 0 1 1 0 0 1 0 1 Word Width 24 Bits 20 Bits 18 Bits 16 Bits The serial data output port mode is set by the logic levels on the SMODE_OUT_0/1 and WLNGTH_OUT_0/1 pins. The serial mode can be changed to Left Justified, I2S, Right Justified or TDM as defined in the following table. The output word width can be set by using the WLNGTH_OUT_0/1 pins as shown in the Word Width table. When the output word width is less than The following timing diagrams show the serial mode formats. LRCLK SCLK SDATA MSB MSB LEFT CHANNEL RIGHT CHANNEL LSB MSB LSB LEFT JUSTIFIED MODE - 16 TO 24 BITS PER CHANNEL LRCLK LEFT CHANNEL SCLK MSB LSB I2S MODE - 16 TO 24 BITS PER CHANNEL MSB MSB LSB RIGHT CHANNEL SDATA LRCLK SCLK SDATA LEFT CHANNEL RIGHT CHANNEL MSB LSB MSB LSB RIGHT JUSTIFIED MODE - SELECT NUMBER OF BITS PER CHANNEL LRCLK SCLK SDATA MSB LSB TDM MODE - 16 TO 24 BITS PER CHANNEL 1/fs NOTES: 1. LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (fs) 2. SCLK FREQUENCY IS NORMALLY 64 LRCLK EXCEPT FOR TDM MODE WHICH IS N 64 fs, WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN, IN MASTER MODE N = 4 MSB LSB Figure 10. Input/Output Serial Data Formats -20- REV. A AD1895 TDM MODE APPLICATION In TDM mode, several AD1895s can be daisy-chained together and connected to the serial input port of a SHARC(R) DSP. The AD1895 contains a 64-bit parallel load shift register. When the LRCLK_O pulse arrives, each AD1895 parallel loads its left and right data into the 64-bit shift register. The input to the shift register is connected to TDM_IN while the output is connected to SDATA_O. By connecting the SDATA_O to the TDM_IN of the next AD1895, a large shift register is created which is clocked by SCLK_O. The number of AD1895s that can be daisy-chained together is limited by the maximum frequency of SCLK_O, which is about 25 MHz. For example, if the output sample rate, fS, is 48 kHz, up to eight AD1895s could be connected since 512 x fS is less than 25 MHz. In Master/TDM Mode, the number of AD1895s that can be daisy-chained is fixed to four. LRCLK SCLK AD1895 TDM_IN SDATA_O LRCLK_O SCLK_O AD1895 TDM_IN SDATA_O LRCLK_O SCLK_O AD1895 TDM_IN SDATA_O LRCLK_O SCLK_O DR0 RFS0 SHARC DSP RCLK0 SLAVE-1 M2 M1 M0 M2 SLAVE-2 M1 M0 M2 SLAVE-n M1 M0 0 0 0 0 0 0 0 0 0 STANDARD MODE Figure 11. Daisy-Chain Configuration for TDM Mode (All AD1895s Being Clock-Slaves) AD1895 TDM_IN SDATA_O LRCLK_O SCLK_O AD1895 TDM_IN SDATA_O LRCLK_O SCLK_O AD1895 TDM_IN SDATA_O LRCLK_O SCLK_O DR0 RFS0 SHARC DSP RCLK0 CLOCK-MASTER M2 M1 M0 M2 SLAVE-1 M1 M0 M2 SLAVE-n M1 M0 0 1 1 0 0 0 0 0 0 STANDARD MODE Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1895 Being Clock-Master) SHARC is a registered trademark of Analog Devices, Inc. REV. A -21- AD1895 Serial Data Port Master Clock Modes Bypass Mode Either of the AD1895 serial ports can be configured as a master serial data port. However, only one serial port can be a master while the other has to be a slave. In master mode, the AD1895 requires a 256 x fS, 512 fS or 768 x fS master clock (MCLK_I). For a maximum master clock frequency of 30 MHz, the maximum sample rate is limited to 96 kHz. In slave mode, sample rates up to 192 kHz can be handled. When either of the serial ports is operated in master mode, the master clock is divided down to derive the associated left/ right subframe clock (LRCLK) and serial bit clock (SCLK). The master clock frequency can be selected for 256, 512, or 768 times the input or output sample rate. Both the input and output serial ports will support master mode LRCLK and SCLK generation for all serial modes, Left Justified, I2S, Right Justified, and TDM for the output serial port. Table IV. Serial Data Port Clock Modes When the BYPASS pin is asserted high, the input data bypasses the sample rate converter and is sent directly to the serial output port. Dithering of the output data when the word length is set to less than 24 bits is disabled. This mode is ideal when the input and output sample rates are the same and LRCLK_I and LRCLK_O are synchronous with respect to each other. This mode can also be used for passing through non-AUDIO data since no processing is performed on the input data in this mode. MMODE_0/1/2 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Interface Format Both Serial Ports are in Slave Mode Output Serial Port is Master with 768 x fS_OUT Output Serial Port is Master with 512 x fS_OUT Output Serial Port is Master with 256 x fS_OUT Undefined Input Serial Port is Master with 768 x fS_IN Input Serial Port is Master with 512 x fS_IN Input Serial Port is Master with 256 x fS_IN -22- REV. A AD1895 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.413 (10.50) 0.402 (10.20) 0.390 (9.90) 28 15 PIN 1 1 14 0.220 (5.60) 0.209 (5.30) 0.197 (5.00) 0.323 (8.20) 0.307 (7.80) 0.291 (7.40) 0.073 (1.85) 0.069 (1.75) 0.065 (1.65) 0.079 (2.00) MAX 0.002 (0.05) MIN 0.026 (0.65) BSC 0.015 (0.38) SEATING 0.009 (0.22) PLANE 0.010 (0.25) 0.004 (0.09) 8 4 0 0.037 (0.95) 0.030 (0.75) 0.022 (0.55) AD1895-Revision History Location Page Data Sheet changed from REV. 0 to REV. A. Changes to Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 REV. A -23- -24- C00758-1.5-6/01(A) PRINTED IN U.S.A. |
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