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CA3240, CA3240A
Data Sheet August 2001 File Number 1050.5
Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output
The CA3240A and CA3240 are dual versions of the popular CA3140 series integrated circuit operational amplifiers. They combine the advantages of MOS and bipolar transistors on the same monolithic chip. The gate-protected MOSFET (PMOS) input transistors provide high input impedance and a wide common-mode input voltage range (typically to 0.5V below the negative supply rail). The bipolar output transistors allow a wide output voltage swing and provide a high output current capability. The CA3240A and CA3240 are compatible with the industry standard 1458 operational amplifiers in similar packages.The offset null feature is available only when these types are supplied in the 14 lead PDIP package (E1 suffix).
Features
* Dual Version of CA3140 * Internally Compensated * MOSFET Input Stage - Very High Input Impedance (ZIN) 1.5T (Typ) - Very Low Input Current (II) 10pA (Typ) at 15V - Wide Common-Mode Input Voltage Range (VICR ): Can Be Swung 0.5V Below Negative Supply Voltage Rail * Directly Replaces Industry Type 741 in Most Applications
Applications
* Ground Referenced Single Amplifiers in Automobile and Portable Instrumentation * Sample and Hold Amplifiers * Long Duration Timers/Multivibrators (MicrosecondsMinutes-Hours) * Photocurrent Instrumentation * Intrusion Alarm System * Comparators * Instrumentation Amplifiers * Active Filters * Function Generators * Power Supplies
Ordering Information
PART NUMBER CA3240AE CA3240AE1 CA3240E TEMP. RANGE ( oC) -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 14 Ld PDIP 8 Ld PDIP PKG. NO. E8.3 E14.3 E8.3
Functional Diagram
2mA 4mA V+
Pinouts
CA3240, CA3240A (PDIP) TOP VIEW
BIAS CIRCUIT CURRENT SOURCES AND REGULATOR 200A + INPUT A 1.6mA 200A 2A 2mA OUTPUT
OUTPUT (A) INV. INPUT (A) NON-INV. INPUT (A) V-
1 2 3 4
8 V+ 7 OUTPUT INV. 6 INPUT (B) 5 NON-INV. INPUT (B)
10
A 10,000
A1
-
C1 12pF V-
CA3240A (PDIP) TOP VIEW
INV. INPUT (A) NON-INV. INPUT (A) OFFSET NULL (A) VOFFSET NULL (B) NON - INV. INPUT (B) INV. INPUT (B) OFFSET 14 NULL (A) 13 V+ 12 OUTPUT (A) 11 NC 10 OUTPUT (B) 9 V+ 8 OFFSET NULL (B)
1 2 3 4 5 6 7
OFFSET NULL
NOTE: Only available with 14 lead DIP (E1 Suffix).
Pins 9 and 13 internally connected through approximately 3.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright (c) Intersil Americas Inc. 2001
CA3240, CA3240A
Absolute Maximum Ratings
Supply Voltage (Between V+ and V-). . . . . . . . . . . . . . . . . . . . . 36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (oC/W)
8 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . 100 14 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Voltage Range . . . . . . . . . . . . . . . . . . . . . 4V to 36V or 2V to 18V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within maximum rating. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Large-Signal Voltage Gain (See Figures 13, 28) (Note 3) Common Mode Rejection Ratio (See Figure 18)
For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified CA3240 SYMBOL VIO IIO II AOL CMRR MIN 20 86 70 VICR PSRR (VIO/V) VOM+ VOMVOMI+ PD -15 76 12 -14 0.4 TYP 5 0.5 10 100 100 32 90 -15.5 to +12.5 100 80 13 -14.4 0.13 8 240 MAX 15 30 50 320 11 150 12 360 MIN 20 86 70 -15 76 12 -14 0.4 CA3240A TYP 2 0.5 10 100 100 32 90 -15.5 to +12.5 100 80 13 -14.4 0.13 8 240 MAX 5 20 40 320 12 150 12 360 UNITS mV pA pA kV/V dB V/V dB V V/V dB V V V mA mW
Common Mode Input Voltage Range (See Figure 25) Power Supply Rejection Ratio (See Figure 20) Maximum Output Voltage (Note 4) (See Figures 24, 25) Maximum Output Voltage (Note 5) Total Supply Current (See Figure 16) For Both Amps Total Device Dissipation NOTES:
3. At VO = 26VP-P, +12V, -14V and RL = 2k. 4. At RL = 2k. 5. At V+ = 5V, V- = GND, ISINK = 200A.
Electrical Specifications
PARAMETER
For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified TYPICAL VALUES SYMBOL TEST CONDITIONS Typical Value of Resistor Between Terminals 4 and 3(5) or Between 4 and 14(8) to Adjust Maximum VIO RI CI RO eN BW = 140kHz, RS = 1M CA3240A 18 1.5 4 60 48 CA3240 4.7 1.5 4 60 48 UNITS k T pF V
Input Offset Voltage Adjustment Resistor (E1 Package Only) Input Resistance Input Capacitance Output Resistance Equivalent Wideband Input Noise Voltage (See Figure 2)
2
CA3240, CA3240A
Electrical Specifications
PARAMETER Equivalent Input Noise Voltage (See Figure 19) Short-Circuit Current to Opposite Supply For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified (Continued) TYPICAL VALUES SYMBOL eN IOM + IOMGain Bandwidth Product (See Figures 14, 28) Slew Rate (See Figure 15) Transient Response (See Figure 1) fT SR tr OS Settling Time at 10VP-P (See Figure 26) Crosstalk (See Figure 23) tS RL = 2k, C L = 100pF RL = 2k, C L = 100pF AV = +1, RL = 2k, CL = 100pF, Voltage Follower f = 1kHz Rise Time Overshoot To 1mV To 10mV TEST CONDITIONS f = 1kHz, RS = 100 f = 10kHz, RS = 100 Source Sink CA3240A 40 12 40 11 4.5 9 0.08 10 4.5 1.4 120 CA3240 40 12 40 11 4.5 9 0.08 10 4.5 1.4 120 UNITS nV/Hz nV/Hz mA mA MHz V/s s % s s dB
Electrical Specifications
For Equipment Design, at VSUPPLY = 15V, TA = -40 to 85oC, Unless Otherwise Specified TYPICAL VALUES
PARAMETER Input Offset Voltage Input Offset Current (Note 8) Input Current (Note 8) Large Signal Voltage Gain (See Figures 13, 28), (Note 6)
SYMBOL |VIO| |IIO| II AOL CMRR
CA3240A 3 32 640 63 96
CA3240 10 32 640 63 96 32 90 -15 to +12.3 150 76 12.4 -14.2 8.4 252 15
UNITS mV pA pA kV/V dB V/V dB V V/V dB V V mA mW V/oC
Common Mode Rejection Ratio (See Figure 18)
32 90
Common Mode Input Voltage Range (See Figure 25) Power Supply Rejection Ratio (See Figure 20)
VICR PSRR (VIO/V) VOM+ VOM I+ PD VIO/T
-15 to +12.3 150 76 12.4 -14.2 8.4 252 15
Maximum Output Voltage (Note 7) (See Figures 24, 25)
Supply Current (See Figure 16) Total For Both Amps Total Device Dissipation Temperature Coefficient of Input Offset Voltage NOTES: 6. At VO = 26VP-P, +12V, -14V and RL = 2k. 7. At RL = 2k. 8. At TA = 85oC.
Electrical Specifications
For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified TYPICAL VALUES
PARAMETER Input Offset Voltage Input Offset Current Input Current Input Resistance Large Signal Voltage Gain (See Figures 13, 28)
SYMBOL |VIO| |IIO| II RIN AOL
CA3240A 2 0.1 2 1 100 100
CA3240 5 0.1 2 1 100 100
UNITS mV pA pA T kV/V dB
3
CA3240, CA3240A
Electrical Specifications
For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified (Continued) TYPICAL VALUES PARAMETER Common-Mode Rejection Ratio SYMBOL CMRR CA3240A 32 90 Common-Mode Input Voltage Range (See Figure 25) VICR PSRR -0.5 2.6 Power Supply Rejection Ratio 31.6 90 Maximum Output Voltage (See Figures 24, 25) VOM+ VOM Maximum Output Current Source Sink Slew Rate (See Figure 15) Gain Bandwidth Product (See Figure 14) Supply Current (See Figure 16) Device Dissipation IOM+ IOMSR fT I+ PD 3 0.3 20 1 7 4.5 4 20 CA3240 32 90 -0.5 2.6 31.6 90 3 0.3 20 1 7 4.5 4 20 UNITS V/V dB V V V/V dB V V mA mA V/s MHz mA mW
Test Circuits and Waveforms
50mV/Div., 200ns/Div. Top Trace: Input, Bottom Trace: Output FIGURE 1A. SMALL SIGNAL RESPONSE
+15V 10k + CA3240 0.1F
5V/Div., 1s/Div. Top Trace: Input, Bottom Trace: Output FIGURE 1B. LARGE SIGNAL RESPONSE
SIMULATED LOAD 2k
0.1F
100pF
-15V 2k 0.05F BW (-3dB) = 4.5MHz SR = 9V/s
FIGURE 1C. TEST CIRCUIT FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS
4
CA3240, CA3240A Test Circuits and Waveforms
(Continued)
+15V 0.01F RS + 1M CA3240 NOISE VOLTAGE OUTPUT 30.1k 0.01F
-
-15V
BW (-3dB) = 140kHz TOTAL NOISE VOLTAGE (REFERRED TO INPUT) = 48V (TYP)
1k
FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT
Schematic Diagram (One Amplifier of Two)
BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK V+ D1 Q1 Q2 Q3 D7 R9 50 R10 Q19 1K Q4 R11 20 Q17 R8 1K Q18 D2 D3 D4 D5 INVERTING INPUT OUTPUT R 12 12K Q20 D8 R14 20K R13 15K
Q6
Q5
Q7 R1 8K
Q21
Q8
-
Q9 Q10 R3 500
NON-INVERTING INPUT + R2 500 Q11 R4 500
C1 12pF
Q13 Q12 R5 500
Q14
Q15
Q16 D6
R6 50
R7 30
OFFSET NULL (NOTE 9)
V-
NOTES: 9. Only available with 14 Lead DIP (E1 Suffix). 10. All resistance values are in ohms.
5
CA3240, CA3240A Application Information
Circuit Description
The schematic diagram details one amplifier section of the CA3240. It consists of a differential amplifier stage using PMOS transistors (Q9 and Q10) with gate-to-source protection against static discharge damage provided by zener diodes D3, D4, and D5. Constant current bias is applied to the differential amplifier from transistors Q2 and Q5 connected as a constant current source. This assures a high common-mode rejection ratio. The output of the differential amplifier is coupled to the base of gain stage transistor Q13 by means of an NPN current mirror that supplies the required differential-to-single-ended conversion. Provision for offset null for types in the 14 lead plastic package (E1 suffix) is provided through the use of this current mirror. The gain stage transistor Q13 has a high impedance active load (Q3 and Q4) to provide maximum open-loop gain. The collector of Q13 directly drives the base of the compound emitter-follower output stage. Pulldown for the output stage is provided by two independent circuits: (1) constant-currentconnected transistors Q14 and Q15 and (2) dynamic currentsink transistor Q16 and its associated circuitry. The level of pulldown current is constant at about 1mA for Q15 and varies from 0 to 18mA for Q16 depending on the magnitude of the voltage between the output terminal and V+. The dynamic current sink becomes active whenever the output terminal is more negative than V+ by about 15V. When this condition exists, transistors Q21 and Q16 are turned on causing Q16 to sink current from the output terminal to V-. This current always flows when the output is in the linear region, either from the load resistor or from the emitter of Q18 if no load resistor is present. The purpose of this dynamic sink is to permit the output to go within 0.2V (VCE (sat)) of V- with a 2k load to ground. When the load is returned to V+, it may be necessary to supplement the 1mA of current from Q15 in order to turn on the dynamic current sink (Q16). This may be accomplished by placing a resistor (Approx. 2k) between the output and V-.
Input Circuit Considerations
As indicated by the typical VICR, this device will accept inputs as low as 0.5V below V-. However, a series currentlimiting resistor is recommended to limit the maximum input terminal current to less than 1mA to prevent damage to the input protection circuitry. Moreover, some current-limiting resistance should be provided between the inverting input and the output when the CA3240 is used as a unity-gain voltage follower. This resistance prevents the possibility of extremely large inputsignal transients from forcing a signal through the inputprotection network and directly driving the internal constantcurrent source which could result in positive feedback via the output terminal. A 3.9k resistor is sufficient. The typical input current is on the order of 10pA when the inputs are centered at nominal device dissipation. As the output supplies load current, device dissipation will increase, rasing the chip temperature and resulting in increased input current. Figure 4 shows typical input-terminal current versus ambient temperature for the CA3240.
V+
+HV LOAD
CA3240 RL
RS 120VAC
LOAD 30V NO LOAD
MT2
Output Circuit Considerations
Figure 24 shows output current-sinking capabilities of the CA3240 at various supply voltages. Output voltage swing to the negative supply rail permits this device to operate both power transistors and thyristors directly without the need for level-shifting circuitry usually associated with the 741 series of operational amplifiers. Figure 3 shows some typical configurations. Note that a series resistor, RL, is used in both cases to limit the drive available to the driven device. Moreover, it is recommended that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit.
CA3240 RL MT1
FIGURE 3. METHODS OF UTILIZING THE VCE (SAT) SINKING CURRENT CAPABILITY OF THE CA3240 SERIES
6
CA3240, CA3240A
10K VS = 15V
1K
100
10
shift in the output voltage (Terminal 7) of the CA3240E. These positive transitions are fed into the CA3059, which is used as a latching circuit and zero-crossing TRIAC driver. When a positive pulse occurs at Terminal 7 of the CA3240E, the TRIAC is turned on and held on by the CA3059 and its associated positive feedback circuitry (51k resistor and 36k/42k voltage divider). When the positive pulse occurs at Terminal 1 (CA3240E), the TRIAC is turned off and held off in a similar manner. Note that power for the CA3240E is supplied by the CA3059 internal power supply. The advantage of using the CA3240E in this circuit is that it can sense the small currents associated with skin conduction while allowing sufficiently high circuit impedance to provide protection against electrical shock.
INPUT CURRENT (pA)
-60
-40
-20
0
20 40 60 80 TEMPERATURE (oC)
100
120 140
FIGURE 4. INPUT CURRENT vs TEMPERATURE
Dual Level Detector (Window Comparator)
Figure 7 illustrates a simple dual liquid level detector using the CA3240E as the sensing amplifier. This circuit operates on the principle that most liquids contain enough ions in solution to sustain a small amount of current flow between two electrodes submersed in the liquid. The current, induced by an 0.5V potential applied between two halves of a PC board grid, is converted to a voltage level by the CA3240E in a circuit similar to that of the on/off touch switch shown in Figure 6. The changes in voltage for both the upper and lower level sensors are processed by the CA3140 to activate an LED whenever the liquid level is above the upper sensor or below the lower sensor.
It is well known that MOSFET devices can exhibit slight changes in characteristics (for example, small changes in input offset voltage) due to the application of large differential input voltages that are sustained over long periods at elevated temperatures. Both applied voltage and temperature accelerate these changes. The process is reversible and offset voltage shifts of the opposite polarity reverse the offset. In typical linear applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage.
Constant-Voltage/Constant-Current Power Supply
The constant-voltage/constant-current power supply shown in Figure 8 uses the CA3240E1 as a voltage-error and current-sensing amplifier. The CA3240E1 is ideal for this application because its input common-mode voltage range includes ground, allowing the supply to adjust from 20mV to 25V without requiring a negative supply voltage. Also, the ground reference capability of the CA3240E1 allows it to sense the voltage across the 1 current-sensing resistor in the negative output lead of the power supply. The CA3086 transistor array functions as a reference for both constantvoltage and constant-current limiting. The 2N6385 power Darlington is used as the pass element and may be required to dissipate as much as 40W. Figure 9 shows the transient response of the supply during a 100mA to 1A load transition.
Offset-Voltage Nulling
The input offset voltage of the CA3240AE1 and CA3240E1 can be nulled by connecting a 10k potentiometer between Terminals 3 and 14 or 5 and 8 and returning its wiper arm to Terminal 4, see Figure 5A. This technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized. Typical values of series resistors that may be placed at either end of the potentiometer, see Figure 5B, to optimize its utilization range are given in the table "Electrical Specifications for Equipment Design" shown on third page of this data sheetAn alternate system is shown in Figure 5C. This circuit uses only one additional resistor of approximately the value shown in the table. For potentiometers, in which the resistance does not drop to 0 at either end of rotation, a value of resistance 10% lower than the values shown in the table should be used.
Precision Differential Amplifier
Figure 10 shows the CA3240E in the classical precision differential amplifier circuit. The CA3240E is ideally suited for biomedical applications because of its extremely high input impedance. To insure patient safety, an extremely high electrode series resistance is required to limit any current that might result in patient discomfort in the event of a fault condition. In this case, 10M resistors have been used to limit the current to less than 2A without affecting the performance of the circuit. Figure 11 shows a typical electrocardiogram waveform obtained with this circuit.
Typical Applications
On/Off Touch Switch
The on/off touch switch shown in Figure 6 uses the CA3240E to sense small currents flowing between two contact points on a touch plate consisting of a PC board metallization "grid". When the "on" plate is touched, current flows between the two halves of the grid causing a positive 7
CA3240, CA3240A
V+ 13(9) 1(7) CA3240 2(6) 4 3 (5) 12(10) CA3240 V+
14(8) 10k
R (NOTE 11)
10k
R (NOTE 11)
V-
V-
FIGURE 5A. BASIC
V+
FIGURE 5B. IMPROVED RESOLUTION
CA3240
10k (NOTE 11) R V-
FIGURE 5C. SIMPLER IMPROVED RESOLUTION NOTE: 11. See Electrical Specification Table for value of R. FIGURE 5. THREE OFFSET-VOLTAGE NULLING METHODS, (CA3240AE1 ONLY)
44M +6V +6V "ON" 1M 6 0.01F 5.1M 1M +6V 5 8 1/2 CA3240 + 51K 36K 7 1N914 42K "OFF" 3 2 0.01F 1M 1/2 CA3240 + 13 9 10 11 7 1 1N914 4 +6V SOURCE 2 + CA3059
10K (2W) RS (NOTE 12) 12K 8 MT2 120V/220V AC 60Hz/50Hz 40W 120V LIGHT T2300B (NOTE 12) G 4 MT1 COMMON
-
5
-
-
100F (16V)
44M
NOTE: 12. At 220V operation, TRIAC should be T2300D, RS = 18K, 5W. FIGURE 6. ON/OFF TOUCH SWITCH
8
CA3240, CA3240A
12M +15V
8 100K 2 +15V 240K HIGH LEVEL 8.2K 5 100K 6 1/2 CA3240 + (0.5V) 3
0.1F +15V 1 33K 3 160K 100K 2 100K 7 + CA3140 6 680 4 LED 7 0.1F
- 1/2
CA3240 +
-
4 LED ON WHEN LIQUID OUTSIDE OF LIMITS
LOW LEVEL
12M
FIGURE 7. DUAL LEVEL DETECTER
VO V+ 2N6385 DARLINGTON 3 75 3K 12 2 13 1/2 CA3240E1 + 4 100 VI = 30V + 2.7K 100K 2000F 50V 10 11 1 14 CA3086E TRANSISTOR ARRAY 9 3 8 5 7 1K 4 6 6.2K 1 1W 13 820 680K 50K 100K 12 6 2.2K 82K V+ 2 + 5F 16V 100K 7 9 1/2 CA3240E1 + 1N914 0.056F 10K IO
-
1 2 180K
1
+ 500 - F
-
-
-
10
CHASSIS GROUND VO RANGE = 20mV TO 25V LOAD REGULATION: VOLTAGE <0.08% CURRENT <0.05% OUTPUT HUM AND NOISE 150VRMS (10MHz BANDWIDTH) SINE REGULATION 0.1%/VO IO RANGE = 10mA - 1.3A
100K
FIGURE 8. CONSTANT-VOLTAGE/CONSTANT-CURRENT POWER SUPPLY
9
CA3240, CA3240A
Top Trace: Output Voltage; 500mV/Div., 5s/Div. Bottom Trace: Collector Of Load Switching Transistor Load = 100mA to 1A; 5V/Div., 5s/Div. FIGURE 9. TRANSIENT RESPONSE
+15V 8 10M 3 2 + 1/2 CA3240 1 2000pF +15V 1% 5.1K 2 CA3140 3.9K 100K 1% 5.1K 1% 3 4 0.1F -15V 7 FREQUENCY RESPONSE (-3dB) DC TO 1MHz SLEW RATE = 1.5V/s COMMON MODE REJ: 86dB GAIN RANGE: 35dB TO 60dB 0.1F -15V 6 2K 0.1F OUTPUT 0.1F
100K 1%
-
2000pF
GAIN CONTROL
100K 1% 100K
7
TWO COND. SHIELDED CABLE
6 5 10M
-
2000pF
1/2 CA3240 + 4
FIGURE 10. PRECISION DIFFERENTIAL AMPLIFIER
10
CA3240, CA3240A
Vertical: 1.0mV/Div. Amplifier Gain = 100X Scope Sensitivity = 0.1V/Div. Horizontal: >0.2s/Div. (Uncal) FIGURE 11. TYPICAL ELECTROCARIOGRAM WAVEFORM
0.015F
100K +15V 8 +15V 5.1K 3 1.3 K 5 13K 6 + 1/2 CA3240E 2 1/2 CA3240E + 200K 2 7 2K +15V
-
1
2K 3 +
7
C30809 PHOTO DIODE
CA3140
6
OUTPUT
4 -15V
4 -15V 100K
C30809 PHOTO DIODE
200k
0.015F
FIGURE 12. DIFFERENTIAL LIGHT DETECTOR
Differential Light Detector
In the circuit shown in Figure 12, the CA3240E converts the current from two photo diodes to voltage, and applies 1V of reverse bias to the diodes. The voltages from the CA3240E outputs are subtracted in the second stage (CA3140) so that
only the difference is amplified. In this manner, the circuit can be used over a wide range of ambient light conditions without circuit component adjustment. Also, when used with a light source, the circuit will not be sensitive to changes in light level as the source ages.
11
CA3240, CA3240A Typical Performance Curves
GAIN BANDWIDTH PRODUCT (MHz) OPEN LOOP VOLTAGE GAIN (dB) RL = 2k 20 10 RL = 2k CL = 100pF
125 100 75
TA = -40oC 25oC 85oC
TA = -40oC 25oC 85oC
50 25 0 5 10 15 20 25
1 0 5 SUPPLY VOLTAGE (V) 10 15 SUPPLY VOLTAGE (V) 20 25
FIGURE 13. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE
FIGURE 14. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE
20
TOTAL SUPPLY CURRENT (mA) FOR BOTH AMPS
RL = 2k CL = 100pF
10 9 8 7 6 5 4 3 2
RL = 25 oC TA = -40oC 85 oC
15 SLEW RATE (V/s) 25oC 10 TA = -40oC 85 oC 5
0
0
5
10
15
20
25
0
5
10
15
20
25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 15. SLEW RATE vs SUPPLY VOLTAGE
FIGURE 16. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
COMMON MODE REJECTION RATIO (dB)
SUPPLY VOLTAGE: VS = 15V TA = 25oC 25 OUTPUT VOLTAGE (VP-P) 20 15 10
120 100 80 60 40 20 0 101
SUPPLY VOLTAGE: VS = 15V TA = 25oC
5 0 10K
100K FREQUENCY (Hz)
1M
4M
10 2
103
104
105
10 6
107
FREQUENCY (Hz)
FIGURE 17. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY
FIGURE 18. COMMON MODE REJECTION RATIO vs FREQUENCY
12
CA3240, CA3240A Typical Performance Curves
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz) 1000 SUPPLY VOLTAGE: VS = 15V TA = 25 oC
(Continued)
POWER SUPPLY REJECTION RATIO (dB) SUPPLY VOLTAGE: VS = 15V TA = 25 oC POWER SUPPLY REJECTION RATIO = VIO/ VS +PSRR
100
100
RS = 100
80 60 -PSRR 40
10
20
1 1
101
10 2 10 3 FREQUENCY (Hz)
10 4
105
101
102
103
104
10 5
10 6
10 7
FREQUENCY (Hz)
FIGURE 19. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
FIGURE 20. POWER SUPPLY REJECTION RATIO vs FREQUENCY
12 OUTPUT SINK CURRENT (mA) PER AMP 10 8 6 4 2 0
TA = 25oC SUPPLY CURRENT (mA) PER AMP (DOUBLE FOR BOTH) VS = 15V ONE AMPLIFIER OPERATING
17.5 15 12.5 10 7.5 5 2.5
TA = 25oC VS = 15V RL =
-15
-10
-5 0 5 10 OUTPUT VOLTAGE (V)
15
-15
-10
-5 0 5 10 OUTPUT VOLTAGE (V)
15
FIGURE 21. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
FIGURE 22. SUPPLY CURRENT vs OUTPUT VOLTAGE
140 130 120 110 100 90 80 0.1
SATURATION VOLTAGE (mV)
CROSSTALK (dB)
TA = 25oC AMP A AMP B AMP B AMP A VS = 15V VO = 5VRMS
OUTPUT STAGE TRANSISTOR (Q15, Q16)
1000
V- = 0V TA = 25oC
100
V+ = +5V
+15V +30V
10
1
101 FREQUENCY (Hz)
10 2
10 3
1.0 0.01
0.1
1.0
10
LOAD (SINKING) CURRENT (mA)
FIGURE 23. CROSSTALK vs FREQUENCY
FIGURE 24. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15 AND Q16 vs LOAD CURRENT
13
CA3240, CA3240A Typical Performance Curves
RL = INPUT AND OUTPUT VOLTAGE REFERENCED TO TERMINAL V+(V) 0 -0.5 -1 -1.5 -2 -2.5 -3 TA = 25 oC 0 5 TA = -40oC TA = 85 oC OUTPUT VOLTAGE (+VO) COMMON MODE VOLTAGE (+VICR) TA = 25oC TA = 85oC
(Continued)
INPUT AND OUTPUT VOLTAGE REFERENCED TO TERMINAL V- (V) 1.5 1.0 0.5
RL = OUTPUT VOLTAGE (-VO) COMMON MODE VOLTAGE (-VICR) TA = -40oC TO 85 oC 0 -0.5 -1.0 -1.5 TA = 85oC TA = -40oC
TA = 25 oC
TA = -40oC 20 25
10 15 SUPPLY VOLTAGE (V)
0
5
10
15
20
25
SUPPLY VOLTAGE (V)
FIGURE 25A.
FIGURE 25B.
FIGURE 25. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
SUPPLY VOLTAGE: VS = 15V TA = 25oC, RL = 2k, CL = 100pF 10 8 INPUT VOLTAGE (V) 6 4 2 0 -2 -4 -6 -8 -10 0.1
2 4
+15V 1mV 1mV 0.1F + 10k CA3240 SIMULATED LOAD 2k
10mV
10mV
FOLLOWER INVERTING -15V 1mV 10mV
6 8
100pF 0.1F
1mV
2k 0.05F 10
10mV 1.0 TIME (s)
2 4 6 8
FIGURE 26A. SETTLING TIME vs INPUT VOLTAGE
5k +15V 5k 0.1F
FIGURE 26B. TEST CIRCUIT (FOLLOWER)
CA3240 200
SIMULATED LOAD 2k
+
100pF 0.1F
4.99k
-15V
5.11k
D1 1N914
SETTLING POINT D2 1N914
FIGURE 26C. TEST CIRCUIT (INVERTING) FIGURE 26. INPUT VOLTAGE vs SETTLING TIME
14
CA3240, CA3240A Typical Performance Curves
10K OPEN LOOP VOLTAGE GAIN (dB) VS = 15V 100
(Continued)
PHASE
-105 -120 -135
INPUT CURRENT (pA)
1K
80 RL = 2k, CL = 100pF 60 GAIN
-150
100
40
10
20 0 101
1 -60
-40
-20
0
20
40
60
80
100
120
140
102
103
104
10 5
10 6
10 7
10 8
TEMPERATURE (oC)
FREQUENCY (Hz)
FIGURE 27. INPUT CURRENT vs TEMPERATURE
FIGURE 28. OPEN LOOP VOLTAGE GAIN AND PHASE vs FREQUENCY
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine, CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 EUROPE Intersil Europe Sarl Ave. C - F Ramuz 43 CH-1009 Pully Switzerland TEL: +41 21 7293637 FAX: +41 21 7293684 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building 83 Austin Road TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433
15
OPEN LOOP PHASE (DEGREES)
VS = 15V TA = 25oC
-75 RL = 2k, CL = 0pF -90

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