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CXG1010N
Power Amplifier for PHS For the availability of this product, please contact the sales office.
Description The CXG1010N is a power amplifier for PHS. This IC is designed using the Sony's GaAs J-FET process and operates at a single power supply. Features * High output power 21.5 dBm * Positive power supply drive VDD=3.4 V * Low current consumption 200 mA * High gain 40 dB Typ. * Low distortion (ACP) -59 dBc Typ. * Small mold package 16-pin SSOP Structure GaAs J-FET MMIC 16 pin SSOP (Plastic)
Absolute Maximum Ratings (Ta=25 C) 6 * Supply voltage VDD * Voltage between gate and source Vgs0 1.5 * Drain current IDD 500 * Power dissipation PD 3 * Channel temperature * Operating temperature * Storage temperature Tch Top Tstg 175 -35 to +85 -65 to +150
V V mA W C C C
Electrical Characteristics VDD=3.4 V, VCTL=2.0 V, f=1.90 GHz Item 1 Current consumption 1 Gate voltage adjustment value Input VSWR Output power (for -15.5 dBm input) 2 Power gain 2 Gain control 3 2 Average leak power level (600 kHz100 kHz) 2 Average leak power level (900 kHz100 kHz) Symbol IDD VGG2 VSWRIN POUT GP GCTL PLEAK600 PLEAK900 Min. 0 21.5 37 Typ. 200 0.5 1.5 40 20 -59 -65 -54 -59 Max. 1.0 2.0 43
(Ta=25 C) Unit mA V -- dBm dB dB dBc dBc
1 This value is adjusted by VGG1 and VGG2 set with Sony's recommended current adjustment method when 21.5 dBm is output. In this time, the voltage ratio of VGG1 and VGG2 should match to the voltage ratio generated by the resistance of the recommended gate bias circuit. 2 When 21.5 dBm is output. 3 GCTL=GP (VCTL 2.0 V)-GP (VCTL 0 V)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E95836-TE
CXG1010N
Block Diagram
Pin Configuration
VDD1
VDD2
VDD3
GND RFOUT GND VGG2 GND VCTL VGG1 GND 16 1
VDD3 GND VDD2 GND VDD1 GND RFIN GND
RFIN
RFOUT
VGG1
VCTL VGG2
Gate adjustment pin
Gate adjustment pin VGG2
470
VGG1 680
Recommended Current Adjustment Method (1) VGG2/PIN separate adjustment (VGG2 adjustment 1) When the RF input (PIN) is off, the current consumption (IDD) is adjusted to 200 mA. Variation of IDD and POUT due to adjustment (2) Simple adjustment (IDD read) When the RF input (PIN) is off, the gate voltage (VGG2) is set to 0.4 V and it is read. Variation of IDD and POUT due to adjustment (VGG2 setting) The formula1 where VGG2=f (IDD: VGG2=0.4 V) is used to set VGG2. 1 e.g. VGG2=a-b x IDD (PIN adjustment) (PIN adjustment 1) The output power (POUT) is adjusted to 21.5 dBm. IDD=20020 mA POUT=21.5 dBm (VGG2 adjustment 2) The current consumption (IDD) is finely adjusted to 200 mA. IDD=200 mA POUT=21.50.2 dBm (PIN adjustment 2) The output power (POUT) is finely adjusted to 21.5 dBm. IDD=2005 mA POUT=21.5 dBm
The output power (POUT) is adjusted to 21.5 dBm.
IDD=2005 mA POUT=21.5 dBm
--2--
CXG1010N
Current Consumption Variation with Recommended Current Adjustment Method (For POUT=21.5 dBm output) (1) Separate adjustment
(mA) 230 5/ VGG2/PIN separate adjustment method (Distribution of the current consumption IDD after executing the PIN adjustment 1)
IDD
180
0 VGG2 VGG2/PIN separate adjustment method (Distribution of the current consumption IDD after executing the PIN adjustment 2)
0.8 (V)
(mA) 220
5/
IDD
180
0 VGG2
0.8 (V)
(2) Simple adjustment
Simple adjustment method (Distribution of the current consumption IDD after executing the PIN adjustment) VGG2=a-bxIDD (Pin off/VGG2=0.4V): a=0.804, b=2.07
(mA) 220
5/
IDD
180 0
VGG2
0.8 (V)
--3--
CXG1010N
Recommended Evaluation Circuit
50mm 3.0V
100
6.8k
RFIN VCTL 1
680 470
RV1 Variable resistor Rv RV2 10k (Max)
GND
1 VGG2 18n 10n 1000p
180
RFOUT
ViaHole GND 1 GND
VDD
Glass fabric-base epoxy board (0.2 mm thickness) GND for the overall back side
Recommended Gate Bias Circuit and Circuit Characteristics
3.0V
(V) VGG2
100
6.8k RV1 Variable RV2 resistor Rv 10k (Max) 0.5
VGG2 470 VGG1 680
180
0
5
10 RV1 (k)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.
--4--
CXG1010N
Example of Representative Characteristics (Ta=25 C)
Input/output characteristics (POUT/ACP) VDD=3.4V, Vctl=2.0V,IDD=200mA@POUT=21.5dBm 25 23 21 21.5dBm -45 -40
POUT-Output power (dBm)
19 17 15 13 11 -55 9 ACP 7 5 -40 -60 -35 -30 -25 -20 -15 PIN-Input power (dBm) POUT -50
GAIN, ACP vs. IDD Freq=1.9GHz, VDD=3.4V, Vctl=2.0V, POUT constant 45 44 43 42 41 POUT=22dBm POUT=21.5dBm GAIN POUT=22dBm -48 -49 -51 -52 -53 -54 -55 -56 -57 -58 -59 ACP -60 -61 -62 -50 24
POUT, ACP vs. VDD Frequency=1.9 GHz, Vctl=2.0 V, PINVGG2 constant (IDD=200mA@VDD=3.4V) -50 -51
ACP-Leak power ratio of adjacent channel (dBc)
ACP-Leak power ratio of adjacent channel (dBc)
23
-52 POUT -53
GAIN-Gain (dB)
40 POUT=21.5dBm 39 38 37 36 35 34 33 32 31
POUT=22dBm 22 @VDD=3.4V POUT=22dBm @VDD=3.4V
-54 -55 -56 -57 -58 POUT=21.5dBm @VDD=3.4V -59 -60 2
21
POUT=21.5dBm @VDD=3.4V
ACP 20
30 -63 140 150 160 170 180 190 200 210 220 230 240 250 260 IDD-Current consumption (mA)
19 2
3
4 VDD-Drain voltage (V)
5
--5--
ACP-Leak power ratio of adjacent channel (dBc)
POUT-Output power (dBm)
CXG1010N
Package Outline
Unit : mm
16PIN SSOP (PLASTIC)
5.0 0.1 + 0.2 1.25 - 0.1 0.1 16 9 A
4.4 0.1
1 + 0.1 0.22 - 0.05
8 0.65 0.12 + 0.05 0.15 - 0.02
0.1 0.1
0 to 10 DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-16P-L01 SSOP016-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.1g
--6--
0.5 0.2
6.4 0.2

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