View MAX9124_104813.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1991; Rev 0; 4/01
KIT ATION EVALU ABLE AVAIL
Quad LVDS Line Driver
Features
o Pin Compatible with DS90LV031A o Guaranteed 800Mbps Data Rate o 250ps Maximum Pulse Skew o Conforms to TIA/EIA-644 LVDS Standard o Single +3.3V Supply o 16-Pin TSSOP and SO Packages
General Description
The MAX9124 quad low-voltage differential signaling (LVDS) line driver is ideal for applications requiring high data rates, low power, and low noise. The MAX9124 is guaranteed to transmit data at speeds up to 800Mbps (400MHz) over controlled impedance media of approximately 100. The transmission media may be printed circuit (PC) board traces, backplanes, or cables. The MAX9124 accepts four LVTTL/LVCMOS input levels and translates them to LVDS output signals. Moreover, the MAX9124 is capable of setting all four outputs to a high-impedance state through two enable inputs, EN and EN, thus dropping the device to an ultra-low-power state of 16mW (typ) during high impedance. The enables are common to all four transmitters. Outputs conform to the ANSI TIA/EIA-644 LVDS standard. The MAX9124 operates from a single +3.3V supply and is specified for operation from -40C to +85C. It is available in 16-pin TSSOP and SO packages. Refer to the MAX9125/ MAX9126 data sheet for quad LVDS line receivers.
MAX9124
Ordering Information
PART MAX9124EUE MAX9124ESE TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 SO
Applications
Digital Copiers Laser Printers Cell Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution
Typical Applications Circuit
LVDS SIGNALS MAX9126
MAX9124
TX
115
RX
Pin Configuration
TOP VIEW
IN1 1 OUT1+ 2 OUT1- 3 EN 4 OUT2- 5 OUT2+ 6 IN2 7 GND 8 16 VCC 15 IN4 14 OUT4+
LVTTL/LVCMOS DATA INPUT
TX
115
RX
LVTTL/LVCMOS DATA OUTPUT
TX
115
RX
MAX9124
13 OUT412 EN 11 OUT310 OUT3+ 9 IN3
100 SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES TX 115 RX
TSSOP/SO
* Future product--contact factory for availability. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad LVDS Line Driver MAX9124
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-0.3V to (VCC + 0.3V) OUT_+, OUT_- to GND..........................................-0.3V to +3.9V Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW 16-Pin SO (derate 8.7mW/C above +70C)................696mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection Human Body Model, OUT_+, OUT_- ..............................6kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER LVDS OUTPUT (OUT_+, OUT_-) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Voltage Change in Magnitude of VOS Between Complementary Output States Output High Voltage Output Low Voltage Differential Output Short-Circuit Current (Note 3) Output Short-Circuit Current Output High-Impedance Current Power-Off Output Current INPUTS (IN_, EN, EN) High-Level Input Voltage Low-Level Input Voltage Input Current SUPPLY CURRENT No-Load Supply Current Loaded Supply Current Disabled Supply Current ICC ICCL ICCZ RL = , IN_ = VCC or 0 for all channels RL = 100, IN_ = VCC or 0 for all channels Disabled, IN_ = VCC or 0 for all channels, EN = 0, EN = VCC 9.2 22.7 4.9 11 30 6 mA mA mA VIH VIL IIN IN_, EN, EN = 0 or VCC 2.0 GND -20 VCC 0.8 20 V V A VOD VOD VOS VOS VOH VOL IOSD IOS IOZ IOFF Enabled, VOD = 0 OUT_+ = 0 at IN_ = VCC or OUT_- = 0 at IN_ = 0, enabled EN = low and EN = high, OUT_+ = 0 or VCC, OUT_- = 0 or VCC , RL = VCC = 0 or open, OUT_+ = 0 or 3.6V, OUT_= 0 or 3.6V, RL = -10 -10 -3.8 0.90 -9 -9 10 10 Figure 1 Figure 1 Figure 1 Figure 1 1.125 250 368 1 1.25 4 450 25 1.375 25 1.6 mV mV V mV V V mA mA A A SYMBOL CONDITIONS MIN TYP MAX UNITS
2
_______________________________________________________________________________________
Quad LVDS Line Driver
SWITCHING CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, CL = 10pF, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 4, 5, 6)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew (Note 7) Differential Channel-to-Channel Skew (Note 8) Differential Part-to-Part Skew (Note 9) Differential Part-to-Part Skew (Note 10) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 11) SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX CONDITIONS Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 4 and 5 Figures 4 and 5 Figures 4 and 5 Figures 4 and 5 400 0.1 0.1 0.35 0.35 MIN 0.8 0.8 TYP 1.42 1.44 0.02 MAX 2.0 2.0 0.25 0.35 0.8 1.2 0.7 0.7 5 5 5 5 UNITS ns ns ns ns ns ns ns ns ns ns ns ns MHz
MAX9124
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25C. Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except VOD. Note 3: Guaranteed by correlation data. Note 4: AC parameters are guaranteed by design and characterization. Note 5: CL includes probe and jig capacitance. Note 6: Signal generator conditions for dynamic tests: VOL = 0, VOH = 3V, f = 100MHz, 50% duty cycle, RO = 50, tR 1ns, tF 1ns (0% to 100%). Note 7: tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|. Note 8: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. Note 9: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5C of each other. Note 10: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 11: fMAX signal generator conditions: VOL = 0, VOH = 3V, f = 400MHz, 50% duty cycle, RO = 50, tR 1ns, tF 1ns (0% to 100%). Transmitter output criteria: duty cycle = 45% to 55%, VOD 250mV.
_______________________________________________________________________________________
3
Quad LVDS Line Driver MAX9124
Typical Operating Characteristics
(TA = +25C)
SINGLE-ENDED OUTPUT VOLTAGE vs. LOAD RESISTANCE (RL = 50 TO 400)
MAX9124 toc01
SINGLE-ENDED OUTPUT VOLTAGE (V)
1.70 1.50 1.30 1.10 0.90 0.70 0.50 0.30 50 100 150 200 250 300 350 OUT_VCC = +3.6V _VCC = +3.0V OUT_+
SINGLE-ENDED OUTPUT VOLTAGE (V)
1.90
2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0 0
DOUT+ VCC = +3.6V _VCC = +3.0V
DOUT1000 2000 3000 4000 5000 6000 7000 RL ()
400
RL ()
Pin Description
PIN 1, 7, 9, 15 2, 6, 10, 14 3, 5, 11, 13 4, 12 8 16 NAME IN_ OUT_+ OUT_EN, EN GND VCC LVTTL/LVCMOS Driver Inputs Noninverting LVDS Driver Outputs Inverting LVDS Driver Outputs Driver Enable Inputs. The driver is disabled and in high impedance when EN is low and EN is high. For other combinations of EN and EN, the outputs are active. Ground Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. FUNCTION
4
_______________________________________________________________________________________
MAX9124 toc02
2.10
SINGLE-ENDED OUTPUT VOLTAGE vs. LOAD RESISTANCE (RL = 0 TO 7k)
Quad LVDS Line Driver
Detailed Description
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9124 is an 800Mbps quad differential LVDS driver that is designed for high-speed, point-to-point, and low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The MAX9124 generates a 2.5mA to 4.0mA output current using a current-steering configuration. This currentsteering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The driver outputs are shortcircuit current limited and enter a high-impedance state when the device is not powered or is disabled. The current-steering architecture of the MAX9124 requires a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor at the input of an LVDS receiver. Logic states are determined by the direction of current flow through the termination resistor. With a typical 3.7mA output current, the MAX9124 produces an output voltage of 370mV when driving a 100 load.
MAX9124
Table 1. Input/Output Function Table
ENABLES EN L EN H INPUTS IN_ X L H Z L H OUTPUTS OUT_+ OUT_ Z H L
All other combinations of ENABLE inputs
close to the device as possible, with the smaller valued capacitor closest to VCC.
Differential Traces
Output trace characteristics affect the performance of the MAX9124. Use controlled-impedance traces to match trace impedance to the transmission medium. Eliminate reflections and ensure that noise couples as common mode by running the differential trace pairs close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
Cables and Connectors
Transmission media should have a nominal differential impedance of 100. To minimize impedance discontinuities, use cables and connectors that have matched differential impedance. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables, such as twisted pair, offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver.
Termination
Because the MAX9124 is a current-steering device, no output voltage will be generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels depend upon the value of the termination resistor. The MAX9124 is optimized for point-to-point interface with 100 termination resistors at the receiver inputs. Termination resistance values may range between 90 and 132, depending on the characteristic impedance of the transmission medium.
Board Layout
For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Isolate the LVTTL/LVCMOS and LVDS signals from each other to prevent coupling.
Chip Information
TRANSISTOR COUNT: 2007 PROCESS: CMOS
Applications Information
Power-Supply Bypassing
Bypass V CC with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallel as
_______________________________________________________________________________________
5
Quad LVDS Line Driver MAX9124
OUT_+ CL
OUT_ + RL/2 GND RL/2 VOS VOD
S
VCC
IN_
VO
GENERATOR
IN_
RL OUT_ CL
50
OUT_-
Figure 1. Driver VOD and VOS Test Circuit
Figure 2. Driver Propagation Delay and Transition Time Test Circuit
3V IN_ 1.5V 1.5V 0 tPLHD OUT_ 0 DIFFERENTIAL OUT_+ 0 VOL 80% VDIFF 50% 20% tTLH 0 80% VDIFF = (VOUT_+) - (VOUT_-) 0 20% tTHL tPHLD VOH
Figure 3. Driver Propagation Delay and Transition Time Waveforms
CL
OUT_+ VCC GND GENERATOR 50 1/4 MAX9124 CL EN EN RL/2 OUT_+1.2V IN_ RL/2
Figure 4. Driver High-Impedance Delay Test Circuit
6
_______________________________________________________________________________________
Quad LVDS Line Driver MAX9124
EN WHEN EN = VCC 1.5V 1.5V 0 3V
3V 1.5V EN WHEN EN = 0 tPHZ OUT_+ WHEN IN_ = VCC OUT_- WHEN IN_ = 0 50% 50% 1.2V 1.2V 50% OUT_+ WHEN IN_ = 0 OUT_- WHEN IN_ = VCC 50% VOL tPLZ tPZL tPZH VOH 1.5V 0
Figure 5. Driver High-Impedance Delay Waveform
Functional Diagram
OUT1+ IN1 OUT1-
OUT2+ IN2 OUT2-
OUT3+ IN3 OUT3-
OUT4+ IN4 OUT4-
EN EN
_______________________________________________________________________________________
7
Quad LVDS Line Driver MAX9124
Package Information
TSSOP,NO PADS.EPS
8
_______________________________________________________________________________________
Quad LVDS Line Driver
Package Information (continued)
SOICN.EPS
MAX9124
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX9124

	To Download MAX9124 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .