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FEATURES Excellent TCVos Match, 2 V/ C Max Low Input Offset Voltage, 150 V Max Low Supply Current, 550 A Max Single Supply Operation, 5 V to 30 V Low Input Offset Voltage Drift, 0.75 V/ C High Open-Loop Gain, 1500 V/mV Min High PSRR, 3 V/V Wide Common-Mode Voltage Range, V- to within 1.5 V of V+ Pin Compatible with 1458, LM158, LM2904 Available in Die Form
Dual Low Power Operational Amplifier, Single or Dual Supply OP221
PIN CONNECTIONS 8-Lead SO (S-Suffix)
+IN A 1 V- 2 +IN B 3 -IN B 4
8 7 6 5
8-Lead HERMETIC DIP (Z-Suffix)
-IN A OUT A V+ OUT B OUT A 1 -IN A 2 +IN A 3 V- 4
8 7 6 5
V+ OUT B -IN B +IN B
NC = NO CONNECT
NC = NO CONNECT
GENERAL DESCRIPTION
The OP221 is a monolithic dual operational amplifier that can be used either in single or dual supply operation. The wide supply voltage range, wide input voltage range, and low supply current drain of the OP221 make it well-suited for operation from batteries or unregulated power supplies. The excellent specifications of the individual amplifiers combined with the tight matching and temperature tracking between channels
provide high performance in instrumentation amplifier designs. The individual amplifiers feature very low input offset voltage, low offset voltage drift, low noise voltage, and low bias current. They are fully compensated and protected. Matching between channels is provided on all critical parameters including input offset voltage, tracking of offset voltage vs. temperature, non-inverting bias currents, and common-mode rejection.
SIMPLIFIED SCHEMATIC
V+ Q11 Q12 Q3 -IN +IN Q7 Q1 Q4 Q2 Q9 Q10 Q4 Q27 Q29 Q26 OUTPUT Q28
Q5
Q6 Q13 NULL* Q33
V- *ACCESSIBLE IN CHIP FORM ONLY
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
OP221-SPECIFICATIONS (Electrical Characteristics at V =
s
.
2.5 V to
Max 150 3 100
15 V, TA = 25 C, unless otherwise noted.)
OP221G Min Typ 250 1.5 70 0/3.5 -15/13.5 Max 500 7 120 Unit V nA nA V 85 dB 90 32 57 800 0.8/4 13.5 100 180 V/V V/mV V
OP221A/E Parameter Symbol Conditions Min Typ 75 VCM = 0 VCM = 0 V+ = 5 V, V- = 0 V (Note 2) VS = 15 V V+ = -5 V, V- = 0 V 0 V VCM 3.5 V VS = 15 V -15 V VCM 13.5 V VS = 2.5 V to 15 V V- = 0 V, V+ = 5 V to 30 V VS = 15 V, RL = 10 k VO = 10 V V+ = 5 V, V- = 0 V RL = 10 k VS = 15 V, RL = 10 k RL = 10 k (Note 1) VS = 2.5 V, No Load VS = 15 V, No Load 1500 0.7/4.1 13.8 0.2 03 600 450 600 550 800 0/3.5 -15/13.5 90 95 100 100 3 6 10 18 0.5 55 Input Offset Voltage VOS Input Offset Current Ios Input Bias Current IB
Input Voltage Range IVR Common-Mode Rejection Ratio CMRR
75 80
Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Slew Rate Bandwidth Supply Current (Both Amplifiers)
PSRR Avo VO
SR BW ISY
0.2
0.3 600 550 850 650 900
V/S kHz A
NOTES 1 Sample tested. 2 Guaranteed by CMRR test limits.
-2-
REV. A
OP221
SPECIFICATIONS -25 C T +85 C for OP221E, -40 C T +85 C for OP221G, unless otherwise noted.)
A A
.
(Electrical Characteristics at VS =
2.5 V to
15 V, -55 C TA +125 C for OP221A,
OP221A/E Parameter Average Input Offset Voltage Input Offset Voltage Symbol TCVOS VOS VCM = 0 VCM = 0 V+ = 5 V, V- = 0 V (Note 2) VS = 15 V V+ = -5 V, V- = 0 V 0 V VCM 3.5 V VS = 15 V -15 V VCM 13.5 V VS = 2.5 V to 15 V V- = 0 V, V+ = 5 V to 30 V VS = 15 V, RL = 10 k VO = 10 V V+ = 5 V, V- = 0 V RL = 10 k VS = 15 V, RL = 10 k VS = 2.5 V, No Load VS = 15 V, No Load 1000 0.8/3.8 13.5 500 700 650 900 0/3.2 -15/13.2 85 90 90 95 6 10 18 32 600 IB IVR CMRR Conditions Min Typ 0.75 150 1 55 Max 1.5 300 5 100 Min
OP221G Typ 2 400 2 80 0/3.2 -15/13.2 70 75 80 dB 85 57 100 180 320 V/V V/mV V 13.2 600 950 750 1000 A Max 3 700 10 140 Unit V/C V nA nA V
Input Offset Current IOS Input Bias Current Input Voltage Range Common-Mode Rejection Ratio
Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Supply Current (Both Amplifiers)
PSRR AVO VO
0.9/3.7
ISY
NOTES 1 Sample tested. 2 Guaranteed by CMRR test limits.
Matching Characteristics at Vs =
.
15 V, TA = 25 C, unless otherwise noted.
OP221A/E OP221G Max 200 80 2 5 4 Min Typ 250 Max 600 120 10 Unit V nA nA Conditions Min Typ 50
Parameter Input Offset Voltage Match
Symbol VOS
Average Noninverting Bias Current IB + Noninverting Input Offset Current Common-Mode Rejection Ratio Match (Note 1) Power Supply Rejection Ratio Match (Note 1) IOS+
CMRR VCM = -15 V to 13.5 V
92
72
dB
PSRR
VS = 2.5 V to 15 V
14
140
V/V
REV. A
-3-
C OP221A, OP221-SPECIFICATIONS (Matching Characteristics at V = 15V,T-55+85 TC for+125 C forunless otherwise noted. -25 C T +85 C for OP221E, -40 C OP221G,
s A A A
Grades E and G are sample tested.)
.
OP221A/E Parameter Input Offset Voltage Match Symbol VOS VCM = 0 1 VCM = 0 3 Conditions Min Typ 100 Max 400 100 2 7 Min
OP221G Typ 400 Max 800 140 3 6 5 12 Unit V nA VC nA
Average Noninverting IB+ Bias Current Input Offset Voltage Tracking Noninverting Input Offset Current Common-Mode Rejection Ratio Match (Note 1) Power Supply Rejection Ratio Match (Note 1) ICVOS IOS+
CMRR VCM = -15 V to 13.2 V
87
90
72
80
dB
PSRR
26
140
V/V
NOTES 1 CMRR is 20 log10 VCM/CME, where VCM is the voltage applied to both noninverting inputs and CME is the difference in common-mode input-referred error. 2 PSRR is: Input-Referred Differential Error VS
Wafer Test Limits at Vs =
.
2.5 V to
15 V, TA = 25 C, unless otherwise noted.
Conditions OP221N Limit 200 VCM = 0 VCM = 0 V+ = 5 V, V- = 0 V VS= 15 V V- = 0 V, V+ = 5 V, 0 V VCM 3.5 V VS = 15 V -15 V VCM 13.5 V VS = 2.5 V to 15 V V- = 0 V, V+ = 5 V to 30 V VS = 15 V RL = 10 k V+ = 5 V, V- = 0 V, RL= 10 k VS = 15 V, RL = 10 k VS = 2.5 V, No Load VS = 15 V, No Load 3.5 85 0/3.5 -15/13.5 88 dB Min 93 12.5 22.5 1500 0.7/4.1 13.8 560 810 V/mV Min V/mV Max V Min/Max V Min A Max Unit V Max nA Max nA Max V Min/Max V Min
Parameter Input Offset Voltage Input Offset Current Input Bias Current Input Voltage Range Common-Mode Rejection Ratio
Symbol VOS IOS IB IVR CMRR
Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Supply Current (Both Amplifiers)
PSRR Avo VO ISY
NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
-4-
REV. A
OP221
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential Input Voltage . . . . . . . . . . 30 V or Supply Voltage Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range OP221A . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C OP221E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C OP221G . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . . 300C Junction Temperature (TJ) . . . . . . . . . . . . . -65C to +150C
Package Type 8-Lead Hermetic DIP (Z) 8-Lead Plastic DIP (P) 8-Lead SO (S)
JA
(Note 2)
JC
Unit C/W C/W C/W
148 103 158
16 43 43
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for TO, Cerdip, and PDIP packages; elA is specified for device soldered to printed circuit board for SO package.
ORDERING INFORMATION 1,2
TA = +25 C VOS MAX ( V) 150 150 300 500 500 500
1
Cerdip 8-Lead
Packages Plastic 8-Lead
Operating Temperature Range MIL IND
Package Options Q-8
OP221AZ3 OP221 EZ3 OP221GP3 OP221GS
XIND XIND
R-8
Burn-in is available on commercial and industrial temperature range parts in CerDIP, plastic DIP, and TO-can packages. For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. Not for new design, obsolete April 2002.
2
3
Figure 1. Dice Characteristics
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP221 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-5-
Typical Perfomance Characteristics - OP221
140 dc 120 OPEN-LOOP GAIN - dB OPEN-LOOP GAIN - dB 100 80 60 40 VS = 20 0 -50 15V
20 0 -50 120 140 dc
140 120
OPEN-LOOP GAIN - dB 10Hz 100Hz
10Hz 100Hz 1kHz
100 80 60 40 VS =
100 80 60 40 20 0 0 5 10
TA = 25 C RL = 15k
1kHz
15V
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
15
TEMPERATURE - C
TEMPERATURE - C
SUPPLY VOLTAGE - V
TPC 1. Open-Loop Gain at 15 V vs. Temperature
TPC 2. Open-Loop Gain at 5 V vs. Temperature
70
TPC 3. Open-Loop Gain at vs. Supply Voltage
25 20
VOLTAGE GAIN - dB
80 TA = 25 C VS = 15V 100 120 m = 42 140 160 GAIN PHASE 180 200 220 1M FREQUENCY - Hz 10M
PHASE SHIFT - Degrees
120
60
OPEN-LOOP GAIN - dB
100 80 VS = 60 VS = 40 20 0 5V 15V
CLOSED-LOOP GAIN - dB
50 40 30 20 10 0 -10
15 10 5 0 -5 -10 100k
0.1
1
10
100 1k 10k 100k 1M 10M FREQUENCY - Hz
1
10
100
1k
10k
100k
1M 10M
FREQUENCY - Hz
TPC 4. Open-Loop Gain at 15 V vs. Frequency
55 50 45 40 GAIN BANDWIDTH VS = PHASE MARGIN 850k 800k 750k 700k 650k SLEW RATE - V/ sec 0.35 0.30 0.25 0.20 -50 -25 0 25 50 75 100 125 SLEW RATE 15V
TPC 5. Closed-Loop Gain vs. Frequency
120 GAIN BANDWIDTH - Hz
TPC 6. Gain and Phase Shift vs. Frequency
120 TA = 25 C VS = 15V
PHASE MARGIN - Degrees
100
+PSRR
100
80 PSRR - dB CMRR - Hz
80
60 -PSRR 40 TA = 25 C VS = 15V 100 1k 10k FREQUENCY - Hz 100k
60
40
20 0 10
20 0 1 10 100 1k 10k 100k FREQUENCY - Hz
TEMPERATURE - C
TPC 7. Phase Margin, Gain Bandwidth, and Slew Rate vs. Temperature
TPC 8. PSRR vs. Frequency
TPC 9. CMRR vs. Frequency
-6-
REV. A
OP221
30
16
PEAK-TO-PEAK AMPLITUTDE - V
28 24 20 16 12 8 4 0 1K 10k 100k FREQUENCY - Hz
MAXIMUM OUTPUT - V
POSITIVE 10 NEGATIVE 8 6 4 2 0 100
MAXIMUM OUTPUT - V
TA = 25 C VS = 15V RL = 10k
14 12
TA = 25 C VS = 15V
2.0
TA = 25 C VS = 2.5V
NEGATIVE POSITIVE
1.0
1M
1k 10k LOAD RESISTANCE -
100k
0 100
1k
10k
100k
LOAD RESISTANCE -
TPC 10. Maximum Output Swing vs. Frequency
100 80 70 60 50 40 30
TPC 11. Maximum Output Voltage vs. Load Resistance
10
TPC 12. Maximum Output Voltage vs. Load Resistance
VOLTAGE NOISE - nV/ Hz
CURRENT NOISE - pA Hz
1.0
20
10 1 10 100 1k FREQUENCY - Hz
0.1 1 10 100 1k FREQUENCY - Hz
TPC 13. Voltage Noise Density vs. Frequency
TPC 13. Current Noise Density vs. Frequency
REV. A
-7-
OP221
Figure 2a. Noninverting Step Response
Figure 3a. Inverting Step Response
Figure 2b. Noninverting Step Response
Figure 3b. Inverting Step Response
INPUT OUTPUT 10k
10k INPUT 10k OUTPUT
Figure 4. TBD.
Figure 5. TBD.
-8-
REV. A
OP221
SPECIAL NOTES ON THE APPLICATION OF DUAL MATCHED OPERATIONAL AMPLIFIERS Advantages of Dual Monolithic Operational Amplifiers INSTRUMENTATION AMPLIFIER APPLICATIONS Two-Op Amp Configuration
Dual matched operational amplifiers provide the engineer with a powerful tool for designing instrumentation amplifiers and many other differential-input circuits. These designs are based on the principle that careful matching between two operational amplifiers can minimize the effect of dc errors in the individual amplifiers. Reference to the circuit shown in Figure 6, a differential-in, differential-out amplifier, shows how the reductions in error can be accomplished. Assuming the resistors used are ideally matched, the gain of each side will be identical. If the offset voltages of each amplifier are perfectly matched, then the net differential voltage at the amplifier's output will be zero. Note that the output offset error of this amplifier is not a function of the offset voltage of the individual amplifiers, but only a function of the difference (degree of matching) between the amplifiers' offset voltages. This error-cancellation principle holds for a considerable number of input referred error parameters--offset voltage, offset voltage drift, inverting and noninverting bias currents, common mode and power supply rejection ratios. Note also that the impedances of each input, both common-mode and differential-mode, are high and tightly matched, an important feature not practical with single operation amplifier circuits.
The two-op amp circuit (Figure 7) is recommended where the common-mode input voltage range is relatively limited; the common-mode and differential voltage both appear at V1. The high open-loop gain of the OP221 is very important in achieving good CMRR in this configuration. Finite open-loop gain of A1 (Ao1) causes undesired feedthrough of the common-mode input. For Ad/Ao, << 1, the common-mode error (CME) at the output due to this effect is approximately (2 Ad/Ao1) x VCM. This circuit features independent adjustment of CMRR and differential gain.
Three-Op Amp Configuration
The three-op amp circuit (Figure 8) has increased commonmode voltage range because the common-mode voltage is not amplified as it is in Figure 7. The CMR of this amplifier is directly proportional to the match of the CMR of the input op amps. CMRR can be raised even further by trimming the output stage resistors.
R0 GAIN ADJ R1 R2 1/2 AD = 2 1+ R1 R0 V1 R3 R4 1/2
OP221
VCM - 1/2VD A1
R3
- Vd
OP221
A2 VO - ADVD
R1 + INPUT - R2 SIDE `R' - SIDE `A' +
+ VCM + 1/2VD R4 VO = R3 1+1 2 R2 + R3 R1 R4 + R2 + R3 R0
OP221
OUTPUT
Vd + R4 R3
R3 - R2 R4 R1
VCM
IF R1 = R2 = R3 = R4, THEN VO = 2 1 + R1 VD R0
Figure 7. Two-Op Amp Circuit
R4
R1
Figure 6. Differential-In, Differential-Out Amplifier
VCM - 1/2VD - R0 Vd A1 1/2 V1
VO = 2 1 + R2
2R1 R0
VD
R2 V+
OP221
R1 V+ R2 A2 1/2 V-
OP221
A3 VO
- VCM + 1/2VD
V2 R2
V-
OP221
Figure 8. Three-Op Amp Circuit
REV. A
-9-
OP221
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead CERDIP Package (Q-8)
0.055 (1.4) MAX
5
0.005 (0.13) MIN
8
PIN 1
1 4
0.310 (7.87) 0.220 (5.59)
0.100 (2.54) BSC 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 15 0 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37)
SEATING 0.023 (0.58) 0.070 (1.78) PLANE 0.014 (0.36) 0.030 (0.76)
8-Lead SOIC Package (R-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.102 (2.59) 0.094 (2.39) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
-10-
REV. A
OP221 Revision History
Location 09/01--Data Sheet changed from REV. 0 to REV. A. Page
Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Global deletion of references to OP221B and OP221C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 4 Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. A
-11-
-12-
C00324-0-1/02(A)
PRINTED IN U.S.A.

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