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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P3116
4-BIT SINGLE-CHIP MICROCONTROLLER
The PD75P3116 replaces the PD753108's internal mask ROM with a one-time PROM, and features expanded ROM capacity. Because the PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the development stage using the PD753104, 753106, or 753108, and for use in small-scale production. Detailed information about functions is provided in the following User's Manual. Be sure to read it before designing:
PD753108 User's Manual : U10890E
FEATURES
Compatible with PD753108 Memory capacity: * PROM : 16384 x 8 bits * RAM : 512 x 4 bits Can be operated in same power supply voltage range as the mask version PD753108 * VDD = 1.8 to 5.5 V On-chip LCD controller/driver QTOPTM microcontroller Remark QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC. The support include writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part Number Package 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
PD75P3116GC-AB8 PD75P3116GK-8A8
Caution This device does not provide an internal pull-up resistor connection function by means of mask option.
The information in this document is subject to change without notice.
Document No. U11369EJ2V0DS00 (2nd edition) Date Published March 1997 N Printed in Japan
The mark
shows major revised points.
(c)
1994
PD75P3116
FUNCTION OUTLINE
Item Instruction execution time Function * 0.95, 1.91, 3.81, or 15.3 s (main system clock: @ 4.19 MHz) * 0.67, 1.33, 2.67, or 10.7 s (main system clock: @ 6.0 MHz) * 122 s (subsystem clock: @ 32.768 kHz) 16384 x 8 bits 512 x 4 bits * 4-bit manipulation: 8 x 4 banks * 8-bit manipulation: 4 x 4 banks 8 20 4 32 * Segment number selection : 16/20/24 segments (Switchable to CMOS I/O ports in a batch of 4 pins, max. 8 pins) * Display mode selection : static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) 5 channels: * 8-bit timer/event counter : 3 channels (Can be used as 16-bit timer/event counter, carrier generator, and timer with gate) * Basic interval timer/watchdog timer : 1 channel * Watch timer : 1 channel * 3-wire serial I/O mode *** MSB/LSB first switchable * 2-wire serial I/O mode * SBI mode 16 bits , 524, 262, and 65.5 kHz (main system clock: @ 4.19 MHz) , 750, 375, and 93.8 kHz (main system clock: @ 6.0 MHz) * 2, 4, and 32 kHz (main system clock: @ 4.19 MHz or subsystem clock: @ 32.768 kHz) * 2.93, 5.86, 46.9 kHz (main system clock: @ 6.0 MHz) * External : 3 * Internal : 5 * External : 1 * Internal : 1 * Ceramic/crystal oscillation circuit for main system clock * Crystal oscillation circuit for subsystem clock STOP/HALT mode VDD = 1.8 to 5.5 V * 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) * 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) Internal pull-up resistor connection can be specified by software: 7 Internal pull-up resistor connection can be specified by software: 12 Shared by segment pin: 8 13-V withstand voltage
Internal memory
PROM RAM
General-purpose register I/O ports CMOS input CMOS I/O N-ch open-drain I/O Total LCD controller/driver
Timers
Serial interface
Bit sequential buffer (BSB) Clock output (PCL) Buzzer output (BUZ) Vectored interrupts Test inputs System clock oscillation circuit Standby function Power supply voltage Package
2
PD75P3116
CONTENTS
1. PIN CONFIGURATION (Top View) .................................................................................................. 2. BLOCK DIAGRAM ............................................................................................................................ 3. PIN FUNCTIONS ...............................................................................................................................
3.1 3.2 3.3 3.4 Port Pins ................................................................................................................................................... Non-port Pins ...........................................................................................................................................
4 5 6
6 8
Equivalent Circuits for Pins .................................................................................................................... 10 Recommended Connection of Unused Pins ......................................................................................... 12
4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................. 13
4.1 4.2 Differences between Mk I Mode and Mk II Mode ................................................................................... 13 Setting of Stack Bank Selection (SBS) Register ................................................................................... 14
5. DIFFERENCES BETWEEN PD75P3116 AND PD753104, 753106, AND 753108 ...................... 15 6. MEMORY CONFIGURATION ........................................................................................................... 16 7. INSTRUCTION SET .......................................................................................................................... 18 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 27
8.1 8.2 8.3 8.4 Operation Modes for Program Memory Write/Verify ............................................................................ 27 Program Memory Write Procedure ......................................................................................................... 28 Program Memory Read Procedure ......................................................................................................... 29 One-time PROM Screening ..................................................................................................................... 30
9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 31 10. CHARACTERISTIC CURVES (REFERENCE VALUES) .................................................................. 46 11. PACKAGE DRAWINGS ................................................................................................................... 48 12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50 APPENDIX A. FUNCTION LIST OF PD75308B, 753108, AND 75P3116 ........................................... 51 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 53 APPENDIX C. RELATED DOCUMENTS ............................................................................................... 57
3
PD75P3116
1. PIN CONFIGURATION (Top View)
* 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) : PD75P3116GC-AB8 * 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) : PD75P3116GK-8A8
COM3 COM2 COM1 COM0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BIAS VLC0 VLC1 VLC2 P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2 P33/MD3 Vss P50/D4 P51/D5 P52/D6 P53/D7 P60/KR0/D0 P61/KR1/D1 P62/KR2/D2
S12 S13 S14 S15 P93/S16 P92/S17 P91/S18 P90/S19 P83/S20 P82/S21 P81/S22 P80/S23 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0
Note
Always connect the VPP pin directly to VDD during normal operation.
PIN IDENTIFICATIONS
P00-P03 P10-P13 P20-P23 P30-P33 P50-P53 P60-P63 P80-P83 P90-P93 KR0-KR3 SCK SI SO SB0, SB1 RESET MD0 to MD3 D0 to D7 S0 to S23 : Port0 : Port1 : Port2 : Port3 : Port5 : Port6 : Port8 : Port9 : Key Return 0 to 3 : Serial Clock : Serial Input : Serial Output : Serial Data Bus 0, 1 : Reset : Mode Selection 0 to 3 : Data Bus 0 to 7 : Segment Output 0 to 23 COM0 to COM3 : Common Output 0 to 3 VLC0 to VLC2 BIAS LCDCL SYNC TI0 to TI2 PTO0 to PTO2 BUZ PCL INT0, 1, 4 INT2 X1, X2 XT1, XT2 VPP VDD Vss : LCD Power Supply 0 to 2 : LCD Power Supply Bias Control : LCD Clock : LCD Synchronization : Timer Input 0 to 2 : Programmable Timer Output 0 to 2 : Buzzer Clock : Programmable Clock : External Vectored Interrupt 0, 1, 4 : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : Programming Power Supply : Positive Power Supply : Ground
4
P63/KR3/D3 RESET XT1 XT2 VPP Note X1 X2 VDD P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 P11/INT1 P12/INT2/TI1/TI2 P13/TI0
PD75P3116
2. BLOCK DIAGRAM
BUZ/P23
WATCH TIMER INTW fLCD BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT PROGRAM COUNTER (14) ALU SP (8) CY SBS
PORT0
4
P00 to P03
PORT1
4
P10 to P13
PORT2
4
P20 to P23 P30/MD0 to P33/MD3 P50/D4 to P53/D7 P60/D0 to P63/D3 P80 to P83
BANK PORT3 4
TI0/P13 PTO0/P20
8-BIT TIMER/EVENT COUNTER #0 GENERAL REG. PROGRAM MEMORY (PROM) 16384 x 8 BITS
PORT5
4
TI1/TI2/ P12/INT2 PTO1/P21 PTO2/ PCL/P22 TOUT0
INTT0 TOUT0 INTT1 8-BIT CASCADED TIMER/EVENT 16-BIT COUNTER #1 TIMER/ EVENT 8-BIT TIMER/EVENT COUNTER COUNTER #2 INTT2 CLOCKED SERIAL INTERFACE INTCSI TOUT0 INT1 INTERRUPT CONTROL 4 BIT SEQ. BUFFER (16)
PORT6
4
DECODE AND CONTROL
PORT8 DATA MEMORY (RAM) 512 x 4 BITS
4
PORT9
4
P90 to P93
SI/SB1/P03 SO/SB0/P02 SCK/P01
16
S0 to S15 S16/P93 to S19/P90 S20/P83 to S23/P80 COM0 to COM3 BIAS VLC0 VLC1 VLC2 SYNC/P31 LCDCL/P30
4
LCD CONTROLLER/ DRIVER
INT0/P10 INT1/P11 INT4/P00 INT2/P12/TI1/TI2 P60/KR0 to P63/KR3
4
fx/2 N
CPU CLOCK fLCD
4
SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER CONTROL CONTROL MAIN SUB
PCL/PTO2/P22
X1 X2 XT1 XT2
VDD Vss VPP RESET
5
PD75P3116
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P50 Note 2 P51 Note 2 P52 Note 2 P53 Note 2 I/O I/O I/O I/O Input I/O I/O I/O Input Alternate function INT4 SCK SO/SB0 SI/SB1 INT0 INT1 TI1/TI2/INT2 TI0 PTO0 PTO1 PCL/PTO2 BUZ LCDCL/MD0 SYNC/MD1 MD2 MD3 D4 D5 D6 D7 N-ch open-drain 4-bit I/O port (PORT5) When set to open-drain, voltage is 13 V. X High impedance M-E Programmable 4-bit I/O port (PORT3) Input and output in single-bit units can be specified. When set for 4-bit units, connection of an internal pull-up resistor can be specified by software. X Input E-B 4-bit I/O port (PORT2) Connection of an internal pull-up resistor can be specified by software in 4-bit units. X Input E-B 4-bit input port (PORT1) Connection of an internal pull-up resistor can be specified by software in 4-bit units. P10/INT0 can select noise elimination circuit. X Input Function 4-bit input port (PORT0) P01 to P03 are 3-bit pins for which connection of an internal pull-up resistor can be specified by software. 8-bit I/O X Status after reset Input I/O circuit typeNote 1 -A -B -C -C
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.
6
PD75P3116
3.1 Port Pins (2/2)
Pin name P60 P61 P62 P63 P80 P81 P82 P83 P90 P91 P92 P93 I/O I/O I/O I/O Alternate function KR0/D0 KR1/D1 KR2/D2 KR3/D3 S23 S22 S21 S20 S19 S18 S17 S16 Programmable 4-bit I/O port (PORT9) When set for 4-bit units, connection of an internal pull-up resistor can be specified by softwareNote 3. Input H 4-bit I/O port (PORT8) When set for 4-bit units, connection of an internal pull-up resistor can be specified by softwareNote 3. Input H Function Programmable 4-bit I/O port (PORT6) Input and output in single-bit units can be specified. When set for 4-bit units, connection of an internal pull-up resistor can be specified by software. 8-bit I/O X Status after reset Input I/O circuit type Note 1 -A
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. Low-level leak current increases when an input instruction or a bit manipulation instruction is performed. 3. Do not connect an internal pull-up resistor by software when used as the segment signal output.
7
PD75P3116
3.2 Non-port Pins (1/2)
Pin name TI0 TI1 TI2 PTO0 PTO1 PTO2 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 INT1 INT2 KR0 to KR3 X1 X2 XT1 XT2 RESET MD0 to MD3 D0 to D3 D4 to D7 VPP
Note 2
I/O Input
Alternate function P13 P12/INT2/TI2 P12/INT2/TI1
Function External event pulse input to timer/event counter
Status after reset Input
I/O circuit typeNote 1 -C
Output
P20 P21 P22/PCL P22/PTO2 P23
Timer/event counter output
Input
E-B
Clock output Frequency output (for buzzer or system clock trimming) Serial clock I/O Serial data output Serial data bus I/O Serial data input Serial data bus I/O Edge detection vectored interrupt input (valid for detecting both rising and falling edges) Edge detection vectored interrupt input With noise elimination (detection edge is selectable) circuit/asynch is selectable INT0/P10 can select noise elimination circuit. Asynch Rising edge detection testable input Asynch Input -- -A -- Input Input -A -B -C -C
I/O
P01 P02 P03
Input Input
P00 P10 P11
Input I/O Input -- Input -- Input Input I/O
P12/TI1/TI2 P60 to P63 --
Parallel falling edge detection testable input Ceramic/crystal resonator connection for main system clock oscillation. If using an external clock, input signal to X1 and input inverted phase to X2. Crystal resonator connection for subsystem clock oscillation. If using an external clock, input signal to XT1 and input inverted phase to XT2. XT1 can be used as a 1-bit (test) input. System reset input (low-level active) Mode selection for program memory (PROM) write/verify
--
--
--
-- P30 to P33
-- Input Input
E-B -A M-E
P60/KR0 to P63/KR3 Data bus for program memory (PROM) write/verify P50 to P53
--
--
Programmable power supply voltage applied for program memory (PROM) write/verify. For normal operation, connect directly to VDD. Apply +12.5 V for PROM write/verify. Positive power supply Ground potential
--
--
VDD Vss
-- --
-- --
-- --
-- --
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. The VPP pin does not operate correctly when it is not connected to the VDD pin during normal operation.
8
PD75P3116
3.2 Non-port Pins (2/2)
Pin name S0 to S15 S16 to S19 S20 to S23 I/O Output Output Output Alternate function -- P93 to P90 P83 to P80 -- -- -- P30/MD0 P31/MD1 Segment signal output Segment signal output Segment signal output Common signal output Power supply for driving LCD Output for external split resistor cut Clock output for driving external expansion driver Clock output for synchronization of external expansion driver Function Status after reset Note 1 Input Input Note 1 -- Note 2 Input Input I/O circuit type G-A H H G-B -- -- E-B E-B
COM0 to COM3 Output VLC0 to VLC2 BIAS LCDCL Note 3 SYNC
Note 3
-- Output I/O I/O
Notes 1. The VPP pin does not operate normally if it is not connected with VDD pin when normal operation. 2. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs. S0 to S23: VLC1, COM0 to COM2: VLC2, COM3: VLC0 3. When the split resistor is incorporated : Low level When the split resistor is not incorporated : High impedance 4. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
9
PD75P3116
3.3 Equivalent Circuits for Pins The equivalent circuits for the PD75P3116's pins are shown in abbreviated form below.
TYPE A VDD Data P-ch IN Output disable N-ch TYPE D VDD P-ch OUT
N-ch
CMOS standard input buffer
Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable P-ch
TYPE B
IN Data Type D Output disable IN/OUT
Type A Schmitt trigger input with hysteresis characteristics. P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable Data Type D Output disable IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor P.U.R. P-ch
P-ch
IN/OUT
(Continued)
10
PD75P3116
(Continued)
TYPE F-B VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch Data Output disable Type E-B VDD P-ch IN/OUT P-ch SEG data Type G-A P-ch N-ch IN/OUT TYPE H
P.U.R. : Pull-Up Resistor TYPE G-A P-ch N-ch P-ch N-ch P-ch N-ch P.U.R. enable TYPE M-C VDD VLC0 P.U.R. P-ch IN/OUT OUT SEG data VLC2 P-ch N-ch N-ch P.U.R. : Pull-Up Resistor N-ch Data Output disable N-ch
VLC1
TYPE G-B P-ch N-ch P-ch N-ch P-ch N-ch
TYPE M-E IN/OUT Data Output disable VDD Input instruction P-ch P.U.R.
Note
VLC0 VLC1
N-ch (+13-V withstand voltage)
OUT COM data N-ch P-ch VLC2 N-ch P-ch N-ch
Voltage controller
(+13-V withstand voltage)
Note Pull-up resistor that operates only when an input instruction is executed. (The current flows from VDD to a pin when the pin is at low level.)
11
PD75P3116
3.4 Recommended Connection of Unused Pins Table 3-1. List of Unused Pin Connection
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 and P11/INT1 P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL P23/BUZ P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2 P33/MD3 P50/D4 to P53/D7 P60/KR0/D0 to P63/KR3/D3 S0 to S15 COM0 to COM3 S16/P93 to S19/P90 S20/P83 to S23/P80 VLC0 to VLC2 BIAS XT1 Note XT2 Note VPP Input status : Individually connect to Vss or VDD through a resistor Connect to Vss Input status : Individually connect to Vss or VDD through a resistor Output status : Leave open Leave open Input status : Individually connect to Vss or VDD through a resistor Output status : Leave open Connect to Vss Connect to Vss or VDD Recommended connection Connect to Vss or VDD Individually connect to Vss or VDD through a resistor.
Output status : Leave open Connect to Vss Connect to Vss only when neither of VLC0, VLC1 and VLC2 is used. In other cases, leave open. Connect to Vss or VDD Leave open Always connect to VDD directly
Note In case the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback resistor not used).
12
PD75P3116
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting a stack bank selection (SBS) register for the PD75P3116 enables the program memory to be switched between the Mk I mode and Mk II mode. This function is applicable when using the PD75P3116 to evaluate the PD753104, 753106, or 753108. When the SBS bit 3 is set to 1 : sets the Mk I mode (supports the Mk I mode for the PD753104, 753106, and 753108) When the SBS bit 3 is set to 0 : sets the Mk II mode (supports the Mk II mode for the PD753104, 753106, and 753108) 4.1 Differences between Mk I Mode and Mk II Mode Table 4-1 lists differences between the Mk I mode and the Mk II mode for the PD75P3116. Table 4-1. Differences between Mk I Mode and Mk II Mode
Item Program counter Program memory (bytes) Data memory (bits) Stack Stack bank No. of stack bytes Instruction BRA !addr1 instruction CALLA !addr1 instruction Instruction CALL !addr instruction 3 machine cycles 2 machine cycles When set to Mk I mode: PD753104, 753106, and 753108 4 machine cycles 3 machine cycles When set to Mk II mode: PD753104, 753106, and 753108 PC13-0 16384 512 x 4 Selectable via memory banks 0, 1 2 bytes Not available 3 bytes Available Mk I mode Mk II mode
execution time CALLF !faddr instruction Supported mask ROMs
Caution
The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. With regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used.
13
PD75P3116
4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format of the stack bank selection register. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 100XB Note at the beginning of the program. When using the Mk II mode, be sure to initialize it to 000XB Note. Note Set the desired value for X. Figure 4-1. Format of Stack Bank Selection Register
Address F84H
3 SBS3
2 SBS2
1 SBS1
0 SBS0
Symbol SBS
Stack area specification
0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Setting prohibited
0
Be sure to enter "0" for bit 2.
Mode selection specification
0 1 Mk II mode Mk I mode
Caution
SBS3 is set to "1" after RESET input, and consequently the CPU operates in the Mk I mode. When using instructions for the Mk II mode, set SBS3 to "0" and set the Mk II mode before using the instructions.
14
PD75P3116
5. DIFFERENCES BETWEEN PD75P3116 AND PD753104, 753106, 753108
The PD75P3116 replaces the internal mask ROM in the PD753104, 753106, and 753108 with a one-time PROM and features expanded ROM capacity. The PD75P3116's Mk I mode supports the Mk I mode in the PD753104, 753106, and 753108 and the PD75P3116's Mk II mode supports the Mk II mode in the PD753104, 753106, and 753108. Table 5-1 lists differences among the PD75P3116 and the PD753104, 753106, and 753108. Be sure to check the differences among these products before using them with PROMs for debugging or prototype testing of application systems or, later, when using them with a mask ROM for full-scale production. For details on the CPU functions and internal hardware, refer to the User's Manual. Table 5-1. Differences between PD75P3116 and PD753104, 753106, and 753108
Item Program counter Program memory (bytes) Data memory (x 4 bits) Mask options Pull-up resistor for PORT5 Split resistor for LCD driving power supply Wait time after RESET Feedback resistor of subsystem clock Pin configuration Pin Nos. 5 to 8 Pin Nos. 10 to 13 Pin Nos. 14 to 17 Pin No. 21 Other Available (Selectable between 217/fX and 215/fX) Available (Use/not use can be selected.) P30 to P33 P50 to P53 P60/KR0 to P63/KR3 IC Not available (fixed to 215/fX) Note Not available (Enable) P30/MD0 to P33/MD3 P50/D4 to P53/D7 P60/KR0/D0 to P63/KR3/D3 VPP
PD753104
12 bits Mask ROM 4096 512
PD753106
13 bits Mask ROM 6144
PD753108
PD75P3116
14 bits
Mask ROM 8192
One-time PROM 16384
Available (On chip/not on chip can be specified.)
Not available (Not on chip)
Noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts.
Note
217/fX : 21.8 ms at 6.0-MHz operation, 31.3 ms at 4.19-MHz operation 215/fX : 5.46 ms at 6.0-MHz operation, 7.81 ms at 4.19-MHz operation
Caution Noise resistance and noise radiation are different in PROM and mask ROMs. When changing from PROM versions to mask ROM versions when switching from prototype development to full production, be sure to fully evaluate the mask ROM version's CS (not ES).
15
PD75P3116
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
7 0000H MBE
6 RBE
5
0
Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) CALLF !faddr instruction entry address
0004H
MBE
RBE
INT0 start address (upper 6 bits) INT0 start address (lower 8 bits)
0006H
MBE
RBE
INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) BRCB !caddr instruction branch address Branch addresses for the following instructions * BR !addr * CALL !addr * BRA !addr1 Note * CALLA !addr1Note * BR BCDE * BR BCXA Branch/call address by GETI
0008H
MBE
RBE
INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits)
000AH
MBE
RBE
INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits)
000CH
MBE
RBE
INTT1/INTT2 start address (upper 6 bits) INTT1/INTT2 start address (lower 8 bits)
0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH
BR $addr instruction relative branch address (-15 to -1, +2 to +16)
BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Note Can be used only in the Mk II mode Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC's lower 8 bits only.
16
PD75P3116
Figure 6-2. Data Memory Map
Data memory 000H General-purpose register area 01FH 020H (32 x 4)
Memory bank
256 x 4 Stack area Note Data area static RAM (512 x 4) (224 x 4)
0
0FFH 100H 256 x 4 (224 x 4) 1DFH 1E0H Display data memory 1F7H 1F8H (8 x 4) 1FFH (24 x 4) 1
Not incorporated
F80H
Peripheral hardware area
128 x 4
15
FFFH
Note
Memory bank 0 or 1 can be selected as the stack area.
17
PD75P3116
7. INSTRUCTION SET
(1) Representation and coding formats for operands In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's operand representations (for further description, refer to the RA75X Assembler Package User's Manual Language (EEU-1363)). When there are several codes, select and use just one. Codes that consist of upper-case letters and + or - symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, refer to the User's Manual). The number of labels that can be entered for fmem and pmem are restricted.
Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label 0000H to 3FFFH immediate data or label 0000H to 3FFFH immediate data or label (Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (however, bit0 = 0) or label PORT0 to PORT3, PORT5, PORT6, PORT8, PORT9 IEBT, IECSI, IET0 to IET2, IE0 to IE2, IE4, IEW RB0 to RB3 MB0, MB1, MB15 Coding format
Note When processing 8-bit data, only even-numbered addresses can be specified.
18
PD75P3116
(2) Operation legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IEXXX RBS MBS PCC . (XX) XXH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Expansion register pair (XA') : Expansion register pair (BC') : Expansion register pair (DE') : Expansion register pair (HL') : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Delimiter for address and bit : Addressed data with xx : Hexadecimal data
PORTn : Port n (n = 0 to 3, 5, 6, 8, 9)
19
PD75P3116
(3) Description of symbols used in addressing area
MB = MBE * MBS *1 MBS = 0, 1, 15 *2 MB = 0 MBE = 0 *3 MBE = 1 : MB = MBS MBS = 0, 1, 15 *4 *5 *6 *7 (Current PC) +2 to (Current PC) +16 caddr = 0000H to 0FFFH (PC13, 12 = 00B) or 1000H to 1FFFH (PC13, 12 = 01B) or *8 2000H to 2FFFH (PC13, 12 = 10B) or 3000H to 3FFFH (PC13, 12 = 11B) *9 *10 *11 faddr = 0000H to 07FFH taddr = 0020H to 007FH addr1 = 0000H to 3FFFH (Mk II mode only) Program memory addressing MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 3FFFH addr, addr1 = (Current PC) -15 to (Current PC) -1 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) Data memory addressing
Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. (4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. * No skip ..................................................................... S = 0 * Skipped instruction is 1-byte or 2-byte instruction .... S = 1 * Skipped instruction is 3-byte instructionNote .............. S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock . Use the PCC setting to select among four cycle times.
20
PD75P3116
Instruction group Transfer
Mnemonic MOV
Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA
No. of Machine bytes cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 A<-n4 reg1<-n4 XA<-n8 HL<-n8 rp2<-n8 A<-(HL)
Operation
Addressing area
Skip condition String-effect A
String-effect A String-effect B
*1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L=FH
A<-(HL), then L<-L+1 A<-(HL), then L<-L-1 A<-(rpa1) XA<-(HL) (HL)<-A (HL)<-XA A<-(mem) XA<-(mem) (mem)<-A (mem)<-XA A<-reg XA<-rp' reg1<-A rp'1<-XA A<->(HL) A<->(HL), then L<-L+1 A<->(HL), then L<-L-1 A<->(rpa1) XA<->(HL) A<->(mem) XA<->(mem) A<->reg1 XA<->rp' XA<-(PC13-8+DE)ROM XA<-(PC13-8+XA)ROM XA<-(BCDE)ROM XA<-(BCXA)ROM
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
*1 *1 *1 *2 *1 *3 *3 L=0 L=FH
Table reference
MOVT
XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA
Note
1 1
*6 *6
Note
Note Only the lower 3 bits in the B register are valid.
21
PD75P3116
Instruction group Bit transfer
Mnemonic MOV1
Operand CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY
No. of Machine bytes cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S
Operation CY<-(fmem.bit) CY<-(pmem7-2+L3-2.bit(L1-0)) CY<-(H+mem3-0.bit) (fmem.bit)<-CY (pmem7-2+L3-2.bit(L1-0))<-CY (H+mem3-0.bit)<-CY A<-A+n4 XA<-XA+n8 A<-A+(HL) XA<-XA+rp' rp'1<-rp'1+XA A, CY<-A+(HL)+CY XA, CY<-XA+rp'+CY rp'1, CY<-rp'1+XA+CY A<-A-(HL) XA<-XA-rp' rp'1<-rp'1-XA A, CY<-A-(HL)-CY XA, CY<-XA-rp'-CY rp'1, CY<-rp'1-XA-CY A<-A ^ n4 A<-A ^ (HL) XA<-XA ^ rp' rp'1<-rp'1 ^ XA A<-A v n4 A<-A v (HL) XA<-XA v rp' rp'1<-rp'1 v XA A<-A v n4 A<-A v (HL) XA<-XA v rp' rp'1<-rp'1 v XA CY<-A0, A3<-CY, An-1<-An A<-A reg<-reg+1 rp1<-rp1+1 (HL)<-(HL)+1 (mem)<-(mem)+1 reg<-reg-1 rp'<-rp'-1
Addressing area *4 *5 *1 *4 *5 *1
Skip condition
Arithmetic
ADDS
A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA
carry carry *1 carry carry carry *1
ADDC
A, @HL XA, rp' rp'1, XA
SUBS
A, @HL XA, rp' rp'1, XA
*1
borrow borrow borrow
SUBC
A, @HL XA, rp' rp'1, XA
*1
AND
A, #n4 A, @HL XA, rp' rp'1, XA
*1
OR
A, #n4 A, @HL XA, rp' rp'1, XA
*1
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
*1
Accumulator manipulation Increment/ decrement
RORC NOT INCS
A A reg rp1 @HL mem
reg=0 rp1=00H *1 *3 (HL)=0 (mem)=0 reg=FH rp'=FFH
DECS
reg rp'
22
PD75P3116
Instruction group Comparison
Mnemonic SKE
Operand reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp'
No. of Machine bytes cycle 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Skip if reg=n4 Skip if (HL)=n4 Skip if A=(HL)
Operation
Addressing area
Skip condition reg=n4
*1 *1 *1
(HL)=n4 A=(HL) XA=(HL) A=reg XA=rp'
Skip if XA=(HL) Skip if A=reg Skip if XA=rp' CY<-1 CY<-0 Skip if CY=1 CY<-CY (mem.bit)<-1 (fmem.bit)<-1 (pmem7-2+L3-2.bit(L1-0))<-1 (H+mem3-0.bit)<-1 (mem.bit)<-0 (fmem.bit)<-0 (pmem7-2+L3-2.bit(L1-0))<-0 (H+mem3-0.bit)<-0 Skip if(mem.bit)=1 Skip if(fmem.bit)=1 Skip if(pmem7-2+L3-2.bit(L1-0))=1 Skip if(H+mem3-0.bit)=1 Skip if(mem.bit)=0 Skip if(fmem.bit)=0 Skip if(pmem7-2+L3-2.bit(L1-0))=0 Skip if(H+mem3-0.bit)=0 Skip if(fmem.bit)=1 and clear Skip if(pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if(H+mem3-0.bit)=1 and clear CY<-CY ^ (fmem.bit) CY<-CY ^ (pmem7-2+L3-2.bit(L1-0)) CY<-CY ^ (H+mem3-0.bit) CY<-CY v (fmem.bit) CY<-CY v (pmem7-2+L3-2.bit(L1-0)) CY<-CY v (H+mem3-0.bit) CY<-CY v (fmem.bit) CY<- CY v (pmem7-2+L3-2.bit(L1-0)) CY<-CY v (H+mem3-0.bit)
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit
CY=1
Memory bit manipulation
SET1
*3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR
fmem.bit pmem.@L @H+mem.bit
AND1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
OR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
XOR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
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PD75P3116
Instruction group Branch
Mnemonic BRNote 1
Operand addr
No. of Machine bytes cycle -- --
Operation PC13-0<-addr Use the assembler to select the most appropriate instruction among the following. * BR !addr * BRCB !caddr * BR $addr PC13-0<-addr1 Use the assembler to select the most appropriate instruction among the following. * BRA !addr1 * BR !addr * BRCB !caddr * BR $addr1 PC13-0<-addr PC13-0<-addr PC13-0<-addr1 PC13-0<-PC13-8+DE PC13-0<-PC13-8+XA PC13-0<-BCDENote 2 PC13-0<-BCXA PC13-0<-addr1 PC13-0<-PC13, 12+caddr11-0
Note 2
Addressing area *6
Skip condition
addr1
--
--
*11
!addr $addr $addr1 PCDE PCXA BCDE BCXA BRA
Note 1
3 1 1 2 2 2 2 3 2
3 2 2 3 3 3 3 3 2
*6 *7
*6 *6 *11 *8
!addr1 !caddr
BRCB
Notes 1. The portion in a double box can be supported only in the Mk II mode. The others can be supported only in the MK I mode. 2. The B register is valid only for the lower two bits.
24
PD75P3116
Instruction group Subroutine stack control
Mnemonic
Operand
No. of Machine bytes cycle 3 3
Operation
Addressing area *11
Skip condition
CALLANote !addr1
(SP-6)(SP-3)(SP-4)<-PC11-0 (SP-5)<-0, 0, PC13, 12 (SP-2)<-X, X, MBE, RBE PC13-0<-addr1, SP<-SP-6
CALL
Note
!addr
3
3
(SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12 PC13-0<-addr, SP<-SP-4
*6
4
(SP-6)(SP-3)(SP-4)<-PC11-0 (SP-5)<-0, 0, PC13, 12 (SP-2)<-X, X, MBE, RBE PC13-0<-addr, SP<-SP-6
CALLFNote
!faddr
2
2
(SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12 PC13-0<-000+faddr, SP<-SP-4
*9
3
(SP-6)(SP-3)(SP-4)<-PC11-0 (SP-5)<-0, 0, PC13, 12 (SP-2)<-X, X, MBE, RBE PC13-0<-000+faddr, SP<-SP-6
RET
Note
1
3
MBE, RBE, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) SP<-SP+4 X, X, MBE, RBE<-(SP+4) PC11-0<-(SP)(SP+3)(SP+2) 0, 0, PC13, 12<-(SP+1) SP<-SP+6
RETS
Note
1
3+S
MBE, RBE, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) SP<-SP+4 then skip unconditionally X, X, MBE, RBE<-(SP+4) PC11-0<-(SP)(SP+3)(SP+2) 0, 0, PC13, 12<-(SP+1) SP<-SP+6 then skip unconditionally
Unconditional
RETI Note
1
3
MBE, RBE, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) PSW<-(SP+4)(SP+5) SP<-SP+6 0, 0, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) PSW<-(SP+4)(SP+5), SP<-SP+6
Note The portion in a double box can be supported only in the Mk II mode. Other portions can be supported only in the Mk I mode.
25
PD75P3116
Instruction group Subroutine stack control
Mnemonic PUSH rp BS POP rp BS
Operand
No. of Machine bytes cycle 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3
Operation (SP-1)(SP-2)<-rp, SP<-SP-2 (SP-1)<-MBS, (SP-2)<-RBS, SP<-SP-2 rp<-(SP+1)(SP), SP<-SP+2 MBS<-(SP+1), RBS<-(SP), SP<-SP+2 IME(IPS.3)<-1 IEXXX<-1 IME(IPS.3)<-0 IEXXX<-0 A<-PORTn (n=0 to 3, 5, 6, 8, 9) XA<-PORTn+1, PORTn (n=8) PORTn<-A (n=2 to 3, 5, 6, 8, 9) PORTn+1, PORTn<-XA (n=8) Set HALT Mode(PCC.2<-1) Set STOP Mode(PCC.3<-1) No Operation RBS<-n (n=0 to 3) MBS<-n (n=0, 1, 15) * When using TBR instruction PC13-0<-(taddr)5-0+(taddr+1)
Addressing area
Skip condition
Interrupt control
EI IEXXX DI IEXXX
2 2 2 2 2 2 2 2 2 1
I/O
IN
Note 1
A, PORTn XA, PORTn
OUT Note 1
PORTn, A PORTn, XA
CPU control
HALT STOP NOP
Special
SEL
RBn MBn
2 2 1
GETI
Note 2, 3
taddr
*10
--------------------------* When using TCALL instruction (SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12 PC13-0<-(taddr)5-0+(taddr+1) SP<-SP-4
------------
--------------------------* When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions * When using TBR instruction PC13-0<-(taddr)5-0+(taddr+1)
-----------Determined by referenced instruction
1
3
*10
-------------------------------4 * When using TCALL instruction (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-5)<-0, 0, PC13, 12 (SP-2)<-X, X, MBE, RBE PC13-0<-(taddr)5-0+(taddr+1)
------------
-------------------------------3 * When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions
SP<-SP-6
-----------Determined by referenced instruction
Notes 1. Setting MBE=0 or MBE=1, MBS=15 is required during the execution of IN or OUT instruction. 2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction table definitions. 3. The portion in a double box can be supported only in the Mk II mode. Other portions can be supported only in the Mk I mode.
26
PD75P3116
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory contained in the PD75P3116 is a 16384 x 8-bit one-time PROM that can be electrically written one time only. The pins listed in the table below are used for this PROM's write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses.
Pin VPP X1, X2 MD0 to MD3 D0/P60 to D3/P63 (lower 4 bits) D4/P50 to D7/P53 (upper 4 bits) VDD Function Pin where program voltage is applied during program memory write/verify (usually VDD potential) Clock input pins for address updating during program memory write/verify. Input the X1 pin's inverted signal to the X2 pin. Operation mode selection pin for program memory write/verify 8-bit data I/O pins for program memory write/verify
Pin where power supply voltage is applied. Applies 1.8 to 5.5 V in normal operation mode and +6 V for program memory write/verify.
Caution Pins not used for program memory write/verify should be connected to Vss.
8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the PD75P3116 enters the program memory write/verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation mode specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L X MD2 H H H H MD3 L H H H Zero-clear program memory address Write mode Verify mode Program inhibit mode Operation mode
X: L or H
27
PD75P3116
8.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull down unused pins to Vss through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Select the program memory address zero-clear mode. (5) Supply 6 V to VDD and 12.5 V to VPP pins. (6) Write data in the 1-ms write mode. (7) Select the verify mode. If the data is written, go to (8) and if not, repeat (6) and (7). (8) Additional write. (X: number of write operations from (6) and (7)) x 1 ms (9) Apply four pulses to the X1 pin to increment the program memory address by one. (10) Repeat (6) to (9) until the end address is reached. (11) Select the program memory address zero-clear mode. (12) Return the VDD- and VPP-pin voltages to 5 V. (13) Turn off the power. The following figure shows steps (2) to (9).
X repetitions Write Verify Additional write Address increment
VPP VPP VDD VDD + 1 VDD VDD
X1 D0/P60 to D3/P63 D4/P50 to D7/P53
Data input
Data output
Data input
MD0/P30
MD1/P31
MD2/P32
MD3/P33
28
PD75P3116
8.3 Program Memory Read Procedure The PD75P3116 can read program memory contents using the following procedure. (1) Pull down unused pins to VSS through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Select the program memory address zero-clear mode. (5) Supply 6 V to the VDD and 12.5 to the VPP pins. (6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (7) Select the program memory address zero-clear mode. (8) Return the VDD- and VPP-pin voltages to 5V. (9) Turn off the power. The following figure shows steps (2) to (7).
VPP VPP VDD VDD + 1 VDD VDD
X1
D0/P60 to D3/P63 D4/P50 to D7/P53
Data output
Data output
MD0/P30
MD1/P31
"L"
MD2/P32
MD3/P33
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PD75P3116
8.4 One-time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening.
Storage temperature 125C Storage time 24 hours
NEC offers QTOP microcontrollers for which one-time PROM writing, marking, screening, and verification are provided at additional cost. For more detailed information, contact an NEC sales representative.
30
PD75P3116
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Parameter Power supply voltage PROM power supply voltage Input voltage Symbol VDD VPP Test Conditions Rating -0.3 to +7.0 -0.3 to +13.5 Unit V V
VI1 VI2
Except port 5 Port 5 (N-ch open drain)
-0.3 to VDD +0.3 -0.3 to +14 -0.3 to VDD +0.3
V V V mA mA mA mA
Output voltage Output current high
VO IOH Per pin Total of all pins
-10 -30 30 220 -40 to +85
Note
Output current low
IOL
Per pin Total of all pins
Operating ambient temperature Storage temperature
TA
C
Tstg
-65 to +150
C
Note When LCD is driven in normal mode: TA = -10 to +85C Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the reliability of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. CAPACITANCE (TA = 25C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
31
PD75P3116
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator
C1 VDD C2
Recommended constant
X1 X2
Parameter Oscillation frequency (fx) Oscillation stabilization time Note 3
Note 1
Test conditions
MIN. 1.0
TYP.
MAX. 6.0 Note 2
Unit MHz
After VDD reaches oscillation voltage range MIN. 1.0
Note 1
4
ms
Crystal resonator
C1
X1
X2
Oscillation frequency (fx)
C2
6.0 Note 2
MHz
Oscillation stabilization time Note 3 X1 input
VDD = 4.5 to 5.5 V
10 30 1.0 6.0 Note 2
ms
VDD
External clock
X1 X2
MHz
frequency (fx)
Note 1
X1 input high-/low-level width (tXH, tXL)
83.3
500
ns
Notes 1. 2.
The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. When the power supply voltage is 1.8 V VDD < 2.7 V and the oscillation frequency is 4.19 MHz < fx 6.0 MHz, setting the processor clock control register (PCC) to 0011 results in 1 machine cycle being less than the required 0.95 s. Therefore, set PCC to a value other than 0011.
3.
The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode.
Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VDD. * Do not ground to a ground pattern in which a high current flows. * Do not fetch a signal from the oscillator.
32
PD75P3116
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator
C3 VDD
Recommended constant
XT1 XT2 R C4
Parameter Oscillation frequency (fXT) Oscillation stabilization time Note 2 XT1 input frequency
Note 1
Test conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
VDD = 4.5 to 5.5 V
1.0
2 10
s
External clock
XT1 XT2
32
100
kHz
(fXT)
Note 1
XT1 input high-/low-level width (tXTH, tXTL)
5
15
s
Notes 1. 2. Caution
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VDD. * Do not ground to a ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, and is more liable to misoperation by noise than the main system clock oscillation circuit. Special care should therefore be taken regarding the wiring method when the subsystem clock is used.
33
PD75P3116
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current low Symbol IOL Per pin Total of all pins Input voltage high VIH1 Ports 2, 3, 8, and 9 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH2 Ports 0, 1, 6, RESET 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIH3 Port 5 (N-ch open-drain) VIH4 Input voltage low VIL1 X1, XT1 Ports 2, 3, 5, 8, and 9 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL2 Ports 0, 1, 6, RESET 2.7 VDD 5.5 V 1.8 VDD < 2.7 V VIL3 Output voltage high Output voltage low VOH VOL1 X1, XT1 SCK, SO, Ports 2, 3, 6, 8, and 9 IOH = -1.0 mA IOL = 15 mA, VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 When N-ch open-drain pull-up resistor 1 k Pins other than X1, XT1 X1, XT1 VIN = 13 V VIN = 0 V Port 5 (N-ch open-drain) Pins other than X1, XT1, and Port 5 X1, XT1 Port 5 (N-ch open-drain) When another instruction than input instruction is executed Port 5 (N-ch open-drain) When input instruction is executed Output leakage current high Output leakage current low On-chip pull-up resistor ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 13 V VOUT = 0 V VDD = 5.0 V VDD = 3.0 V -10 -3 0.4 0.2VDD V V 2.7 VDD 5.5 V 1.8 VDD < 2.7 V 0.7VDD 0.9VDD 0.8VDD 0.9VDD 0.7VDD 0.9VDD VDD - 0.1 0 0 0 0 0 VDD - 0.5 0.2 2.0 Test conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD 13 13 VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 Unit mA mA V V V V V V V V V V V V V V
SCK, SO, Ports 2, 3, 5, 6, 8, and 9
Input leakage current high
ILIH1 ILIH2 ILIH3
VIN = VDD
3 20 20 -3 -20 -3
A A A A A A
Input leakage current low
ILIL1 ILIL2 ILIL3
-30 -27 -8 3 20 -3
A A A A A A
SCK, SO/SB0, SB1, Ports 2, 3, 6, 8, and 9 Port 5 (N-ch open-drain)
RL
VIN = 0 V
Ports 0, 1, 2, 3, 6, 8, and 9 (Excluding P00 pin)
50
100
200
k
34
PD75P3116
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter LCD drive voltage Symbol VLCD VAC0 = 0 Test conditions TA = -40 to +85C TA = -10 to +85C VAC0 = 1 VAC current
Note 1
MIN. 2.7 2.2 1.8
TYP.
MAX. VDD VDD VDD
Unit V V V
IVAC VODC
VAC0 = 1, VDD = 2.0 V 10% lo = 1.0 A lo = 0.5 A 6.00 MHz Note 4 Crystal oscillation VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 1.8 V VLCD VDD VDD = 5.0 V 10% VDD = 3.0 V 10% HALT mode
Note 5 Note 6
1 0 0
4 0.2 0.2
A
V V
LCD output voltage deviation Note 2 (common)
LCD output voltage VODS deviation Note 2 (segment) Supply current Note 3 IDD1
3.2 0.55 0.7 0.25 2.5 0.45 0.65 0.22 45 20 45 42 42 5.5 2.2 5.5 4.0 4.0 0.05 0.02
9.5 1.6 2.0 0.8 7.5 1.35 1.8 0.7 130 55 90 120 85 18 7 12 12 8 10 5 3
mA mA mA mA mA mA mA mA
IDD2
C1 = C2 = 22 pF
VDD = 5.0 V 10% VDD = 3.0 V 10%
IDD1
4.19 MHz Note 4 Crystal oscillation
VDD = 5.0 V 10% Note 5 VDD = 3.0 V 10% Note 6 HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10%
IDD2
C1 = C2 = 22 pF
IDD3
32.768 kHz Note 7 Crystal oscillation
Low-voltage mode
Note 8
VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 3.0 V, TA = 25C
A A A A A A A A A A A A A
Low power consumption mode Note 9 IDD4 HALT mode
VDD = 3.0 V 10% VDD = 3.0 V, TA = 25C VDD = 3.0 V 10% Lowvoltage VDD = 2.0 V 10% mode VDD = 3.0 V, TA = 25C Note 8 Low VDD = 3.0 V 10% power consump- VDD = 3.0 V, tion mode TA = 25C Note 9
IDD5
XT1 = 0 V Note 10 STOP mode
VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25C
0.02
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9.
Set to VAC0 = 0 when the low power consumption mode and the stop mode are used. If VAC0 = 1 is set, the current increases for approx. 1 A. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). Not including currents flowing in on-chip pull-up resistors. Including oscillation of the subsystem clock. When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode. When PCC is set to 0000 and the device is operated in the low-speed mode. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. When the sub-oscillation circuit control register (SOS) is set to 0000. When SOS is set to 0010.
10. When SOS is set to 00x1 and the feedback resistor of the sub-oscillation circuit is not used.
35
PD75P3116
AC CHARACTERISTICS (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter CPU clock cycle time
Note 1
Symbol tCY Operating on main system clock
Test conditions VDD = 2.7 to 5.5 V
MIN. 0.67 0.95 114
TYP.
MAX. 64 64
Unit
s s s
(Min. instruction execution time = 1 machine cycle) TI0, TI1, TI2 input frequency TI0, TI1, TI2 input high-/low-level width Interrupt input high-/ low-level width tTIH, tTIL fTI
Operating on subsystem clock
122
125
VDD = 2.7 to 5.5 V
0 0
1.0 275
MHz kHz
VDD = 2.7 to 5.5 V
0.48 1.8
s s s s s s s
tINTH, tINTL INT0
IM02 = 0 IM02 = 1
Note 2 10 10 10 10
INT1, 2, 4 KR0 to KR7 RESET low-level width tRSL
Notes 1.
The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC) and the processor clock control
Cycle Time tCY [s] 6 5 4 3 64 60
tCY vs VDD (At main system clock operation)
register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic with the main system clock operating. 2. 2tCY or 128/fx is set by setting the interrupt mode register (IM0).
Guaranteed Operation Range
2
1
0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V]
36
PD75P3116
SERIAL TRANSFER OPERATION 2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY1 VDD = 2.7 to 5.5 V Test conditions MIN. 1300 3800 SCK high-/low-level width SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL1, tKH1
VDD = 2.7 to 5.5 V
tKCY1/2-50 tKCY1/2-150
setup time
tSIK1
VDD = 2.7 to 5.5 V
150 500
(to SCK) SI
Note 1
hold time
tKSI1
VDD = 2.7 to 5.5 V
400 600
(from SCK) SCKSO delay time
Note 1
output
tKSO1
RL = 1 k, CL = 100 pF
Note 2
VDD = 2.7 to 5.5 V
0 0
250 1000
ns ns
Notes 1. 2.
In 2-wire serial I/O mode, read this parameter as SB0 or SB1 instead. RL and CL are the load resistance and load capacitance of the SO output lines, respectively.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY2 VDD = 2.7 to 5.5 V Test conditions MIN. 800 3200 SCK high-/low-level width SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL2, tKH2
VDD = 2.7 to 5.5 V
400 1600
setup time
tSIK2
VDD = 2.7 to 5.5 V
100 150
(to SCK) SI
Note 1
hold time
tKSI2
VDD = 2.7 to 5.5 V
400 600
(from SCK) SCKSO delay time
Note 1
output
tKSO2
RL = 1 k, CL = 100 pF
Note 2
VDD = 2.7 to 5.5 V
0 0
300 1000
ns ns
Notes 1. 2.
In 2-wire serial I/O mode, read this parameter as SB0 or SB1 instead. RL and CL are the load resistance and load capacitance of the SO output lines, respectively.
37
PD75P3116
SBI Mode (SCK...Internal clock output (master)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY3 VDD = 2.7 to 5.5 V Test conditions MIN. 1300 3800 SCK high-/low-level width SB0, 1 setup time (to SCK) SB0, 1 hold time (from SCK) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3 RL = 1 k, CL = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
tKL3, tKH3
VDD = 2.7 to 5.5 V
tKCY3/2-50 tKCY3/2-150
tSIK3
VDD = 2.7 to 5.5 V
150 500 tKCY3/2 VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns
Note
RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
SBI Mode (SCK...External clock input (slave)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY4 VDD = 2.7 to 5.5 V Test conditions MIN. 800 3200 SCK high-/low-level width SB0, 1 setup time (to SCK) SB0, 1 hold time (from SCK) SCKSB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4 RL = 1 k, CL = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
tKL4, tKH4
VDD = 2.7 to 5.5 V
400 1600
tSIK4
VDD = 2.7 to 5.5 V
100 150 tKCY4/2 VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000
ns ns ns ns ns ns
Note
RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
38
PD75P3116
AC Timing Test Point (Excluding X1, XT1 Input)
VIH (MIN.) VIL (MAX.)
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
VOH (MIN.) VOL (MAX.)
Clock Timing
1/fX tXL tXH
X1 Input
VDD-0.1 V 0.1 V
1/fXT tXTL tXTH
XT1 Input
VDD-0.1 V 0.1 V
TI0, TI1, TI2 Timing
1/fTI tTIL tTIH
TI0, TI1, TI2
39
PD75P3116
Serial Transfer Timing 3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK tSIK1, 2 tKSI1, 2
SI tKSO1, 2
Input Data
SO
Output Data
2-wire serial I/O mode
tKCY1, 2 tKL1, 2 tKH1, 2
SCK tSIK1, 2 tKSI1, 2
SB0, 1
tKSO1, 2
40
PD75P3116
Serial Transfer Timing Bus release signal transfer
tKCY3, 4 tKL3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4
SB0, 1 tKSO3, 4
Command signal transfer
tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INT0, 1, 2, 4 KR0 to 7
RESET input timing
tRSL
RESET
41
PD75P3116
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85C)
Parameter Release signal set time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Release by RESET Release by interrupt request Test conditions MIN. 0 215 /fX Note 2 TYP. MAX. Unit
s
ms ms
Notes 1. 2.
The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 220/fx 217/fx 215/fx 213/fx fx = at 4.19 MHz (approx. 250 ms) (approx. 31.3 ms) (approx. 7.81 ms) (approx. 1.95 ms) Wait time 220/fx 217/fx 215/fx 213/fx fx = at 6.0 MHz (approx. 175 ms) (approx. 21.8 ms) (approx. 5.46 ms) (approx. 1.37 ms)
42
PD75P3116
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT mode STOP Mode Operating Mode
Data Retention Mode
VDD tSREL STOP Instruction Execution RESET tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode STOP Mode Operating Mode
Data Retention Mode
VDD tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT
43
PD75P3116
DC PROGRAMMING CHARACTERISTICS (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Input voltage high Symbol VIH1 VIH2 Input voltage low VIL1 VIL2 Input leakage current Output voltage high Output voltage low VDD power supply current VPP power supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Test conditions Except X1 and X2 pins X1, X2 Except X1 and X2 pins X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 MIN. 0.7VDD VDD-0.5 0 0 TYP. MAX. VDD VDD 0.3VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Avoid exceeding +13.5 V for VPP including the overshoot. 2. VDD must be applied before VPP, and cut after VPP. AC PROGRAMMING CHARACTERISTICS (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Address setup time
Note 2
Symbol (to MD0) tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR
Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR - - - - - - - tACC tOH - -
Test conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
MD1 setup time (to MD0) Data setup time (to MD0) Address hold time
Note 2
(from MD0)
Data hold time (from MD0) MD0data output float delay time VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width Additional program pulse width MD0 setup time (to MD1) MD0data output delay time MD1 hold time (from MD0) MD1 recovery time (from MD0) Program counter reset time X1 input high-/low-level width X1 input frequency Initial mode set time MD3 setup time (to MD1) MD3 hold time (from MD1) MD3 setup time (to MD0) Address Address
Note 2 Note 2
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H+tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2 During program memory read During program memory read During program memory read During program memory read During program memory read 0 2 2 2 2 130
MHz
s s s s s
ns
data output delay time data output hold time
MD3 hold time (from MD0) MD3data output float delay time
s s
Notes 1. Corresponding symbol of PD27C256A 2. The internal address signal is incremented by 1 at the rising edge of the fourth X1 input and is not connected to a pin.
44
PD75P3116
Program Memory Write Timing
tVPS VPP VPP VDD tVDS VDD VDD+1 VDD tXH
X1
D0/P60 to D3/P60 D4/P50 to D7/P53 tI MD0/P30
Data input tDS tDH
Data output tDV tDF
Data input tDS tDH
tXL
Data input tAS
tAH
tPW MD1/P31 tPCR MD2/P32 tM3S MD3/P33 tM1S tM1H
tM1R
tM0S
tOPW
tM3H
Program Memory Read Timing
tVPS VPP VPP VDD tVDS VDD VDD+1 VDD tXH
X1 tXL D0/P60 to D3/P60 D4/P50 to D7/P53 tDV tI MD0/P30 tM3HR tDAD tHAD Data output Data output tDFR
MD1/P31
tPCR MD2/P32 tM3SR MD3/P33
45
PD75P3116
10. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD vs VDD (Main System Clock: 6.0-MHz Crystal Resonator) 10 (TA = 25C)
5.0
PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 Main system clock HALT mode + 32-kHz oscillation 0.5
Supply Current IDD (mA)
0.1
Subsystem clock operation mode (SOS.1 = 0) Main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) and subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1) and subsystem clock HALT mode (SOS.1 = 1)
0.05
0.01
0.005
X1
X2 XT1
XT2 330 k 22 pF
Crystal resonator 6.0 MHz
Crystal resonator 32.768 kHz
22 pF
22 pF VDD
22 pF VDD 6
0.001
0
1
2
3
4 Supply Voltage VDD (V)
5
7
8
46
PD75P3116
IDD vs VDD (Main System Clock: 4.19-MHz Crystal Resonator) 10 (TA = 25C)
5.0
PCC = 0011 PCC = 0010 PCC = 0001 1.0 PCC = 0000
0.5
Main system clock HALT mode + 32-kHz oscillation
Supply Current IDD (mA)
0.1
Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode + 32-kHz oscillation (SOS.1 = 0) Main system clock STOP mode + 32-kHz oscillation (SOS.1 = 1) and subsystem clock HALT mode (SOS.1 = 1)
0.05
0.01
0.005
X1
X2 XT1
XT2
Crystal resonator
4.19 MHz 22 pF 22 pF VDD 0.001 0 1 2 3 4 Supply Voltage VDD (V) 5 6
32.768 kHz 330 k 22 pF VDD 7 8 22 pF
Crystal resonator
47
PD75P3116
11. PACKAGE DRAWINGS 64 PIN PLASTIC QFP ( 14)
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006 +0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
48
M
55
Q
PD75P3116
64 PIN PLASTIC LQFP ( 12)
A B
48 49 33 32
detail of lead end
C
D
S
64
1
17 16
F
G P
H
I
M
J K
N
NOTE
L
ITEM MILLIMETERS A B C D F G H I J K L M N P Q R S 14.80.4 12.00.2 12.00.2 14.80.4 1.125 1.125 0.300.10 0.13 0.65 (T.P.) 1.40.2 0.60.2 0.15 +0.10 -0.05 0.10 1.4 0.1250.075 55 1.7 MAX. INCHES 0.5830.016 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.5830.016 0.044 0.044 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0550.008 0.024 +0.008 -0.009 0.006 +0.004 -0.003 0.004 0.055 0.0050.003 55 0.067 MAX. P64GK-65-8A8-1
Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
M
Q
R
49
PD75P3116
12. RECOMMENDED SOLDERING CONDITIONS
The PD75P3116 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Sales representative. Table 12-1. Surface Mounting Type Soldering Conditions (1) PD75P3116GC-AB8: 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
Soldering Method Infrared reflow VPS
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C min.), Number of times: Three times max. Package peak temperature: 215C, Time: 40 seconds max. (at 200C min.), Number of times: Three times max. Solder temperature: 260C max., Flow time: 10 seconds max., Number of times: Once, Preheating temperature: 120C max. (Package surface temperature) Pin temperature: 300C max., Time : 3 seconds max. (per device)
Symbol IR35-00-3
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
--
Caution
Use of more than one soldering method should be avoided (except for partial heating).
(2) PD75P3116GK-8A8: 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
Recommended Conditions Reference Code IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions
Package peak temperature: 235C, Time: 30 seconds max. (at 210C min.), Number of times: Twice max., Number of days: 7Note (after that, prebaking is necessary at 125C for 10 hours) Products other than those supplied in thermal-resistant tray (magazine, taping, and non-thermal-resistant tray) cannot be baked in their packs. Package peak temperature: 215C, Time: 40 seconds max. (at 200C min.), Number of times: Twice max., Number of days: 7Note (after that, prebaking is necessary at 125C for 10 hours) Products other than those supplied in thermal-resistant tray (magazine, taping, and non-thermal-resistant tray) cannot be baked in their packs. Soldering bath temperature: 260C max., Time: 10 seconds max., Number of times: Once Preheating temperature: 120C max. (package surface temperature) Number of days: 7Note (after that, prebaking is necessary at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Wave soldering
WS 60-107-1
Partial heating
--
Note Number of days after unpacking the dry pack. Storage conditions are 25C and 65%RH max. Caution Do not use different soldering methods together (however, partial heating can be performed with other soldering methods.)
50
PD75P3116
APPENDIX A. FUNCTION LIST OF PD75308B, 753108 AND 75P3116
Parameter Program memory
PD75308B
Mask ROM 0000H to 1F7FH (8064 x 8 bits)
PD753108
Mask ROM 0000H to 1FFFH (8192 x 8 bits) 000H to 1FFH (512 x 4 bits)
PD75P3116
One-time PROM 0000H to 3FFFH (16384 x 8 bits)
Data memory CPU Instruction execution time When main system clock is selected When subsystem clock is selected SBS register Stack area Subroutine call instruction stack operation Instruction BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr CALLF !faddr I/O port CMOS input CMOS input/output Bit port output N-ch open-drain input/output Total LCD controller/driver 3 machine cycles 2 machine cycles 8 16 8 8 40 75X Standard 0.95, 1.91, 15.3 s (during 4.19-MHz operation)
75XL CPU * 0.95, 1.91, 3.81, 15.3 s (during 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (during 6.0-MHz operation)
122 s (during 32.768-kHz operation) None 000H to 0FFH 2-byte stack Unavailable SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection 000H to 1FFH When Mk I mode : 2-byte stack When Mk II mode : 3-byte stack When Mk I mode : unavailable When Mk II mode : available Available
Stack
Mk I mode : 3 machine cycles Mk II mode : 4 machine cycles Mk I mode : 2 machine cycles Mk II mode : 3 machine cycles 8 20 0 4 32
Segment selection: 24/28/32 Segment selection: 16/20/24 segments (can be changed to CMOS (can be changed to CMOS input/output port in input/output port in 4-unit; 4-unit; max. 8) max. 8) Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) On-chip split resistor for LCD driver can be specified by using mask option. No on-chip split resistor for LCD driver
Timer
3 channels * Basic interval timer: 1 channel * 8-bit timer/event counter: 1 channel * Watch timer: 1 channel
5 channels * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter) * Watch timer: 1 channel
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PD75P3116
Parameter Clock output (PCL)
PD75308B
* , 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation)
PD753108
PD75P3116
* , 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation) * , 750, 375, 93.8 kHz (Main system clock: during 6.0-MHz operation)
BUZ output (BUZ)
2 kHz * 2, 4, 32 kHz (Main system clock: (Main system clock: during 4.19-MHz operation or during 4.19-MHz operation) subsystem clock: during 32.768-kHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: 6.0-MHz operation) 3 modes are available * 3-wire serial I/O mode *** MSB/LSB can be selected for transfer first bit * 2-wire serial I/O mode * SBI mode
Serial interface
SOS register
Feedback resistor cut flag (SOS.0) Sub-oscillation circuit current cut flag (SOS.1)
None None None No External: 3, Internal: 3 VDD = 2.0 to 6.0 V TA = -40 to +85C * 80-pin plastic QFP (14 x 20 mm) * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (Fine pitch) (12 x 12 mm)
Contained Contained Yes Yes External: 3, Internal: 5 VDD = 1.8 to 5.5 V
Register bank selection register (RBS) Standby release by INT0 Vectored interrupt Supply voltage Operating ambient temperature Package
* 84-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) * 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
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PD75P3116
APPENDIX B. DEVELOPMENT TOOLS
The following development tools have been provided for system development using the PD75P3116. In the 75XL series, a common relocatable assembler is used in combination with a device file dedicated to each model.
RA75X relocatable assembler Host machine OS PC-9800 Series MS-DOS
TM
Part No. (name) Supply medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC
S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X
Ver.3.30 to Ver.6.2 Note IBM PC/ATTM or compatibles Refer to OS for IBM PCs
Device file
Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2 Note IBM PC/AT or compatibles Refer to OS for IBM PCs Supply medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC
Part No. (name)
S5A13DF753108 S5A10DF753108 S7B13DF753108 S7B10DF753108
Note Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software. Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described above.
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PD75P3116
PROM Write Tools
Hardware PG-1500 This is a PROM writer that can program single-chip microcontroller with PROM in stand-alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities ranging from 256 K to 4 M bits. This is a PROM programmer adapter for the PD75P3116GC. It can be used when connected to a PG-1500. This is a PROM programmer adapter for the PD75P3116GK. It can be used when connected to a PG-1500. Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on host machine. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2 Note IBM PC/AT or compatible Refer to OS for IBM PCs Supply medium 3.5" 2HD 5" 2HD 3.5" 2HD 5" 2HC Part No. (name)
PA-75P3116BGC PA-75P3116BGK Software PG-1500 controller
S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500
Note Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software. Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.
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PD75P3116
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the PD75P3116. Various system configurations using these in-circuit emulators are listed below.
Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. For development of the PD753108 Subseries, the IE-75000-R is used with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R or EP-753108GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. The IE-75000-R includes a connected emulation board (IE-75000-R-EM). The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. The IE-75001-R is used in combination with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R or EP-753108GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. This is an emulation board for evaluating application systems using the PD75P3116. It is used in combination with the IE-75000-R or IE-75001-R. This is an emulation probe for the PD75P3116GC. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a 64-pin conversion socket (EV-9200GC-64) to facilitate connections with target system. This is an emulation probe for the PD75P3116GK. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a 64-pin conversion adapter (TGK-064SBW) to facilitate connections with target system. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232C or Centronics interface. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2 Note 3 IBM PC/AT or compatible Refer to OS for IBM PCs Supply medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC Part No. (name)
IE-75001-R
IE-75300-R-EM EP-753108GC-R EV-9200GC-64 EP-753108GK-R TGK-064SBW
Note 2
Software
IE control program
S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X
Notes 1. 2. 3.
This is a maintenance product. Made by TOKYO ELETECH Corporation (Tokyo, 03-5295-1661). Contact to an NEC sales representative for detailed information. Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software. Operation of the IE control program is guaranteed only when using the host machine and OS described above. 2. The PD753104, 753106, 753108, and 75P3116 are generically called the PD753108 Subseries.
Remarks 1.
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PD75P3116
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS PC DOS
TM
Version Ver.3.1 to 6.3, J6.1/V Note to J6.3/V Note Ver.5.0 to 6.2 5.0/V Note to 6.2/V Note
MS-DOS
IBM DOSTM
J5.02/V Note
Note Only English mode is supported. Caution Ver. 5.0 and later include a task swapping function, but this function cannot be used in this software.
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PD75P3116
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Device Related Documents
Document No. Document Name English Japanese U10086J U11369J U10890J IEM-5600 U10453J
PD753104, 753106, and 753108 Data Sheet PD75P3116 Data Sheet PD753108 User's Manual PD753108 Instruction Table
75XL Series Selection Guide
U10086E U11369E (This document) U10890E - U10453E
Development Tool Related Documents
Document No. Document Name English Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-753108GC/GK-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language PC-9800 series (MS-DOS) base IBM PC series (PC DOS) base EEU-1416 U11354E EEU-1495 EEU-1335 EEU-1346 EEU-1363 EEU-1291 Japanese EEU-846 U11354J EEU-968 U11940J EEU-731 EEU-730 EEU-704
U10540E
EEU-5008
Other Related Documents
Document No. Document Name English IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcontroller-related Product Guide Third Party's Product C10943X C10535E C11531E C10983E - MEI-1202 - C10535J C11531J C10983J MEM-539 C11893J U11416J Japanese
Caution
The above related documents are subject to change without notice. For design purposes, etc., be sure to use the latest versions.
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PD75P3116
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD75P3116
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
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PD75P3116
QTOP is a trademark of NEC Corporation. MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
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