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FEATURES Fully Compliant with Standard and Enhanced GSM Specification -12 dBm Input 1 dB Compression Point -2 dBm Input Third Order Intercept 10 dB SSB Noise Figure (330 ) DC-400 MHz RF and LO Bandwidths Linear IF Amplifier Linear-in-dB and Stable over Temperature Voltage Gain Control Quadrature Demodulator Onboard Phase-Locked Quadrature Oscillator Demodulates IFs from 5 MHz to 50 MHz Low Power 9 mA at Midgain 1 A Sleep Mode Operation 3.0 V to 3.6 V Operation Interfaces to AD7013, AD7015 and AD6421 Baseband Converters 20-Lead SSOP
GSM 3 V Receiver IF Subsystem AD6458
FUNCTIONAL BLOCK DIAGRAM
LO I RF BPF PLO Q AGC FREF
AD6458
GENERAL DESCRIPTION
The AD6458 is a 3 V, low power receiver IF subsystem for operation at input frequencies as high as 400 MHz and IFs from 5 MHz up to 50 MHz. It is optimized for operation in GSM, DCS1800 and PCS1900 receivers. It consists of a mixer, IF amplifier, I and Q demodulators, a phase-locked quadrature oscillator, precise AGC subsystem, and a biasing system with external power-down. The low noise, high intercept mixer of the AD6458 is a doubly-balanced Gilbert cell type. It has a nominal -12 dBm input-referred 1 dB compression point and a -2 dBm inputreferred third-order intercept. The mixer section of the AD6458 also includes a local oscillator (LO) preamplifier, which lowers the required LO drive to -16 dBm. The gain control input accepts an external gain-control voltage input from an external AGC detector or a DAC. It provides an 80 dB gain range with 27 mV/dB gain scaling. The I and Q demodulators provide inphase and quadrature baseband outputs to interface with Analog Devices' AD7013 (IS54, TETRA, MSAT) and AD7015 and AD6421 (GSM, DCS1800, PCS1900) baseband converters. An onboard
quadrature VCO which is externally phase-locked to the IF signal drives the I and Q demodulators. This locked reference signal is normally provided by an external VCTCXO under the control of the radio's digital processor. The AD6458 can also provide demodulation of N-PSK and N-QAM in many nonTDMA systems when used with external analog carrier recovery systems such as the Costas Loop. Finally, the VCO can be phase-locked to a frequency which is deliberately offset from the IF, as in the case of a Beat-Frequency Oscillator (BFO), resulting in the product detection of CW or SSB. The AD6458 uses supply voltages from 3.0 V to 3.6 V over the temperature range of -40C to +85C. Operation is enabled by a CMOS logical level; response time is typically <80 s. When disabled, the standby current is reduced to 1 A. The AD6458 comes in a 20-lead shrink small outline (SSOP) surface-mount package.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD6458-SPECIFICATIONS (@ T = +25 C, V = 3.0 V, GREF = 1.2 V, unless otherwise noted)
A P
Parameter MIXER Maximum RF and LO Frequency AGC Conversion Gain Variation Input RF Signal Range Input 1 dB Compression Point Input Third-Order Intercept SSB Noise Figure1 Mixer Output Bandwidth at MXOP IF AMPLIFIERS AGC Gain Variation Input Referred Noise Input Resistance Bandwidth I AND Q DEMODULATORS Demodulation Gain Output Voltage Range Output Voltage Common-Mode Level Output Offset Voltage Output Offset Voltage Variation Output Offset Voltage Variation Error in Quadrature Amplitude Match I/Q Output Bandwidth Output Resistance GAIN CONTROL Total Gain Control Range Control Voltage Range at GAIN Gain Scaling Gain Law Conformance Bias Current at GREF Input Resistance at GAIN PLL Frequency Range Phase Noise Acquisition Time Input Drive Level (FREF) POWER-DOWN INTERFACE Logical Threshold Input Current for Logical High Turn On Response Time Stand By Current POWER SUPPLY Supply Range Worst Case Supply Current Supply Current OPERATING TEMPERATURE TMIN to TMAX
Conditions
Min Typ 400 -8.5 to +9.5 -95
Max
Units MHz dB dBm dBm dBm dB MHz dB nV/Hz k MHz dB V V mV mV mV Degree dB MHz k dB V mV/dB dB A k MHz Degree rms s mV V A s A V mA mA C
0.2 V < VG < 2.25 V, ZS = 50 , ZLOAD = 330 @ VG = 0.2 V, ZS = 50 , ZLOAD = 330 @ VG = 0.2 V, ZS = 50 , ZLOAD = 330 @ ZS =1 k, FRF = 83 MHz, FLO = 96 MHz at -16 dBm @ -3 dB, ZLOAD = 330 0.2 V < VG < 2.25 V AC Short Circuit Input @ VG = 0.2 V @ -3 dB
-15 -11 -2 9 55 -9 to +48 3 5 50 17
IRXP, IRXN, QRXP, QRXN (Not Power Supply Dependant) Differential Differential, over Gain and Temperature Range2 Differential, for 0.5 V < VG < 2.4 V and -25C < TA < +85C (See Note 2) IF = 13 MHz CLOAD = 10 pF Each Pin Mixer + IF + Demod, 0.2 V < VG < 2.25 V
0.3 1.5 -150 1 0.5 1.5 0.25 2 4.7 75 0.2 23 27 0.5 0.5 20
VP - 0.2 +150
3.7
2.4 32
5 IF = 13 MHz, Using Ceramic Filter 100 Power-Up On Logical High To Fully Meet Specifications (See Note 3) 3.0 @ VGAIN = 0.2 V, TA = +85C, VP = 3.6 V4 @ VGAIN = 1.2 V 1.5 75 80 1 3.3 16.5 9 -40 to +85 0.5 80
40
VPOS
150 8 3.6 22
NOTES 1 Including IF noise and using 13 MHz ceramic filter, at V GAIN = 0.2 V. 2 Histograms of Demodulator Offset Voltage Variation in Gain and Temperature can be found in Figures 23 to 27. 3 Max value represent the value at six times the standard deviation, in the worst case condition (T A = +85C). The value at three times the standard deviation is 5 A. 4 Max value represent the value at six times the standard deviation. The value at three times the standard variation is 19 mA. Specifications subject to change without notice.
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AD6458
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . +3.6 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering (60 sec) . . . . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 20-Lead SSOP Package: JA = 126C/W.
PIN CONNECTION 20-Lead SSOP (RS-20)
FREF 1 COM1 2 PRUP 3 LOIP 4 RFLO 5 20 VPS1 19 FLTR 18 VPS2 17 IRXP
AD6458
16 IRXN
TOP VIEW RFHI 6 (Not to Scale) 15 QRXP COM2 7 GREF 8 MXOP 9 NC 10 14 QRXN 13 GAIN 12 IFIM 11 IFIP
ORDERING GUIDE
Temperature Range Package Description Package Option
NC = NO CONNECT
Model
AD6458ARS -40C to +85C 20-Lead Shrink Small Outline RS-20
PIN FUNCTION DESCRIPTIONS
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Label FREF COM1 PRUP LOIP RFLO RFHI COM2 GREF MXOP NC IFIP IFIM GAIN QRXN QRXP IRXN IRXP VPS2 FLTR VPS1
Description Frequency Reference Input Common 1 Power-Up Input Local Oscillator Input RF "Low" Input RF "High" Input Common 2 Gain Reference Input Mixer Output IF Input "Plus" IF Input "Minus" Gain Control Input Q Output "Negative" Q Output "Positive" I Output "Negative" I Output "Positive" VPOS Supply 2 PPL Loop Filter VPOS Supply 1
Function Demodulation LO Input. May be 3 V CMOS input or >100 mV ac coupled for lowest stand by current. Ground. CMOS compatible power up control; 0 = OFF, 3 V = ON. AC coupled LO input. Only 50 mV drive needed, 500 mV max. Usually connected to ac ground. AC coupled, -109 dBV to -29 dBV RF input from 1 k filter for optimal operation. Ground. High impedance input, sets gain scaling, typically 1.2 V. Output of the Mixer. Not internally connected. Should be grounded. Differential Input of variable gain amplifier. Differential Input of variable gain amplifier. 0.2 V-2.4 V using 3 V supply. Max gain at 0.2 V. Differential Q Output. Differential Q Output. Differential I Output. Differential I Output. Supply Voltage. Series RC loop filter, connected to VPS2. Supply Voltage.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6458 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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-3-
AD6458
R1 20k C12 220pF R9 50 PRUP 1 FREF 2 COM1 3 PRUP 4 LOIP R2 50 C2 1nF C4 1nF 5 RFLO 6 RFHI R3 50 GREF C3 1nF 7 COM2 8 GREF 9 MXOP R10 301 R5 OPEN R4 54.9 MXOP C6 1nF 10 VSP1 20 R8 1k FLTR 19 C10 1nF VSP2 18 IRXP 17 IRXP C11 0.1F VPOS C1 0.1F VPOS FREF
LOIP
AD6458
IRXN 16 QRXP 15 QRXP QRXN 14 GAIN 13 IFIM 12 IFIP 11 C7 0.01F R6 50 IFIP R7 50 IFIM C8 0.01F C10 0.1F (BOTTOM) QRXN IRXN
RFHI
GAIN
Figure1. Characterization Board
VPOS
1 2 3
Gm
VP 8 7 A=1
C6 0.1pF
VP R4 50 IOUT
FREF
Gm
6 C7 0.1pF VN
PRUP
FREF PRUP
VPOS IRXP IRXN QRXP QRXN GAIN IFIP IFIM
4
AD830
VN 5
LOIP
LOIP
AD6458
CHARACTERIZATION BOARD
RFIP
1 2 3 4
RFIP
Gm
VP 8 7 A=1
C4 0.1pF
VP R3 50 QOUT
GREF
GREF MXOP
Gm
6 C5 0.1pF VN
AD830
VN 5
MXOP
GAIN
1 2 3 4
Gm
VP 8 7 A=1
C11 0.1pF
VP
R6 50
1 2 3
Gm
VP 8 7 A=1
C9 0.1pF
VP
R5 50
Gm
6 C10 0.1pF VN
Gm
6 C8 0.1pF VN
AD830
VN 5
4
AD830
VN 5
IFIN R1 100
Figure 2. Characterization Test Set
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AD6458
HP663X
IEEE HI LO HI LO I HI
HP34401
IEEE +5V -5V COM +15V
HP6237
HP8657B
10MHz OUT 10MHz IN SYNC IEEE RF OUT MOD I/O
POWER SUPPLY
DMM
SYNTHESIZER HP8657B
10MHz OUT 10MHz IN SYNC IEEE RF OUT MOD I/O LOIP RFIP GREF PRUP FREF VPOS VIN VP
AD6458
MOTHER BOARD IOUT QOUT
SYNTHESIZER HP8657B
10MHz OUT 10MHz IN SYNC IEEE RF OUT MOD I/O
GAIN MXOP IFIN
DP8200
HI F HI S LO F IEEE
SYNTHESIZER DP8200
HI F HI S LO F
LO S
HP8593E
CAL OUT RF I/P IEEE 28 VOLT SWEEP OUT
GND
DC SOURCE
IEEE
LO S GND
DC SOURCE
ANALYSER SPECTRUM
Figure 3. Mixer Characterization Setup
PRUP VPOS C12 220pF 1 FREF 2 COM1 3 PRUP LOIP R2 50 RFHI R1 50 GREF C5 0.1F C7 1nF C2 1nF C4 1nF 4 LOIP VSP1 20 R8 1k FLTR 19 C10 1nF VSP2 18 IRXP IRXP 17 C11 0.1F C1 0.1F VPOS
FREF
AD6458
5 RFLO 6 RFHI 7 COM2 8 GREF 9 MXOP 10 BPF2 IRXN 16 QRXP 15 QRXN 14 GAIN 13 IFIM 12 IFIP 11 C9 10nF
IRXN QRXP QRXN GAIN
R5 330 C13 10nF
Figure 4. Typical Connection Diagram
REV. 0
-5-
AD6458
22 20
15 VGAIN = 0.2V 10
CONVERSION GAIN - dB
18
NOISE FIGURE - dB
5 VGAIN = 1.2V 0
16 14 FIF = 13MHz, ZS = 50 12 10 FIF = 26MHz, ZS = 50 8 FIF = 13MHz, ZS = 400 6 80 120 160 200 240 280 320 360 RF FREQUENCY - MHz 400 440
-5 VGAIN = 2.2V
-10
-15 50
100
150
200 250 300 350 400 RF FREQUENCY - MHz
450
500
550
Figure 5. Mixer Noise Figure vs. RF Frequency
Figure 8. Mixer Conversion Gain vs. RF Frequency, TA = +25C, VPOS = 3.0 V, VREF =1.2 V, FIF =13 MHz
35 30 25 PERCENTAGE
GAIN - dB
12
= 7.7dB = 0.26dB
10 8 6 4 VGAIN = 0.2V
20 15 10
2 0 -2 -4 -6 VGAIN = 2.2V VGAIN = 1.5V
5
-8
0 7.0 7.2 7.4 7.6 7.8 8.0 NOISE FIGURE - dB 8.2 8.4
-10 10
14
18
22
26 30 34 38 42 IF FREQUENCY - MHz
46
50
54
Figure 6. Mixer Noise Figure Histogram, RS = 1 k, FRF = 83 MHz, FIF = 13 MHz
Figure 9. Mixer Conversion Gain vs. IF Frequency, TA = +25C, VPOS = 3 V, VREF = 1.2 V, FRF = 250 MHz
2.0 CSH, VGAIN = 0.2V 1.6 RSH, VGAIN = 1.0V RESISTANCE - k
5.5
15
5.0
10 VPOS = 3V TO 3.6V TA = -25C TO +85C 5
GAIN - dB
RSH, VGAIN = 2.2V
CSH, VGAIN = 1.0V 4.0 CSH, VGAIN = 2.2V
CAP - pF
1.2
4.5
0
0.8
-5 3.5
0.4
RSH, VGAIN = 0.2V
-10
0 50
100
150
200 250 300 350 400 RF FREQUENCY - MHz
450
500
3.0 550
-15 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5
Figure 7. Mixer Input Impedance vs. RF Frequency, VPOS = 3.0 V, TA = +25C
Figure 10. Mixer Conversion Gain vs VGAIN, VREF = 1.2 V, FIF =13 MHz, FRF = 83 MHz
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AD6458
-8 -9 -10 VPOS = 3.6V TA = +25C VPOS = 3.0V TA = +85C VPOS = 3.6V TA = +85C
-5 -10
IF INPUT - dBm (REFERRED TO 50)
TA = +85C TA = +25C
INPUT - dBm (REFERRED TO 50)
-15 -20 -25 -30 -35 -40 -45 -50 -55 -60 TA = -25C TA = -40C
-11 -12 -13
VPOS = 3.0V TA = +25C
VPOS = 3.0V TA = -25C
-14 -15
VPOS = 3.0V TA = -40C 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5
0
0.5
1.0 1.5 VGAIN - Volts
2.0
2.5
Figure 11. Mixer Input 1 dB Compression Point vs. VGAIN, VREF = 1.2 V, FRF = 83 MHz, FIF = 13 MHz
Figure 14. IF Amplifier/Demodulator Input 1 dB Compression Point vs. VGAIN, FIF =13 MHz, VREF = 1.2 V, TA = +25C, VPOS = 3.0 V
70 VGAIN = 0.2V 60
IF AMP/DEMOD GAIN - dB
12000
C SHUNT, VGAIN = 0.2V
3.5
10000 R SHUNT, VGAIN = 2.2V C SHUNT, VGAIN = 1.0V
3.0
40 30 20
VGAIN = 1.0V
RESISTANCE -
8000
2.5
6000
C SHUNT, VGAIN = 2.2V R SHUNT, VGAIN = 1.0V
2.0
VGAIN = 1.5V
4000
1.5
10 0
2000
VGAIN = 2.25V 5 10 15 20 25 30 35 INTERMEDIATE FREQUENCY - dB 40 45
0 0 10
R SHUNT, VGAIN = 0.2V
1.0
20
30
40 50 60 70 IF FREQUENCY - MHz
80
90
0.5 100
Figure 12. IF Amplifier and Demodulator Gain vs. Frequency, TA = +25C, VPOS = 3.0 V, VREF =1.2 V
Figure 15. IF Amplifier Input Impedance vs. Frequency, TA = +25C, VPOS = 3.0 V, VREF = 1.2 V
70 60 TA = -40C TO +85C 50
1 0.8 0.6 0.4
ERROR - dB
GAIN - dB
40 30 20 10
0.2 0 -0.2 -0.4 -0.6 IF AMP/DEMOD
MIXER
0 -10
-0.8
0
0.5
1.0 1.5 VGAIN - Volts
2.0
2.5
-1
0
0.5
1 1.5 GAIN VOLTAGE - Volts
2
2.5
Figure 13. IF Amplifier and Demodulator Gain vs. VGAIN, TA = +25C, VPOS = 3.0 V, FIF = 13 MHz, VREF = 1.2 V
Figure 16. AD6458 Gain Error vs. Gain Control Voltage, Representative Part
REV. 0
-7-
CAPACITANCE - pF
50
AD6458
4.0 3.5 3.0 QUAD_ERROR 2.5 2.0 1.5 1.0 0.5 0 10
FLTR PIN VOLTAGE REFERENCED TO VPOS - Volts
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3 -1.5 5 10 15 20 25 30 35 40 PLL FREQUENCY - MHz 45 50 55
15
20
25 30 35 40 FREF FREQUENCY - MHz
45
50
55
Figure 17. Demodulator Quadrature Error vs. FREF Frequency, TA = +25C, VPOS = 3.0 V
Figure 20. PLL Loop Voltage at FLTR Pin (kVCO) vs. Frequency
16 14 12
PERCENTAGE INPUT - dBm (REFERRED TO 50 - ie. +10dBm -> 2V p-p)
-10
= 2.1d = 0.3d
-15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5
10 8 6 4 2 0 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 ERROR - Degrees
Figure 18. Demodulator Quadrature Error Histogram TA = +25C, VPOS = 3.0 V. FIF = 13 MHz
Figure 21. System [(Mixer + IF Ceramic Filter + IF Amplifier + Demodulator)] Input 1 dB Compression Point vs. VGAIN, TA = +25C, VPOS = 3.0 V, FIF = 13 MHz, FRF = 83 MHz, VREF = 1.2 V
-90
80 70
-95
60 50
PHASE NOISE - dBc
-100
GAIN - dB
40 30 20 10 0
-105
-110
-115
-10
-120 0.1
-20
1 10 100 CARRIER FREQUENCY - kHz 1k 10k
0
0.5
1.0 1.5 VGAIN - Volts
2.0
2.5
Figure 19. PLL Phase Noise vs. Frequency, VPOS = 3 V, CFLTR = 1 nF, RFLTR = 1 k, FREF = 13 MHz
Figure 22. System (Mixer + IF Ceramic Filter + IF Amplifier + Demodulator) Conversion Gain vs. VGAIN, TA = +25C, VPOS = 3.0 V, FIF = 13 MHz, FRF = 83 MHz, VREF = 1.2 V
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AD6458
100 90 80 70 = 0.03mV = 0.4mV
16 14 12
PERCENTAGE
= 0.9mV = 3.4mV
PERCENTAGE
60 50 40 30
10 8 6 4
20 10 0 -4.9 -3.9 -2.9 -1.9 -0.9 0.1 1.1 VARIATION - mV 2.1 3.1 4.1
2 0 -10
-8
-6
-4
-2 0 2 4 OFFSET DRIFT - mV
6
8
10
Figure 23. Demodulation Output Offset Voltage Variation Histogram with Variation Referred to Offset at VGAIN = 1.2 V and TA = +25C, VGAIN = 2.25 V and TA = +25C
Figure 26. Demodulation Output Offset Voltage Variation Histogram with Variation Referred to Offset at VGAIN = 1.2 V and TA = +25C, VGAIN = 0.2 V and TA = -25C
80 70 60
30
25 = -0.04mV = 3.6mV
PERCENTAGE
50 40 30 20 = 0.1mV = 0.6mV
PERCENTAGE
20
15
10
5
10 0 -2.9 -2.4 -1.9 -1.4 -0.9 -0.4 0.1 0.6 1.1 VARIATION - mV
0 -10
1.6
2.1
2.6
3.1
-8
-6
-4
-2 0 2 4 OFFSET DRIFT - mV
6
8
10
Figure 24. Demodulation Output Offset Voltage Variation Histogram with Variation Referred to Offset at VGAIN = 1.2 V and TA = +25C, VGAIN = 0.5 V and TA = +25C C
Figure 27. Demodulation Output Offset Voltage Variation Histogram with Variation Referred to Offset at VGAIN = 1.2 V and TA = +25C, VGAIN = 0.2 V and TA = +85C
50 45
18
16
40
SUPPLY CURRENT - mA
VPOS = 3.6V, TA = +85C 14 VPOS = 3.0V, TA = +85C
35
PERCENTAGE
30 25 20 15 10 5 0 -4.9 = 0.04mV = 1.1mV
12
10 VPOS = 3.6V, TA = +25C 8 VPOS = 3.6V, TA = -40C 6 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5
-3.9
-2.9
-1.9
-0.9 0.1 1.1 VARIATION - mV
2.1
3.1
4.1
5.1
Figure 25. Demodulation Output Offset Voltage Variation Histogram with Variation Referred to Offset at VGAIN = 1.2 V and TA = +25C, VGAIN = 0.2 V and TA = +25C
Figure 28. Power Supply Current vs. Gain Control Voltage, VREF = 1.2 V
REV. 0
-9-
AD6458
2.0 1.9 TA = -40C 1.8 1.7 TA = -25C
Mixer
1.6 1.5 1.4 1.3 1.2 1.1 1.0 0 0.5 1.0 1.5 VGAIN - Volts 2.0 2.5 TA = +85C TA = +25C
The UHF mixer is an improved Gilbert-cell design, and can operate from low frequencies (it is internally dc-coupled) up to an RF input of 400 MHz. The dynamic range at the input of the mixer is determined at the upper end by the maximum input signal level of 56 mV (-15 dBm in 50 between RFHI and RFLO) up to which the mixer remains linear and, at the lower end, by the noise level. It is customary to define the linearity of a mixer in terms of the 1 dB gain-compression point and thirdorder intercept, which for the AD6458 are -12 dBm and -2 dBm, respectively, in a 50 system. The mixer's RF input port is differential; that is, pin RFLO is functionally identical to RFHI, and these nodes are internally biased. The RF port can be modeled as a parallel RC circuit as shown in Figure 30.
RFHI CSH RSH
Figure 29. Minimum Power-Up Voltage vs VGAIN, VPOS = 3.0 V, VREF = 1.2 V
PRODUCT OVERVIEW
VPRUP - Volts
RFLO
The AD6458 provides most of the active circuitry required to realize a complete low power, single-conversion superheterodyne receiver, or the latter part of a double-conversion receiver, at input frequencies up to 400 MHz, with an IF from 5 MHz to 50 MHz. The internal I/Q demodulators, and their associated phase-locked loop, support a wide variety of modulation modes, including n-PSK, n-QAM, and GMSK. A single positive supply voltage of 3.3 V is required (3.0 V minimum, 3.6 V maximum) at a typical supply current of 9 mA at midgain. In the following discussion, VPOS will be used to denote the power supply voltage, which will be assumed to be 3.3 V. Figure 31 shows the main sections of the AD6458. It consists of a variable-gain UHF mixer and linear two-stage IF strip, which together provide a calibrated voltage-controlled gain range of more than 76 dB, followed by dual quadrature demodulators. These are driven by inphase and quadrature clocks generated by a Phase-Locked Loop (PLL), which is locked to a corrected external reference. A CMOS-compatible power-down interface completes the AD6458.
LO INPUT -16dBm LOIP 4
Figure 30. Mixer Port Modeled as a Parallel RC Network
The local oscillator (LO) input is internally biased at VP - 0.8 V and must be ac coupled. The LO interface includes a preamplifier which minimizes the drive requirements, thus simplifying the oscillator design and reducing LO leakage from the RF port. The LO requires a single-sided drive of 50 mV, or -16 dBm in a 50 system. For operation above 300 MHz noise figure can be improved by increasing the LO level. The output of the mixer is single ended with a 330 impedance for driving ceramic filters. The conversion gain is measured between the mixer input and the input of this filter, and varies between -9 dB and +10 dB as a function of the voltage at Pin GAIN. The maximum permissible signal level at Pin MXOP is determined by the maximum gain control voltage. The mixer output port is shown in Figure 32.
4.7k 17 IRXP 16 IRXN RF INPUT -95dBm TO -15dBm RFHI 6 MXOP 9 RFLO 5 13MHz CERAMIC BANDPASS FILTER 11 330 12 IFIP 0 PLL IFIM 90 19 FLTR 4.7k 15 QRXP 14 QRXN 4.7k AGC VOLTAGE VPS1 20 VPS2 18 PRUP 3 2 COM1 7 COM2 BIAS CIRCUIT GAIN TC COMPENSATION 13 GAIN 4.7k 1 FREF
0.1F
AD6458
8 GREF
Figure 31. Functional Block Diagram
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AD6458
VPOS MXP MXM 160k 330 VBIAS 25k 275 MXOP
IRXP IRXN 100pF 100pF
IRXP IRXN
FROM MIXER CORE
QRXP QRXN 100pF 100pF
QRXP QRXN
275
AD6458
GREF 0.1F 160 GAIN 1nF
AD6421
BREFOUT BREFCAP
Figure 32. Mixer Output Port
IF Amplifier
AGC DAC
Most of the gain in the AD6458 resides in the IF amplifier strip, which comprises two stages. Both are fully differential and each has a gain span of 26 dB for the AGC voltage range of 0.2 V to 2.25 V. Thus, in conjunction with the variable gain of the mixer, the total gain span is 76 dB. The overall IF gain varies from -9 dB to 48 dB for the nominal AGC voltage of 0.2 V to 2.25 V. Maximum gain is at VGAIN = 0.2 V. The IF input is differential at IFIP and IFIM. Figure 33 shows a simplified schematic of the IF interface modeled as parallel RC network. The IF's small-signal bandwidth is approximately 50 MHz from IFIP and IFIM through the demodulator.
IFHI CSH IFLO RSH
FREF
VCTCXO
AFC DAC
Figure 34. Interfacing the AD6458 to the AD6421 Baseband Converter
Figure 33. IF Amplifier Port Modeled as a Parallel RC Network
Gain Scaling
When using the Analog Devices AD7013 (IS54, TETRA and satellite receiver applications) and AD7015 or AD6421 (GSM, DCS1800, PCS1900) baseband converters, the external reference may also be provided by the reference output of the baseband converters. The interface between the AD6458 and the AD6421 baseband converter is shown in Figure 34. The AD6421 baseband converter provides a VREF of 1.23 V; an auxiliary DAC in the AD6421 can be used to generate the AGC voltage. Since it uses the same reference voltage, the numerical input to this DAC provides an accurate RSSI value in digital form, no longer requiring the reference voltage to have high absolute accuracy.
I/Q Demodulators
The AD6458's overall gain, expressed in decibels, is linear with respect to the AGC voltage VGAIN at pin GAIN. The gain of all sections is maximum when VGAIN is 0.2, and falls off as the bias is increased to VGAIN = 2.25 and is independent of the power supply voltage. The gain of all stages changes simultaneously. The AD6458's gain scaling is also temperature compensated. The GAIN pin of the AD6458 is an input driven by an external low impedance voltage source, normally a DAC, under the control of radio's digital processor. The gain-control scaling is directly proportional to the reference voltage applied to the pin GREF and is independent of the power supply voltage. When this input is set to the nominal value of 1.2 V, the scale is nominally 27 mV/dB (37 dB/V). Under these conditions, 76 dB of gain range (mixer plus IF) corresponds to a control voltage of 0.2 V <= VG <= 2.25 V. The final centering of this 2.05 V range depends on the insertion losses of the IF filters used. Pin GREF can be tied to an external voltage reference, VREF, provided, for example, by a AD1580 (1.21 V) voltage reference.
Both demodulators (I and Q) receive their inputs internally from the IF amplifiers. Each demodulator comprises a full-wave synchronous detector followed by an 8 MHz, two-pole low-pass filter, producing differential outputs at pins IRXP and IRXN, and QRXP and QRXN. Using the I and Q demodulators for IFs above 50 MHz is precluded by the 5 MHz to 50 MHz range of the PLL used in the demodulator section. The I and Q outputs are differential and can swing up to 2.2 V p-p at the low supply voltage of 3.0 V. They are nominally centered at 1.5 V independently of power supply. They can therefore directly drive the RX ADCs in the AD6421 baseband converter, which require an amplitude of 1.23 V to fully load them when driven by a differential signal. The conversion gain of the I and Q demodulators is 17 dB. For IFs of less than 8 MHz, the on-chip low-pass filters (8 MHz cutoff) do not adequately attenuate the IF or feedthrough products; the maximum input voltage must thus be limited to allow sufficient headroom at the I and Q outputs, not only for the desired baseband signal but also the unattenuated higher order demodulation products. These products can be removed by an external low-pass filter. A simple 1-pole RC filter, with its corner above the modulation bandwidth, is sufficient to attenuate undesired outputs. The design of the RC filter is eased by the 4.7 k resistor integrated at each I and Q output pin.
REV. 0
-11-
AD6458
I/Q Convention
Phase-Locked Loop
The demodulators are driven by quadrature signals provided by a variable frequency quadrature oscillator (VFQO), phaselocked to a reference signal applied to Pin FREF. When this signal is at the IF, in-phase and quadrature baseband outputs are generated at the I output (IRXP and IRXN) and Q output (QRXP and QRXN), respectively. The quadrature accuracy of this VFQO is typically 2 at 13 MHz. A simplified diagram of the FREF input is shown in Figure 35.
VPOS 5k
In practice, the probability of a phase mismatch at power-up is high, so the worst-case linear settling period to full lock needs to be considered in making filter choices. This is typically < 80 s for a quadrature phase error of 3 at an IF of 13 MHz. Note that the VFQO always provides quadrature between its own I and Q outputs, but the phasing between it and the reference carrier will swing around the final value during the PLL's settling time.
Bias System
The AD6458 operates from a single supply, VPOS, usually 3.3 V, at a typical supply current of 9 mA at midgain and TA = +25C. Any voltage from 3.0 V to 3.6 V may be used. The bias system includes a fast acting active high CMOScompatible power-up switch, allowing the part to idle at 1 A when disabled. Biasing is generally proportional-to-absolutetemperature (PTAT) to ensure stable gain with temperature. Other special biasing techniques are used to ensure very accurate gain, stable over the full temperature range.
20k FREF 5k 50A PTAT
Figure 35. Simplified Schematic of the FREF Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Plastic SSOP (RS-20)
0.295 (7.50) 0.271 (6.90)
20
11
0.311 (7.9) 0.301 (7.64)
1
10
0.008 (0.203) 0.002 (0.050)
0.0256 (0.65) BSC
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
8 0
0.037 (0.94) 0.022 (0.559)
-12-
REV. 0
PRINTED IN U.S.A.
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.78) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
C3052-2-4/97
The AD6458 is a complete IF receive subsystem. Although not a requirement for using the AD6458, most applications will use a high-side LO injection on pin LOIP (Pin 4) of the mixer. The I and Q convention is such that when a spectrum with I leading Q is presented to the input of the mixer, and a high-side LO is presented on pin LOIP, I still leads Q at the baseband output of the AD6458.
The VFQO operates from 5 MHz to 50 MHz and is controlled by the voltage between VPOS and FLTR. In normal operation, a series RC network, forming the PLL loop filter, is connected from FLTR to VPOS. The use of an integral sample-hold system ensures that the frequency-control voltage on pin FLTR remains held during power-down, so reacquisition of the carrier occurs in less than 80 s.

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