View HA3-2425-5_120006.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HA-2420, HA-2425
November 1996
3.2s Sample and Hold Amplifiers
Description
The HA-2420 and HA-2425 is a monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultra-low leakage analog switch and JFET input unity gain amplifier. With an external hold capacitor connected to the switch output, a versatile, high performance sample-and-hold or track-andhold circuit is formed. When the switch is closed, the device behaves as an operational amplifier, and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. When the switch is opened the output will remain at its last level. Performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. Accuracy to better than 0.01% is achievable over the temperature range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristics. The ability to operate at gains greater than 1 frequently eliminates the need for external scaling amplifiers.
PKG. NO. F14.3 F14.3 E14.3 N20.35 M14.15
Features
* Maximum Acquisition Time - 10V Step to 0.1%. . . . . . . . . . . . . . . . . . . . . 4s (Max) - 10V Step to 0.01%. . . . . . . . . . . . . . . . . . . . 6s (Max) * Low Droop Rate (CH = 1000pF). . . . . . . . 5V/ms (Typ) * Gain Bandwidth Product . . . . . . . . . . . . . 2.5MHz (Typ) * Low Effective Aperture Delay Time . . . . . . . 30ns (Typ) * TTL Compatible Control Input * 12V to 15V Operation
Applications
* 12-Bit Data Acquisition * Digital to Analog Deglitcher * Auto Zero Systems * Peak Detector * Gated Operational Amplifier
Ordering Information
PART NUMBER HA1-2420-2 HA1-2425-5 HA3-2425-5 HA4P2425-5 HA9P2425-5 TEMP. RANGE (oC) -55 to 125 0 to 75 0 to 75 0 to 75 0 to 75 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 20 Ld PLCC 14 Ld SOIC
The device may also be used as a versatile operational amplifier with a gated output for applications such as analog switches, peak holding circuits, etc. For more information, please see Application Note AN517. The MIL-STD-883 data sheet for this device is available on request.
Pinouts
HA-2420 (CERDIP) HA-2425 (CERDIP, PDIP, SOIC) TOP VIEW
+IN -IN 1 +IN 2 OFFSET ADJ. 3 OFFSET ADJ. 4 V- 5 NC 6 OUTPUT 7 14 S/H CONTROL 13 GND 12 NC 11 HOLD CAP. 10 NC 9 V+ 8 NC OFFSET ADJ. 4 NC 5 OFFSET ADJ. 6 NC 7 V- 8 9 NC 10 11 12 13 OUT NC NC V+ 18 NC 17 NC 16 HOLD CAP. 15 NC 14 NC
HA-2425 (PLCC) TOP VIEW
NC GND S/H -IN 2
3
1
20 19
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
2856.2
5-1
HA-2420, HA-2425
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 40V Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Digital Input Voltage (Sample and Hold Pin) . . . . . . . . . . +8V, -15V Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . . . 90 35 PDIP Package . . . . . . . . . . . . . . . . . . . . . 100 N/A PLCC Package . . . . . . . . . . . . . . . . . . . . 75 N/A SOIC Package . . . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature (Ceramic Packages) . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (PLCC and SOIC - Lead Tips Only)
Operating Conditions
Temperature Range HA-2420-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-2425-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . 12V to 15V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions (Unless Otherwise Specified) VSUPPLY = 15.0V; CH = 1000pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) TEST CONDITIONS TEMP. (oC) Full 25 Full 25 Full 25 Full 25 Full RL = 2k, VO = 20VP-P VCM = 10V fIN 100kHz Full Full Full 25 RL = 2k VO = 20VP-P DC VO = 200mVP-P VO = 200mVP-P VO = 10VP-P VIN = 0V VIN = 5V Low High Full 25 25 25 25 25 25 Full Full Full Full 25 HA-2420-2 MIN 10 5 10 25 80 10 15 3.5 2.0 TYP 2 3 40 10 10 50 90 -76 2.5 100 0.15 75 25 5 2.3 MAX 4 6 200 400 50 100 100 40 -0.8 20 0.8 4 MIN 10 5 10 25 74 10 15 3.5 2.0 HA-2425-5 TYP 3 4 40 10 10 50 90 -76 2.5 100 0.15 75 25 5 2.3 MAX 6 8 200 400 50 100 100 40 -0.8 20 0.8 4 UNITS V mV mV nA nA nA nA M V kV/V dB dB MHz V mA kHz ns % V/s mA A V V s
PARAMETER INPUT CHARACTERISTICS Input Voltage Range Offset Voltage Bias Current Offset Current Input Resistance Common Mode Range TRANSFER CHARACTERISTICS Large Signal Voltage Gain Common Mode Rejection Hold Mode Feedthrough Attenuation (Note 2) Gain Bandwidth Product (Note 2) OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Full Power Bandwidth (Note 2) Output Resistance TRANSIENT RESPONSE Rise Time (Note 2) Overshoot (Note 2) Slew Rate (Note 2) DIGITAL INPUT CHARACTERISTICS Digital Input Current Digital Input Voltage
SAMPLE AND HOLD CHARACTERISTICS Acquisition Time (Note 2) To 0.1% 10V Step
5-2
HA-2420, HA-2425
Electrical Specifications
Test Conditions (Unless Otherwise Specified) VSUPPLY = 15.0V; CH = 1000pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold), Unity Gain Configuration (Output tied to Negative Input) (Continued) TEST CONDITIONS To 0.01% 10V Step VIN = 0V To 1mV TEMP. (oC) 25 25 25 25 25 25 VIN = 0V 25 Full Full Full 25 25 Full HA-2420-2 MIN 80 TYP 3.2 10 860 30 30 5 5 1.8 3.5 2.5 90 MAX 6 20 10 5.5 3.5 MIN 74 HA-2425-5 TYP 3.2 10 860 30 30 5 5 0.1 7.5 3.5 2.5 90 MAX 6 20 1.0 10.0 5.5 3.5 UNITS s mV ns ns ns ns pA nA nA nA mA mA dB
PARAMETER Acquisition Time (Note 2) Hold Step Error Hold Mode Settling Time Aperture Time (Note 3) Effective Aperture Delay Time Aperture Uncertainty Drift Current (Note 2) HA1-2420 HA1-2425 HA3-2425, HA4P2425, HA9P2425 POWER SUPPLY CHARACTERISTICS Supply Current (+) Supply Current (-) Power Supply Rejection NOTES:
2. AV = 1, RL = 2k, CL = 50pF. 3. Derived from computer simulation only; not tested.
Functional Diagram
OFFSET ADJUST V+ 3 4 9
-INPUT +INPUT S/H CONTROL
1 2 14
+
+ HA-2420/2425
7
OUT
13 GND V-
5
11 HOLD CAPACITOR
Test Circuits and Waveforms
-IN INPUT +IN S/H CONTROL HOLD CAP GND
OUTPUT S/H CONTROL HOLD SAMPLE
OUTPUT CH S/H CONTROL INPUT VSTEP
NOTE: Set rise/fall times of S/H Control to approximately 20ns. FIGURE 2. HOLD STEP ERROR TEST
FIGURE 1. HOLD STEP ERROR AND DRIFT CURRENT
5-3
HA-2420, HA-2425 Test Circuits and Waveforms
(Continued)
SINE WAVE INPUT IN2 IN1 IN3 IN4 IN5 IN6 IN7 IN8 A2 A1 +5V EN HI-508A MUX OUT HA-2420/2425 OUT +IN S/H HOLD CONTROL CAP GND VINP-P A0 CH
-IN
VO
S/H CONTROL
HOLD SAMPLE
OUTPUT
V
t
S/H CONTROL INPUT
NOTE: Compute hold mode feedthrough attenuation from the formula: VO UT HOLD Feedthrough Attenuation = 20 log --------------------------------V IN HOLD Where VOUTHOLD = Peak-to-Peak value of output sinewave during the hold mode. FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION
NOTE: Measure the slope of the output during hold, V/t, and compute drift current from: ID = CH V/t. FIGURE 3. DRIFT CURRENT TEST
Schematic Diagram
OFFSET ADJ. V+ R1 Q23 Q90 Q2 Q4 Q45 RP Q7 Q105 Q15 Q11 Q6 Q47 Q49 D1 Q8 Q
19
Q89 Q5 Q17 Q106 Q82
R2 Q30 Q58 J63
Q64 Q65 Q66 Q72
Q29
Q46
Q59 J61 Q73
Q74
Q9
Q91 Q87 Q51 Q48 R7 Q53 Q54 Q50 Q75 Q31 Q32 Q100 Q101 Q56 Q76 C4 J60 Q67 Q68 Q78 Q70 Q102 Q62 R13 Q81 +IN -IN VQ71 Q80 R14 Q79 Q69 R10 Q77 Q55 Q26 C3 15pF R8 R9 OUT Q27 Q21 Q20 Q52 CH
Q3 Q10
Q18 Q13 Q22 Q83
Q24 Q25
Q33 Q34 Q38 Q35
S/H CONTROL
GND Q12
Q14 R11 Q103
R121 GND J86 J57
Q39 Q42
Q40 Q43
Q83 Q41 Q44
Q16
5-4
HA-2420, HA-2425 Application Information
HOLD STEP VOLTAGE (mV) +10 5 -10 -5 0 -5 -10 -15 -20 -25 -30 -35 CH = 100pF CH = 10,000pF CH = 1000pF DC INPUT VOLTAGE (V) CH = 0.1F +5 +10 RI 0.002RI INPUT +IN -IN S/H CONTROL OUT OUTPUT
RF
S/H CONTROL INPUT
RF NOTE: GAIN ~ 1 + ------RI
FIGURE 7. NON-INVERTING CONFIGURATION
Figure 8 shows a typical unity gain circuit, with Offset Zeroing. All of the other normal op amp feedback configurations may be used with the HA-2420/2425. The input amplifier may be used as a gated amplifier by utilizing Pin 11 as the output. This amplifier has excellent drive capabilities along with exceptionally low switch leakage.
CONTROL CH V+
FIGURE 5. HOLD STEP vs INPUT VOLTAGE
Offset Adjustment The offset voltage of the HA-2420 and HA-2425 may be adjusted using a 100k trim pot, as shown in Figure 8. The recommended adjustment procedure is: Apply 0V to the sample-and-hold input, and a square wave to the S/H control. Adjust the trim pot for 0V output in the hold mode. Gain Adjustment The linear variation in pedestal voltage with sample-and- hold input voltage causes a -0.06% gain error (CH = 1000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. The two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. The recommended procedure for adjusting gain error is: 1. Perform offset adjustment. 2. Apply the nominal input voltage that should produce a +10V output. 3. Adjust the trim pot for +10V output in the hold mode. 4. Apply the nominal input voltage that should produce a -10V output. 5. Measure the output hold voltage (V-10NOMINAL). Adjust the trim pot for an output hold voltage of
(V ) + ( -10V ) - 10 NOMINAL --------------------------------------------------------------------------IN
+
+
-
V-
OUT
100k OFFSET TRIM (25mV RANGE)
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)
The method used to reduce leakage paths on the PC board and the device package is shown in Figure 9. This guard ring is recommended to minimize the drift during hold mode. The hold capacitor should have extremely high insulation resistance and low dielectric absorption. Polystyrene (below 85oC), Teflon, or Parlene types are recommended. For more applications, consult Intersil Application Note AN517, or the factory applications group.
CONTROL GND -IN HOLD CAPACITOR +IN
2
RF INPUT RI -IN +IN S/H CONTROL
0.002RF OUTPUT OUT OUT V+ V-
S/H CONTROL INPUT
-RF NOTE: GAIN ---------RI FIGURE 9. GUARD RING LAYOUT (BOTTOM VIEW)
FIGURE 6. INVERTING CONFIGURATION
5-5
HA-2420, HA-2425 Glossary of Terms
Acquisition Time The time required following a "sample" command, for the output to reach its final value within 0.1% or 0.01%. This is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time. Aperture Time The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. The switch opening time is that interval between the conditions of 10% open and 90% open. Effective Aperture Delay Time (EADT) The difference between the digital delay time from the Hold command to the opening of the S/H switch, and the propagation time from the analog input to the switch. EADT may be positive, negative or zero. If zero, the S/H amplifier will output a voltage equal to VIN at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of pedestal and droop errors) will correspond to a value of VIN that occurred before the Hold command. Aperture Uncertainty The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data. Drift Current The net leakage current from the hold capacitor during the hold mode. Drift current can be calculated from the droop rate using the formula:
V I D (pA) = C H (pF) x ------- (V s ) t
Typical Performance Curves
1000 1000 MIN. SAMPLE TIME DRIFT DURING HOLD FOR 0.1% ACCURACY AT 25oC (mV/s) 10V SWINGS (s) NOISE (VRMS) UNITY GAIN PHASE MARGIN (DEGREES) 10 HOLD STEP OFFSET ERROR (mV) 100 OUTPUT NOISE "HOLD" MODE EQUIV. INPUT NOISE "SAMPLE" MODE - 100k SOURCE RESISTANCE
100
1.0
UNITY GAIN BANDWIDTH (MHz) SLEW RATE (V/s) 10pF 100pF 0.01F 1000pF CH VALUE 0.1F 1.0F
10 EQUIV. INPUT NOISE "SAMPLE" MODE - 0 SOURCE RESISTANCE 1 10
0.1
0.01
100 1K 10K 100K BANDWIDTH (LOWER 3dB FREQUENCY = 10Hz)
1M
FIGURE 10. TYPICAL SAMPLE AND HOLD PERFORMANCE AS A FUNCTION OF HOLDING CAPACITOR
FIGURE 11. BROADBAND NOISE CHARACTERISTICS
1000 OPEN LOOP VOLTAGE GAIN (dB)
100 ID (pA)
10
1 -50 -25 0 25 50 75 TEMPERATURE (oC) 100 125
100 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 10
CH = 100pF CH = 1000pF CH = 0.01F
CH = 1.0F CH = 0.1F
100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. DRIFT CURRENT vs TEMPERATURE
FIGURE 13. OPEN LOOP FREQUENCY RESPONSE
5-6
HA-2420, HA-2425 Typical Performance Curves
-30 CH = 1000pF -40 ATTENUATION (dB) -50 -60 -70 -80 -90
(Continued)
OPEN LOOP PHASE ANGLE (DEGREES) 0 20 40 60 80 100 120 140 160 180 200 220 240 10 100 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) CH = 0.1F CH = 0.01F CH = 1000pF CH 100pF CH = 1.0F
100
1K
10K
100K
1M
10M
10V SINUSOIDAL INPUT FREQUENCY (Hz)
FIGURE 14. HOLD MODE FEED THROUGH ATTENUATION
S/H CONTROL S/H (5V/DIV.) SAMPLE HOLD
FIGURE 15. OPEN LOOP PHASE RESPONSE
4V 0V S/H (5V/DIV.)
0V
+10V
VOUT (2V/DIV.)
VOUT (2V/DIV.)
-10V
0V
TIME (1s/DIV.)
TIME (1s/DIV.)
FIGURE 16. ACQUISITION TIME (CH = 1000pF)
FIGURE 17. ACQUISITION TIME (CH = 1000pF)
S/H (5V/DIV.)
S/H (5V/DIV.)
0V
+1V VOUT (0.5V/DIV.) 0V
VOUT (0.5V/DIV.) -1V
TIME (1s/DIV.)
TIME (1s/DIV.)
FIGURE 18. ACQUISITION TIME (CH = 1000pF)
FIGURE 19. ACQUISITION TIME (CH = 1000pF)
5-7
HA-2420, HA-2425 Typical Performance Curves
(Continued)
S/H (5V/DIV.) S/H (5V/DIV.) 0.1V
0V 0V VOUT (50mV/DIV.) -0.1V
VOUT (50mV/DIV.)
TIME (500ns/DIV.)
TIME (500ns/DIV.)
FIGURE 20. ACQUISITION TIME (CH = 1000pF)
FIGURE 21. ACQUISITION TIME (CH = 1000pF)
5-8
HA-2420, HA-2425 Die Characteristics
DIE DIMENSIONS: 102 mils x 61 mils x 19 mils 2590m x 1550m x 483m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA SUBSTRATE POTENTIAL: VBACKSIDE FINISH: Gold, Nickel, Silicon, etc. PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA TRANSISTOR COUNT: 78 PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-2420, HA-2425
GND
VOS ADJ
VOS ADJ
HOLD CAP
V-
V+
OUTPUT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
5-9

▲Up To Search▲

Price & Availability of HA3-2425-5

	To Download HA3-2425-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .