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Integrated Circuit Systems, Inc.
ICS9159-07
Frequency Generator for NexGenTM Nx586 Systems
General Description
The ICS9159-07 is a low-cost frequency generator designed specifically for NexGen Nx586 systems. The integrated buffer minimizes skew and provides the CPU clocks required by the NexGen Nx586 microprocessor. A 14.318 MHz XTAL oscil-lator provides the reference clock to generate standard Nx586 frequencies. The CPU clock makes gradual frequency transi-tions without violating the PLL timing of internal microproc-essor clock multipliers. Either synchronous (2XCPU/3) or asynchronous (32 MHz) PCI bus operation can be selected. Green PC systems are supported through doze mode. * * * * * * *
Features
Three CPU clocks operate up to 65 MHz at 3.3V, plus smooth transitions Selection of nine frequencies, tristate Seven BUS clocks support sync or async bus operation Integrated buffer outputs drive up to 10pF loads 3.13 to 5.25V (3.35%, 5.05%) supply range 28-pin SOIC package Clock duty cycles 45/55
Applications
* Ideal for NexGen Nx586 PCI-based motherboard designs
Block Diagram
NexGen is a trademark of NexGen Corporation.
9159-07 Rev C 060697
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9159-07
Pin Configuration
28-Pin SOIC
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1 2 6,7, 9 3, 11, 23 4, 5, 14 8, 26 10 12 13 15, 16, 18 19, 21, 22, 27 20 17 24 25 28
X1 X2 CPU(0:2) GND FS(0:2) VDD OE DOZE# BSEL# BCLK(0:6) VDDB GNDB DISK KEYBD REF
IN OUT OUT PWR IN PWR IN IN IN OUT PWR PWR OUT OUT OUT
XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz XTAL. Normally, 14.318 MHz. XTAL output which includes XTAL load capacitance. Processor clock outputs which are a multiple of the input reference frequency as shown in the table below. Device Ground. Frequency multiplier select pins. See table below. These inputs have internal pullup devices.* Positive power supply. Output Enable. All outputs tristate when low.** Reduces CPU clock frequency to 10 MHz when at a logic low level.* Synchronous and non-synchronous bus clock selector.* ASYNC=0, SYNC=1 Bus clock outputs are fixed at 2 3 the PCLK frequency. Power for BUS output buffers. This ground return path is brought on separately to permit separating the noise impulses from high output buffers from affecting sensitive internal circuitry.*** Fixed 24 MHz clock (with 14.318 MHz input). Fixed 12 MHz clock (with 14.318 MHz input). REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz.
* Internally pulled-up. ** External pull-up resistor of 5 to 20 kW recommended due to dynamic coupling of adjacent CPU pins. *** Ground for bus clock buffers.
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ICS9159-07
Functionality
14.318 MHz Input, all frequencies in MHz.
OE FS2 FS1 FS0 DZE CPU (0:2) BUS 0:6
1 1 1 1 1 1 1 1 1 0
0 0 0 0 1 1 1 1 X X
0 0 1 1 0 0 1 1 X X
0 1 0 1 0 1 0 1 X X
1 1 1 1 1 1 1 1 0 X
65 60 55.5 51 46.5 42 37.5 35 10 Tristate
BSEL=1 43.3 40 37 34 31 28 25 23.3 6.6 Tristate
BSEL=0 32 32 32 32 32 32 32 32 32 Tristate
Actual CPU Frequencies
CPU Frequency (MHz) Actual Frequency (MHz)
65 60 55.5 51 46.5 42 37.5 35 10 Tristate
64.98 60.03 55.50 51.00 46.53 42.00 37.48 35.00 10.00 Tristate
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ICS9159-07
Absolute Maximum Ratings
Supply Voltage .......................................................................................................... 7.0 V Logic Inputs ....................................................................... GND -0.5 V to VDD +0.5 V Ambient Operating Temperature ............................................................. 0C to +70C Storage Temperature ........................................................................... -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 - 3.7 V, TA = 0 - 70 C unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current
1
SYMBOL VIL VIH IIL IIH IOL IOH IOL VIN=0V
TEST CONDITIONS
MIN 0.7VDD -5.0 30.0 25.0 2.4 2.4 -
TYP 25.0 47.0 -66.0 38.0 -47.0 0.3 2.8 0.3 2.8 80.0
MAX 0.2VDD -5.0 5.0 -42.0 -30.0 0.4 0.4 130.0
UNITS V V A A mA mA mA mA V V V V mA
VIN=VDD VOL=0.8V; for PCLKS & BCLKS VOL=2.0V; for PCLKS & BCLKS VOL=0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL=15mA; for PCLKS & BCLKS IOH=-30mA; for PCLKS & BCLKS IOL=12.5mA; for fixed CLKs IOH=-20mA; for fixed CLKs CPU @65.0 MHz; BUS @ 43.3 MHz; all outputs unloaded
Output High Current1 Output Low Current
1 1 1 1 1 1
Output High Current Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Supply Current
IOH VOL VOH VOL VOH ICC
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-07
Electrical Characteristics at 3.3V
VDD = 3.1 - 3.7 V, TA = 0 - 70 C
AC Characteristics
PARAMETER Rise Time
1
SYMBOL Tr1 Tf1 Tr2 Tf2
TEST CONDITIONS 20pF load; 0.8 to 2.0V 20pF load; 2.0 to 0.8V 20pF load; 20% to 80% 20pF load; 80% to 20% 20pF load; VOUT=1.4V Load=10pF Load=10pF; 0.8 to 2.0V Load=10pF Load=30pF; 0.8 to 2.0V Fixed CLK; Load=20pF; Comp. to the period Fixed CLK; Load=20pF; Comp. to the period A Logic input pins X1, X2 pins Acquisition from 35 MHz to 65 MHz (first crossing) (and 65 to 35). Acquisition from 10 MHz to 65 MHz (first crossing) (and 65 to 10) From 1 st crossing of acquisition to <1% settling.
MIN 45 -150 1.0 -250 0.6 12.0 -250 -600
TYP 0.9 0.8 1.5 1.4 50 50 1.6 1.0 1 2 14.318 5 18 0.46 0.76 400 200 -400 -550
MAX 1.5 1.4 2.5 2.4 55 +150 A 250 A 3 5 16.0 1.4 2.3 +250 1000 110 +500 250
UNITS ns ns ns ns % ps V/ns ps V/ns % % MHz pF pF ms ms ms
Fall Time1 Rise Time Fall Time
1 1 1
Duty Cycle CPU(0:2) BUS(0:6)
Dt Jitter Cycle-to-Cycle Slew1 Jitter 1Cycle-to-Cycle Slew
1 1
Tjcc1 SR1 Tjcc2 SR2 Tjis Tjab Fi
Jitter, One Sigma1 Jitter, Absolute1 Input Frequency1 Logic Input Capacitance
1 1
CIN CINX Ta1 Ta2 ts CPU to CPU CPU to BUS(0:5) TSK1 TSK2 TSK3S TSK4 TSK5
Crystal Oscillator Capacitance Frequency Transition Time1
Frequency Transition Time (to DOZE)1 Frequency Settling Time 1
Skew
1
CPU to BUS(6) BUS(0:5) to BUS(0:5) BUS(0:5) to BUS(6)
CL=10pF VO=1.5V
-900 -500 -1050
ps
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-07
Electrical Characteristics at 5.5V
VDD = 4.5 - 5.5 V, TA = 0 - 70 C
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Input High Current Output Enable Pin2 Output Low Current 1 Output High Current 1 Output Low Current
1
SYMBOL VIL VIH IIL IIH IIH(OE) IOL IOH IOL IOH VOL VOH VOL VOH ICC VIN=0V
TEST CONDITIONS
MIN 2.0 -45.0 -5.0 -5.0 36.0 30.0 2.4 2.4 -
TYP -15.0 A 62.0 -152.0 50.0 -110.0 0.25 4.0 0.2 4.7 130.0
MAX 0.8 A 5.0 400.0 -90.0 -65.0 0.4 0.4 220.0
UNITS V V mA mA mA mA mA mA mA V V V V mA
VIN=VDD, other logic inputs VIN=VDD, OE pin VOL=0.8V; for PCLKS & BCLKS VOL=2.0V; for PCLKS & BCLKS VOL=0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL=20mA; for PCLKS & BCLKS IOH=-70mA; for PCLKS & BCLKS IOL=15mA; for fixed CLKs IOH=-50mA; for fixed CLKs CPU @65.0 MHz; BUS @ 43.3 MHz; all outputs unloaded
Output High Current 1 Output Low Voltage1 Output High Voltage1 Output Low Voltage
1
Output High Voltage1 Supply Current
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-07
Electrical Characteristics at 5.5V
VDD = 4.5 - 5.5 V, TA = 0 - 70 C
AC Characteristics
PARAMETER Rise Time Fall Time Fall Time
1 1
SYMBOL Tr1 Tf1 Tr2 Tf2
TEST CONDITIONS 20pF load; 0.8 to 2.0V 20pF load; 2.0 to 0.8V 20pF load; 20% to 80% 20pF load; 80% to 20% 20pF load; VOUT=1.4V Load=10pF Load=10pF; 0.8 to 2.0V Load=10pF Load=30pF; 0.8 to 2.0V Fixed CLK; Load=20pF; Comp. to the period Fixed CLK; Load=20pF; Comp. to the period Logic input pins X1, X2 pins Acquisition from 35 MHz to 65 MHz (first crossing) (and 65 to 35). Acquisition from 10 MHz to 65 MHz (first crossing) (and 65 to 10) From 1 st crossing of acquisition to <1% settling.
MIN 45 -150 1.6 -250 1.0 12.0 -250 -1600
TYP 0.55 0.52 1.2 1.1 50 50 2.6 1.6 1 2 14.318 5 18 0.50 0.78 400 -800 -1250 -400
MAX 0.95 0.90 2.1 2.0 55 +150 250 3 5 16.0 1.5 2.4 +250 0 -750 +500 -100
UNITS ns ns ns ns % ps V/ns ps V/ns % % MHz pF pF ms ms ms
Rise Time1
1 1
Duty Cycle CPU(0:2)
Dt Jitter Cycle-to-Cycle Slew
1 1 1
Tjcc1 SR1 Tjcc2 SR2 Tjis Tjab Fi CIN
BUS(0:6) Jitter, One Sigma1 Jitter, Absolute1 Input Frequency1 Logic Input Capacitance1
Jitter Cycle-to-Cycle Slew1
Crystal Oscillator Capacitance Frequency Transition Time1
1
CINX Ta1 Ta2 ts
Frequency Transition Time (to DOZE)1 Frequency Settling Time 1 CPU to CPU CPU to BUS(0:5) Skew
1
TSK1 TSK2 TSK3S TSK4 TSK5 CL=10pF VO=1.5V
CPU to BUS(6) BUS(0:5) to BUS(0:5) BUS(0:5) to BUS(6)
-1750 -500 -900
ps
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-07
Typical Timing Diagram of Outputs Showing Skew Relationship
Clock Singles
Note that the skew is rising edge to rising edge. The CPU is runniing at VCO/2 and the BUS clock is runing at VCO/3 resulting in the output rising edges being coincident every 3rd pulse.
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ICS9159-07
LEAD COUNT DIMENSIONL
28L 0.704
SOIC Package Ordering Information
ICS9159M-07
Example:
ICS XXXX M-PPP
Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type
M=SOIC, SOP
Device Type (consists of 3 or 4 digit numbers) Prefix
ICS=Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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