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HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
Integrated Device Technology, Inc.
IDT71V321S/L
FEATURES:
* High-speed access --Commercial: 25/35/55ns (max.) * Low-power operation --IDT71V321S --Active: 250mW (typ.) --Standby: 3.3mW (typ.) --IDT71V321L --Active: 250mW (typ.) --Standby: 660W (typ.) * Two INT flags for port-to-port communications * On-chip port arbitration logic * BUSY output flag * Fully asynchronous operation from either port * Battery backup operation--2V data retention * TTL-compatible, single 3.3V 0.3V power supply * Available in popular plastic packages
DESCRIPTION:
The IDT71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port RAM. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 250mW of power. Low-power (L) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200W from a 2V battery. The IDT71V321 devices are packaged in a 52-pin PLCC and a 64-pin TQFP (thin plastic quad flatpack).
FUNCTIONAL BLOCK DIAGRAM
OEL
R/WL
OER
R/WR
CEL
CER
I/O0L- I/O7L I/O Control I/O Control
I/O0R-I/O7R
BUSYL
(1,2)
BUSYR
Address Decoder
11
(1,2)
A10L A0L
MEMORY ARRAY
Address Decoder
A10R A0R
11
NOTE: 1. BUSY and INT are totem-pole outputs.
OEL
R/WL
CEL
ARBITRATION and INTERRUPT LOGIC
CER
OER
R/WR
INTL
(2)
INTR
(2)
3026 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-3026/2
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (1,2)
V CC CER R/W R BUSYR A 10L INT L BUSYL R/W L CE L INT R A10R
OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7R 43 42 IDT71V321 J52-1 PLCC TOP VIEW(3) 41 40 39 38 37 36 35 34 33
NDEX A1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L
87 6 9 10 11 12 13 14 15 16
A 0L OEL
54
32 1
52 51 50 49 48 47 46 45 44
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
I/O4L I/O5L I/O6L I/O7L
NC GND I/O0R I/O1R
I/O2R I/O3R I/O4R
I/O5R I/O6R
3026 drw 02
BUSYR INTR
INTL BUSYL
R/WR
R/W L
INDEX
A0L A1L A 2L A 3L A 4L A 5L A 6L N/C A 7L A 8L A9L N/C I/O 0L I/O1L I/O2L
OEL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
A10R N/C N/C
N/C N/C A10L
CE L
CER
VCC VCC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IDT71V321 PN64-1 64-PIN TQFP TOP VIEW (3)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OER
A 0R A 1R A 2R A 3R A 4R A 5R A 6R N/C A 7R A 8R A 9R N/C N/C I/O7R I/O 6R
3026 drw 03
NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate orientation of the actual part-marking. 6.34 2
I/O3L N/C I/O 4L I/O 5L I/O 6L I/O 7L N/C GND GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R
IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +4.6 Unit V
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Ambient Temperature 0C to +70C GND 0V VCC 3.3V 0.3V
3026 tbl 02
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
C C C mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V 2.0 -- Vcc+0.3 V (1) -0.3 -- 0.8 V
3026 tbl 03
3026 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V.
NOTES: 1. VIL (min.) = -1.5V for pulse width less than 20ns. 2. VTERM must not exceed VCC + 0.5V.
CAPACITANCE(1)
(TA = +25C, f = 1.0MHz) TQFP ONLY
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VIN = 3dV Max. Unit 9 pF 10 pF
3026 tbl 04 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V 0.3V)
IDT71V321S Symbol |lLl| |lLO| VOL VOH
NOTE:
lDT71V321L Min. -- -- -- 2.4 Max. 5 5 0.4 -- Unit A A V V
3026 tbl 05
Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage (l/O0-l/O7) Output High Voltage
Test Conditions VCC = 3.6V VIN = 0V to VCCVIN = GND to VCC
Min. -- -- -- 2.4
Max. 10 10 0.4 --
CE = VIH, VOUT = 0V to VCC
lOL = 4mA lOL= 16mA lOH = -4mA
VCC = 3.6V, VOUT = GND to VCC
1. At Vcc < 2.0V input leakages are undefined.
Supply CurrentVIN > VCC -0.2V or < 0.2V
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V 0.3V)
71V321X25 Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports -- TTL Level Inputs) Standby Current (One Port -- TTL Level Inputs) ISB3 Full Standby Current (Both Ports -- All CMOS Level Inputs) Test Condition Version COM'L. S L S L S L Typ.(2) Max. 75 75 20 20 30 30 150 120 50 35 105 75 71V321X35 Typ.(2) 75 75 20 20 30 30 71V321X55 Max. Unit 135 105 50 35 90 60 mA Max. Typ.(2) 145 115 50 35 100 70 75 75 20 20 30 30
f = fMAX(3)
CE = VIL, Outputs Open SEM = VIH
ISB1
f = fMAX(3)
CER = CEL = VIH SEMR = SEML = VIH CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Open,
COM'L.
mA
ISB2
COM'L.
mA
f = fMAX(3) Both Ports CEL and CER > VCC - 0.2V
SEMR = SEML = VIH
COM'L. S L 1.0 0.2 5.0 3.0 1.0 0.2 5.0 3.0 1.0 0.2 5.0 3.0 mA
VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V
ISB4
Full Standby Current (One Port -- All CMOS Level Inputs)
CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Open f = fMAX(3)
COM'L.
S L
30 30
90 75
30 30
85 70
30 30
75 60
mA
NOTES: 3026 tbl 06 1. "X" in part numbers indicates power rating (S or L). 2. VCC = 3.3V, TA = +25C, and are not production tested. ICCDC = 70mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
DATA RETENTION CHARACTERISTICS (L Version Only)
Symbol VDR ICCDR tCDR(3) tR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
NOTES: 1. VCC = 2V, TA = +25C, and is not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but not production tested.
3026 tbl 07
Test Conditions VCC = 2.0V, CE > VCC - 0.2V VIN > VCC - 0.2V or VIN< 0.2V COM'L.
Min. 2.0 -- 0 tRC(2)
71V321L Typ.(1) -- 100 -- --
Max. 0 1500 -- --
Unit V A ns ns
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1and 2
3026 tbl 08
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
3.0V tCDR
VDR 2.0V
3.0V tR
CE
VDR VIH VIH
3026 drw 04
3.3V 590 DATA OUT
3.3V 590 DATA OUT 30pF 435 5pF
BUSY INT 435
3026 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load (For tHZ, tLZ, tWZ and tOW) * Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
71V321X25 Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time(1, 2) Output High-Z Time(1, 2) Chip Enable to Power Up Time
(2) (2)
71V321X35 Min. 35 -- -- -- 3 0 -- 0 -- Max. -- 35 35 20 -- -- 15 -- 50
71V321X55 Min. 55 -- -- -- 3 0 -- 0 -- Max. -- 55 55 25 -- -- 30 -- 50 Unit ns ns ns ns ns ns ns ns ns
3026 tbl 09
Parameter
Min. 25 -- -- -- 3 0 -- 0 --
Max. -- 25 25 12 -- -- 12 -- 50
Chip Disable to Power Down Time
NOTES: 1. Transition is measured 200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. "X" in part numbers indicates power rating (S or L).
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID tOH
BUSYOUT
tBDD(2,3)
3026 drw 06
NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low. 2. tBDD delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultanious read operations BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(3)
tACE
CE
tAOE
(4)
tHZ (2)
OE
tLZ DATAOUT tLZ ICC CURRENT ISS
tPU
(1) (1)
tHZ VALID DATA tPD
(4)
(2)
50%
50%
3026 drw 07
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. R/W = VIH, and the address is valid prior to other coincidental with CE transition Low. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6.34
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
71V321X25 Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1, 2) Data Hold Time(3) Write Enable to Output in High-Z
(1, 2)
71V321X35 Min. 35 30 30 0 30 0 20 -- 0 -- 0 Max. -- -- -- -- -- -- -- 15 -- 15 --
71V321X55 Min. 55 40 40 0 40 0 20 -- 0 -- 0 Max. -- -- -- -- -- -- -- 30 -- 30 -- Unit ns ns ns ns ns ns ns ns ns ns ns
Parameter
Min. 25 20 20 0 20 0 12 -- 0 -- 0
Max. -- -- -- -- -- -- -- 12 -- 15 --
Output Active from End-of-Write(1, 2)
NOTES: 3026 tbl 10 1. Transition is measured 200mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. "X" in part numbers indicates power rating (S or L).
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1,(R/W CONTROLLED TIMING) (1,5,8) W
tWC ADDRESS tHZ (7)
OE
tAW
CE
tAS (6) R/W tWZ (7) DATA OUT
(4)
tWP (2)
tWR
(3)
tHZ
(7)
tOW
(4)
tDW DATA IN
tDH
3026 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
tWC ADDRESS tAW
CE
tAS(6) R/W tDW DATA IN
3026 drw 09
tEW(2)
tWR
(3)
tDH
NOTES: 1. R/W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL. 3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
6.34
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
71V321X25 Symbol BUSY TIMING (M/S = VIH) S tBAA tBDA tBAC tBDC tAPS tBDD tWDD tDDD
BUSY BUSY BUSY BUSY
71V321X35 Min. -- -- -- -- 5 -- -- -- Max. 20 20 20 20 -- 30 60 45
71V321X55 Min. -- -- -- -- 5 -- -- -- Max. 30 30 30 30 -- 45 80 65 Unit ns ns ns ns ns ns ns ns
3026 tbl 11
Parameter Access Time from Address Match Disable Time from Address Not Matched Access Time from Chip Enable Low Disable Time from Chip Enable High Disable to Valid Data(3)
(1)
Min. -- -- -- -- 5 -- -- --
Max. 20 20 20 20 -- 30 50 35
Arbitration Priority Set-up Time(2)
BUSY
Write Pulse to Delay Data
Write Pulse to Delay Data(1)
NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. "X" in part numbers indicates power rating (S or L).
BUSY".
TIMING WAVE FORM OF WRITE WITH PORT-TO-PORT READ WITH BUSY (1,2,3)
tWC ADDR'A' MATCH tWP R/W'A' tDW DATAIN'A' tAPS ADDR'B'
(1)
tDH
VALID
MATCH t BDA tBDD
BUSY'B'
tWDD DATAOUT'B'
NOTES: 1. To ensure that the earlier of the two ports wins. 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
VALID tDDD
3026 drw 10
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH BUSY(3)
tWP R/ W'A' tWB
BUSY'B'
R/ W'B' tWH
(2) (1)
3026 drw 11
NOTES: 1. tWH must be met for BUSY. 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High. 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (1)
ADDR 'A' AND 'B' ADDRESSES MATCH
CE'B'
tAPS
(2)
CE'A'
tBAC tBDC
BUSY'A'
3026 drw 12
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1)
tRC ADDR'A'
(2)
OR
tWC ADDRESSES DO NOT MATCH
ADDRESSES MATCH tAPS
ADDR'B' tBAA tBDA
BUSY'B'
3026 drw 13
NOTES: 1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. 6.34 10
IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
71V321X25 Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 -- -- -- -- 25 25 0 0 -- -- -- -- 25 25 0 0 -- -- -- -- 45 45 ns ns ns ns
3026 tbl 12
71V321X35 Min. Max.
71V321X55 Min. Max. Unit
Parameter
Min.
Max.
NOTE: 1. "X" in part numbers indicates power rating (S or L).
TIMING WAVEFORM OF INTERRUPT MODE
INT SETS
tWC ADDR'A' INTERRUPT ADDRESS tAS(3) R/W'A' tINS
INT'B'
(2)
tWR
(4)
(3)
3026 drw 14
INT CLEARS
tRC ADDR'B' INTERRUPT CLEAR ADDRESS tAS (3)
OE'B'
tINR (3)
INT'A'
3026 drw 15
NOTES:. 1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.34
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLES TABLE I -- NON-CONTENTION READ/WRITE CONTROL(4)
Left or Right Port(1) R/W CE OE D0-7 W X H X Z X L H H H L L L X X L H Function Port Disabled and in PowerDown Mode, ISB2 or ISB4 Z CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 DATAIN Data on Port Written Into Memory(2) DATAOUT Data in Memory Output on Port(3) Z High-impedance Outputs
3026 tbl 13
NOTES: 1. A0L - A10L A0R - A10R. 2. If BUSY = VIL, data is not written. 3. If BUSY = VIL, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON'T CARE, 'Z' = High-impedance.
TABLE II -- INTERRUPT FLAG(1,4)
R/WL W L X X X
CEL CE
L X X L
Left Port
OEL OE
X X X L
A10L - A0L 7FF X X 7FE
INTL INT
X X L(3) H(2)
R/WR W X X L X
CER CE
X L L X
Right Port
OER OE
X L X X
A10L - A0R X 7FF 7FE X
INTR INT
L(2) H(3) X X
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
3026 tbl 14
NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH, 'L' = LOW, 'X' = DON'T CARE.
TABLE III -- ADDRESS BUSY ARBITRATION
Inputs Outputs
CEL CE
X H X L
CER CE
X X H L
A0L-A10L A0R-A10R
NO MATCH MATCH MATCH MATCH
BUSYL BUSYR BUSY (1) BUSY (1)
H H H (2) H H H (2)
Function Normal Normal Normal Write Inhibit(3)
3026 tbl 15 NOTES: 1. Pins BUSYL and BUSYR are both outputs for IDT71V321. BUSYX outputs on the IDT71V321 are push-pull, not open-drain outputs. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can not be low simultaneously.
6.34
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IDT71V321S/L HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT71V321 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT71V321 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted.
interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The Busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of busy logic is not required or desirable for all applications. In some cases it may be useful to logically OR the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. The Busy outputs on the IDT71V321 RAM are totem-pole type outputs and do not require pull-up resistors to operate. If these RAMs are being expanded in depth, then the Busy indication for the resulting array does not require the use of an external AND gate.
INTERRUPTS
If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CE = R/W = VIL per the Truth Table. The left port clears the interrupt by access address location 7FE access when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (8 bits) at 7FE or 7FF is userdefined, since it is an addressable SRAM location. If the
ORDERING INFORMATION
IDT XXXX A Device Type Power 999 Speed A Package A Process/ Temperature Range
Blank
Commercial (0C to +70C)
J PF
52-pin PLCC (J52-1) 64-pin TQFP (PN64-1)
25 35 55
Speed in nanoseconds
L S
Low Power Standard Power
71V321
16K (2K x 8-Bit) MASTER 3.3V Dual-Port RAM w/ Interrupt
3026 drw 16
6.34
13

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