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L6221A L6221AD L6221N
QUAD DARLINGTON SWITCH
.FOURNONI .OUTPUTVOLTAGEUPTO50V .OUTPUTCURRENTUPTO1. .VERYLOWSATURATI .TTLCOMPATI .I
ENABLE
NVERTING INPUTS WITH
8A ON VOLTAGE BLE INPUTS NTEGRAL FAST RECIRCULATION DIODES
Powerdip 12 + 2 + 2 Multiwatt 15
DESCRIPTION The L6221 monolithic quad darlington switch is designedfor high current, high voltageswitching applications. Each of the four switches is controlled by a logic input and all four are controlled by a common enableinput.All inputsareTTL-compatiblefor direct connection to logic circuits. Eachswitch consists of an open-collectordarlington transistor plus a fast diodefor switchingapplications with inductive device loads. The emitters of the four switches are commoned. Any number of inputsand outputs of the same device may be paralleled.
SO16+2+2 ORDERING NUMBERS: L6221A (Powerdip) L6221N (Multiwatt15) L6221AD (SO16+2+2)
BLOCK DIAGRAM
July 1998
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L6221A - L6221AD - L6221N
THERMAL DATA
Symbol R th j-pins R th j-case Rth j-amb Parameter Thermal Resistance Junction-pins Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Max. SO20 17 - 80 Powerdip Multiwatt15 14 - 80 - 3 35 Unit C/W C/W C/W
PIN CONNECTIONS (top views)
L6221A (Powerdip)
L6221AD (SO16+2+2)
OUT4 CLAMPB N.C. OUT3 GND GND OUT2 N.C. CLAMPA OUT1
1 2 3 4 5 6 7 8 9 10
D95IN231
20 19 18 17 16 15 14 13 12 11
IN4 IN3 N.C. ENABLE GND GND VS N.C. IN2 IN1
L6221N (Multiwatt-15)
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L6221A - L6221AD - L6221N
ABSOLUTE MAXIMUM RATINGS
Symbol Vo Vs VIN, VEN IC IC IC Top Tstg Isub Ptot Output Voltage Logic Supply Voltage Input Voltage, Enable Voltage Continuous Collector Current (for each channel) Collector Peak Current (repetitive, duty cycle = 10 % ton = 5 ms) Collector Peak Current (non repetitive, t = 10 s) Operating Temperature Range (junction) Storage Temperature Range Output Substrate Current Total Power Dissipation at at at at at at Tpins Tcase Tcase Tamb Tamb Tamb = = = = = = 90 90 90 70 70 70 C C C C C C (powerdip) (multiwatt) (SO20) (powerdip) (multiwatt) (SO20) Parameter Value 50 7 Vs 1.8 2.5 3.2 - 40 to + 150 - 55 to + 150 350 4.3 20 3.5 1 2.3 1 A A A C C mA W W W W W W Unit V V
TRUTH TABLE
Enable H H L
For each input : H = High level L = Low level
Input H L X
Power Out ON OFF OFF
PIN FUNCTIONS (see block diagram)
Name IN 1 IN 2 OUT 1 OUT 2 CLAMP A IN 3 IN 4 OUT 3 OUT 4 CLAMP B ENABLE VS GND Input to Driver 1 Input to Driver 2 Output of Driver 1 Output of Driver 2 Diode Clamp to Driver 1 and Driver 2 Input to Driver 3 Input to Driver 4 Output of Driver 3 Output of Driver 4 Diode Clamp to Driver 3 and Driver 4 Enable Input to All Drivers Logic Supply Voltage Common Ground 3/15 Function
L6221A - L6221AD - L6221N
ELECTRICAL CHARACTERISTICS Refer to the test circuit to Fig. 1 to Fig. 9 (VS = 5V, Tamb = 25oC unless otherwise specified)
Symbol VS Is VCE(sus) ICEX VCE(sat) Parameter Logic Supply Voltage Logic Supply Current Output Sustaining Voltage Output Leakage Current Collector Emitter Saturation Voltage (one input on ; all others inputs off.) All Outputs ON, IC = 0.7A All Outputs OFF VIN = VINL, VEN = VENH IC = 100 mA VCE = 50V VIN = VINL, VEN = VENH Vs = 4.5V VIN = VINH, VEN = VENH IC = 0.6A IC = 1A IC = 1.8A VIN = VINL, VEN = VENL 2.0 VIN = VINH, VEN = VENH VR = 50 V, VEN = VENH VIN = VINL IF = 1A IF = 1.8A Vp = 5V, RL = 10 Vp = 5V, RL = 10 VIN = 5V, VEN = 5V Iout = - 300 mA for Each Channel 10 100 1.6 2.0 2 5 120 46 1 Test Conditions Min . Typ . Max . 4.5 5.5 20 20 Unit V mA mA V mA V 1 1.2 1.6 0.8 - 100 V A V A A V V s s mA
VINL, VENL IINL, IENL VINL, VENH IINH , IENH IR VF td (on) td (off) Is
Input Low Voltage Input Low Current Input High Voltage Input High Current Clamp Diode Leakage Current Clamp Diode Forward Voltage Turn on Delay Time Turn off Delay Time Logic Supply Current Variation
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L6221A - L6221AD - L6221N
TEST CIRCUITS (X) = Referred to Multiwatt package X = Referred to Powerdip package Figure 1 : Logic supply current.
Set V IN = 4.5V,V EN = 0.8V,or V IN = 0.8V,V EN = 4.5V, for I S (all outputs off) Set V IN = 2V, V EN = 2V, for I S (all outputs on)
Figure 2 : Output Sustaining Voltage.
Figure 3 : Output Leakage Current.
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L6221A - L6221AD - L6221N
Figure 4 : Collector-emitter Saturation Voltage Figure 5 : Logic Input Characteristics
Set Set Set Set
S1, S2 open, VIN, VEN = 0.8V for IIN L, IEN L S1, S2 open, VIN, VEN = 2V for IIN H, IEN H S1, S2 close, VIN, VEN = 0.8V for V IN L, VEN L S1, S2 close, VIN, VEN = 2V for VIN H, VEN H
Figure 6 : Clamp Diode Leakage Current.
Figure 7 : Clamp Diode Forward Voltage.
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L6221A - L6221AD - L6221N
Figure 8 : Switching Times Test Circuit. Figure 9 : Switching TImes Waveforms.
Figure 10 : Allowed Peak Collector Current versus Duty Cycle for 1, 2, 3 or 4 Contemporary Working Outputs (L6221A)
Figure 11 : Allowed Peak Collector Current versus Duty Cycle for 1, 2, 3 or 4 Contemporary Working Outputs (L6221N)
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L6221A - L6221AD - L6221N
Figure 12 : Collector Saturation Voltage versus Collector Current Figure 13 : Free-wheeling Diode Forward Voltage versus Diode Current
Figure 14 : Collector Saturation Voltage versus Junction Temperature at IC = 1A
Figure 15 : Free-wheeling Diode Forward Voltage versus Junction Temperature at IF = 1A
Figure 16 : Saturation Voltage vs. Junc-
Figure 17 : Free-wheeling Diode Forward
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L6221A - L6221AD - L6221N
APPLICATION INFORMATION When inductive loads are driven by L6221A/N, a zener diode in series with the integral free-wheeling diodes increases the voltage across which energy stored in the load is discharged and therefore speeds the current decay (fig. 18). For reliability it is suggestedthat the zener is chosen so that Vp + Vz < 35 V. The reasons for this are two fold : 1) The zener voltage changes in temperature and current. 2) The instantaneouspowermust belimited to avoid the reverse second breakdown. Figure 18.
Figure 19 : Driver for Solenoids up to 3A.
Some care must be taken to ensure that the collectors are placed close togetherto avoid differentcurrent partitioning at turn-off. We suggest to put in parallel channel 1 and 4 and channel2 and 3 as shown in figure 19 for the similar
electrical characteristics of the logic section(turn-on and turn-off delay time) and the power stages (collector saturation voltage, free-wheeling diode forward voltage).
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L6221A - L6221AD - L6221N
Figure 20 : Saturation Voltage versus Collector Current Figure 21 : Peak Collector Current versus Duty Cycle for 1 or 2 Paralleled Outputs Driven (L6221A)
Figure 22 : Peak Collector Current versus Duty Cycle for 1 or 2 Paralleled Outputs Driven (L6221N)
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L6221A - L6221AD - L6221N
MOUNTING INSTRUCTION The Rth j-amb of the L6221A can be reduced by solderingthe GND pins to a suitablecopperarea of the printed circuit board (Fig. 23) or to an external heatsink (Fig. 24). The diagram of figure 25 shows the maximum dissipable power Ptot and the Rth j-amb as a function of the side " " of two equal square copper areas havFigure 23 : Example of P.C. Board Copper Area Which is Used as Heatsink
ing a thickness of 35 (1.4 mils). During soldering the pins temperature must not exceed 260 C and the soldering time must not be longer than 12 seconds. The external heatsink or printed circuit copper area must be connected to electrical ground. Figure 24 : External Heatsink Mounting Example
Figure 25 : Maximum Dissipable Power and Junction to Ambient Thermal Resistance versus Side " "
Figure 26 : Maximum Allowable Power Dissipation versus Ambient Temperature
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L6221A - L6221AD - L6221N
POWERDIP 16 PACKAGE MECHANICAL DATA
DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.30 1.27 8.80 2.54 17.78 7.10 5.10 0.130 0.050 0.38 0.51 0.85 0.50 0.50 20.0 0.346 0.100 0.700 0.280 0.201 0.015 1.40 mm TYP. MAX. MIN. 0.020 0.033 0.020 0.020 0.787 0.055 inch TYP. MAX.
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L6221A - L6221AD - L6221N
MULTIWATT 15 PACKAGE MECHANICAL DATA
DIM. MIN. A B C D E F G G1 H1 H2 L L1 L2 L3 L4 L7 M M1 S S1 Dia1 21.9 21.7 17.65 17.25 10.3 2.65 4.25 4.63 1.9 1.9 3.65 4.55 5.08 17.5 10.7 22.2 22.1 0.49 0.66 1.02 17.53 19.6 20.2 22.5 22.5 18.1 17.75 10.9 2.9 4.85 5.53 2.6 2.6 3.85 0.862 0.854 0.695 0.679 0.406 0.104 0.167 0.182 0.075 0.075 0.144 0.179 0.200 0.689 0.421 0.874 0.870 1.27 17.78 1 0.55 0.75 1.52 18.03 0.019 0.026 0.040 0.690 0.772 0.795 0.886 0.886 0.713 0.699 0.429 0.114 0.191 0.218 0.102 0.102 0.152 0.050 0.700 mm TYP. MAX. 5 2.65 1.6 0.039 0.022 0.030 0.060 0.710 MIN. inch TYP. MAX. 0.197 0.104 0.063
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L6221A - L6221AD - L6221N
SO20 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 mm TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299
0 (min.)8 (max.)
L
h x 45
A B e K H D A1 C
20
11 E
1
10
SO20MEC
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L6221A - L6221AD - L6221N
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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