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7DEOH ica /;7eee 5HFHLYH 7LPLQJ &KDUDFWHULVWLFV o6HH )LJXUH iao 3DUDPHWHU Receive clock period DSX-1 E1 Receive clock duty cycle Receive clock pulse width High Receive clock pulse width Low RPOS / RNEG to RCLK rising setup time RCLK rising to RPOS / RNEG hold time DSX-1 E1 DSX-1 E1 DSX-1 E1 DSX-1 E1 6\P W3: W3: 5&/.G W3:+ W3:+ W3:/ W3:/ W685 W685 W+5 W+5 0LQ eae eea ei eea iae eea iae ei ei ei ei 7\Si cea eaa ei eee eee eee eee eaee iae eaee iae 0D[ aeie eeae ci eaa eae eaa eae 8QLWV QV QV QV QV QV QV QV QV QV QV QV 7HVW &RQGLWLRQV Elastic store not in overflow or underflow.
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Jitter
LXT332 Device Jitter Performance Loop Mode
Pub 62411 Dec 1990
28 UI 18 UI 10 UI
1.5 UI @ 20 Hz
1 UI 0.4 UI .1 UI 1 Hz 10 Hz
ITU G.823 Mar 1993
30 kHz
1.5 UI @ 2.9 kHz 0.2 UI @ 18 kHz
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