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| FEDL7731-02-04 1 Semiconductor MSM7731-02 Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free This version: Jan. 2000 Previous version: Jan. 2000 GENERAL DESCRIPTION The MSM7731 is an IC device developed for portable, handsfree communication with built-in line echo canceler, acoustic echo canceler, and transmission signal noise canceler. Built-in to the voice signal interface is a linear CODEC for the analog interface on the acoustic-side, and a linear CODEC for the analog interface on the line-side. On the line-side, in addition to the analog interface, there is also a -law PCM/16-bit linear digital interface. Equipped with gain and mute controls for data transmission and reception, a -law PCM/16-bit linear digital interface for memo recording and message output, and transfer clock and sync clock generators for digital communication, this device is ideally suited for a handsfree system. FEATURES * Single 3 V Power Supply Operation (2.7 to 3.6 V) * Built-in 2-channel (line and acoustic) echo canceler Echo attenuation : 35 dB (typ.) for white noise Cancelable echo delay time : Line echo canceler + acoustic echo canceler Acoustic echo canceler only * Built-in transmission signal noise canceler Noise attenuation : 17 dB (typ.) for white noise 40 dB (typ.) for single tone * Built-in 2-channel CODEC Synchronous transmission and reception enables full duplex operation * Built-in analog input gain amp stage (max. gain = 30 dB) * Analog output configuration : Push-pull drive (can drive a 1.2 k load) * Built-in transmit slope filter * Digital interface coding formats : -law PCM, 16-bit linear (2's complement) * Digital interface sync formats : Normal-sync, short-frame-sync * Built-in digital transmission clock generators Sync clock (SYNC) : 8 kHz output Transmission clock (BCLK) : 64 kHz output (-law PCM)/128 kHz output (16-bit linear) * Digital transmission rate External input : 64 to 2048 kbps Internal generation : 64 kbps (-law PCM)/128 kbps (16-bit linear) * Fixed digital interface sync clock (SYNC) enables automatic power-down * Master clock frequency : 19.2 MHz Compatible with crystal oscillator and crystal * Low power consumption Operating mode : typ. 35 mA (when VDD = 3.0 V in a silent mode) Power down operation : typ. 0.02 mA (when VDD = 3.0 V in a silent mode) * Control by both the serial microcomputer interface and parallel port is possible * Transmit/receive mute function, transmit/receive programmable gain setting * Package : 64-pin plastic QFP (QFP64-P-1414-0.80-BK)(Product name: MSM7731-02GA) : Tlined = 27 ms (max.) Tacoud = 59 ms - Tlined (max.) : Tacoud = 59 ms (max.) 1/53 Linear Codec (Acoustic side) Slope Filter SinA LPF DAC RC LPF - + 1.2 k LPWI LOUT 1 Semiconductor Acoustic Echo Canceler GPADA BLOCK DIAGRAM BPF Center Chip ATTsA SoutA TPAD RinL Power Calc. Howling Detector Double Talk Det Line Echo RoutL Canceler ATTrL GainL Linear Codec (Line side) + LPADA - AIN Noise Canleler - + ADC AGSX GPADNC LPADNC Line Adaptive FIR Filter RC LPF Acoustic Adaptive FIR Filter (AAFF) LVFRO AVFRO (LAFF) RC LPF Power Calc. Howling Detector RC LPF ADC - + BPF LGSX LIN APWI Center Chip DAC - + Double Talk Det LPADL AOUT RinA SoutL RPAD GPADL ATTsL - + 1.2 k SinL LPF GainA ATTrA RoutA SG EC/NC/SF/PAD Controller VREF MCU Interface LEC Controller P/S &S/P LINEEN Clock Gen P/S Timing Gen AEC Controller &S/P LTHR LGC LATT LHD ATHR AGC AATT AHD PCMO PCMI PCMEO PCMEI DEN EXCK DIN DOUT MCUSEL SYNC SYNCSEL BCLK CLKSEL PCMSEL NCPAD1,2 NCSEL1,2 RPAD1-4 TPAD1-4 ECSEL GLPADTHR SLPTHR RST PDN/RST MCK/X1 X2 AGND AVDD DGND1,2 DVDD1,2 TEST1-4 TEST9 FEDL7731-02-04 MSM7731-02 2/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 PIN CONFIGURATION (TOP VIEW) 55 PDN/RST 61 SLPTHR 62 NCSEL1 56 NCSEL2 51 CLKSEL 49 PCMEI 60 TEST1 59 TEST2 58 TEST3 57 TEST4 53 SYNC 64 EXCK 52 BCLK 50 PCMI 54 RST 63 DIN ECSEL MCUSEL AHD NCPAD2 AATT AGC DGND1 ATHR LHD NCPAD1 LATT LGC LTHR RPAD4 DVDD1 RPAD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 PCMEO 47 PCMO 46 PCMSEL 45 SYNCSEL 44 DOUT 43 DEN 42 DVDD2 41 GLPADTHR 40 TEST9 39 LINEEN 38 AGND 37 LOUT 36 LPWI 35 LVFRO 34 LGSX 33 LIN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RPAD2 RPAD1 DGND2 TPAD4 TPAD3 TPAD2 TPAD1 MCK/X1 X2 AVDD AGSX AIN AVFRO APWI AOUT SG 64-Pin Plastic QFP 32 3/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 PIN FUNCTIONAL DESCRIPTION AIN, AGSX These are the acoustic analog input and level adjusting pins. The AIN pin is connected to the inverting input of the internal amp and the AGSX pin is connected to the amp output. For level adjustment, refer to the diagram below (Figure 1). At power-down reset, the AGSX pin goes to a high impedance state. AVFRO, AOUT, APWI These are acoustic analog output and level adjusting pins. The AVFRO pin is an audio output and can directly drive 20 k. The AOUT pin is an analog output and can directly drive a load of 1.2 k. For level adjustment, refer to the diagram below (Figure 1). At power-down reset, these output pins go to a high impedance state. LIN, LGSX These are the line analog input and level adjusting pins. The LIN pin is connected to the inverting input of the internal amp and the LGSX pin is connected to the amp output. For level adjustment, refer to the diagram below (Figure 1). At power-down reset, the LGSX pin goes to a high impedance state. If LIN is not used, short the LIN and LGSX together. LVFRO, LOUT, LPWI These are acoustic analog output and level adjusting pins. The LVFRO pin is an audio output and can directly drive 20 k. The LOUT pin is an analog output and can directly drive a load of 1.2 k. For level adjustment, refer to the diagram below (Figure 1). At power-down reset, these output pins go to a high impedance state. If LOUT is not used, short the LPWI and LOUT pins together. LINEEN This is the power-down control pin for the line CODEC. A logic "0" continues normal operation and a logic "1" power down only the line CODEC. If the line CODEC is not used, power down the line CODEC and short the LIN pin to the LGSX pin and the LPWI pin to the LOUT pin. This procedure results in the low consumption of electrical power. At power-down, the output pins go to a high impedance state. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7). This pin is ORed with CR0-B5 of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". VAGSX/Vi = R2/R1 30 VAGSX = 1.3 VPP R2 20 k MIC Vi C1 R1 0.1 F + - 10 F R3 C2 SP VO/VAVFRO = R4/R3 2 VO = 2.6 VPP, VAVFRO = 1.3 VPP R3, R4 20 k Acoustic Side (Mic, Speaker) Transmit Signal R4 Vo Acoustic CODEC AGSX R2 AIN SG AVFRO APWI AOUT - + - + to ENCODER VREF LVFRO LPWI LOUT LINEEN Line CODEC LGSX LIN Same as acoustic analog interface SPamp Receive Signal Line Side (Hand Set) Figure 1 Analog Interface 4/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 AGND This is analog ground pin. DGND1, DGND2 These are the digital ground pins. AVDD This is the analog +3 V power supply pin. DVDD1, DVDD2 These are the digital +3 V power supply pins. SG This is the output pin for the analog signal ground potential. The output voltage is approximately 1.4 V. Insert 10 F and 0.1 F ceramic bypass capacitors between the AGND and SG pin. At power-down rest, this output becomes 0 V. PDN/RST PDN RST This is the power-down reset control input pin. If a logic "0" is input to this pin, the device enters the power-down state. At this time, all control register bits, internal variables, and coefficients of echo cancelers and noise cancelers will be reset. After the power-down reset state is released, the device enters the initial mode (refer to the CR0 control register description). During normal operation, set this pin to a logic "1". The PDN/RST pin is ORed (negative logic) with CR0-B7 of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". MCK/X1 This is the master clock input pin. The clock frequency is 19.2 MHz. The input clock may be asynchronous with respect to the SYNC signal or the BCLK signal. Refer to Figure 2 (a) for an example application of an external clock and Figure 2 (b) for an example oscillator circuit. X2 This is the crystal oscillator output pin. If an existing external clock is to be used, leave this pin open and input the clock to the MCK pin. Refer to Figure 2 (b) for an example oscillator circuit. MCK/X1 X2 MCK/X1 R X2 X'tal (19.2 MHz) C 10 pF T.B.D R 1 M T.B.D X'tal C C HC-49/U CX-91F Figure 2 (a) External Clock Figure2 (b) Application Example Oscillator Circuit Example 5/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 SYNC This is the 8 kHz sync signal I/O pin for digital data communication. This pin is switched to unction as an input or output by the CLKSEL pin. If the internal clock mode is selected by the CLKSEL pin, an 8 kHz clock synchronized to be BCLK signal is output and digital data communication is performed. If the external clock mode is selected by the CLKSEL pin, this pin becomes an input that requires an 8 kHz clock input synchronized to be BCLK pin, and digital data communication is performed based on this input clock. This pin enables automatic power-down control. Fixing this pin to a logic "1" or logic "0" causes this device to enter the power-down state. Two kinds of power-down modes can be selected by the SYPDN (CR11-B0) bit of the control register. For the power-down mode, refer to the description of control register CR11. BCLK This is the shift clock I/O pin for digital data communication. This pin is switched to function as an input or output by the CLKSEL pin. If the internal clock mode is selected by the CLKSEL pin, a 64 kHz or 128 kHz clock synchronized to the SYNC signal is output and digital data communication is performed. Switching between 64 kHz and 128 kHz is performed by the PCMSEL pin or PCMSEL (CR11-B1) bit. If -law PCM is selected by the PCMSEL pin or PCMSEL bit, a 64 kHz clock is output. Or, if 16-bit linear mode is selected, a 128 kHz clock is output. If the external clock mode is selected by the CLKSEL pin, this pin becomes an input that requires a clock input synchronized to the SYNC. In this case, the clock frequency range is from 64 kHz to 2048 kHz. CLKSEL This pin selects internal or external clock modes for the SYNC and BCLK signals. A logic "0" selects the internal clock mode. At this time, SYNC and BCLK pins are configured as output pins and each internally generated clock is output to perform digital data communication. A logic "1" selects the external clock mode and configures the SYNC and BCLK pins as input pins. At this time, digital data communication is performed with the externally input SYNC and BCLK clocks. If digital data communication is not used, set this pin to a logic "0" to select internal clocks. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7). PCMI This is the digital receive signal input pin on the line-side. This input signal is shifted at the rising edge of the BCLK signal and input. The beginning of digital data is identified on the rising edge of the SYNC signal. The coding format can be selected as -law PCM or 16-bit linear (2's complement) by the PCMSEL pin or PCMSEL (CR11-B1) bit. If the PCMI pin is not used, set it to a logic "1" if -law PCM has been selected, or a logic "0" if 16-bit linear mode has been selected. The sync format can be selected as normal-sync or short-frame-sync by the SYNCSEL pin. Refer to Figure 3 for the timing. This digital input signal is added internally to the CODEC digital output signal. Be careful of overflow when using the CODEC. PCMO This is the digital transmit signal output pin on the line-side. This output signal is synchronized to the rising edge of the BCLK and SYNC signals and then output. When not used for output, this pin is in the high impedance state. It is at high impedance during the power-down reset and the initial modes. The coding format can be selected as -law PCM or 16-bit linear (2's complement) by the PCMSEL pin or PCMSEL (CR11-B1) bit. The sync format can be selected as normal-sync or short-frame-sync by the SYNCSEL pin. Refer to Figure 3 for the timing. 6/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 PCMEI This is the massage signal input pin. Use this pin when a massage is output to the speaker on the acoustic-side. This input signal is shifted at the rising edge of the BCLK signal and then input. The beginning of digital data is identified on the rising edge of the SYNC signal. The coding format can be selected as -law PCM or 16-bit linear (2's complement) by the PCMSEL pin or PCMSEL (CR11-B1) bit. If the PCMEI pin is not used, set it to a logic "1" if -law PCM has been selected, or a logic "0" if 16-bit linear mode has been selected. The sync format can be selected as normal-sync or short-frame sync by the SYNCSEL pin. Timing is the same as for the PCMI pin (refer to Figure 3). This digital input signal is added internally to the echo canceler output signal. Be careful of overflow during telephone conversations. PCMEO This output pin is for memo recording. Use it with the memo function. This output signal is synchronized to the rising edge of the BCLK an SYNC signals and then output. When not used for output, this pin is in the high impedance state. It is also at high impedance during the power-down reset and the initial modes. The coding format can be selected as -law PCM or 16-bit linear (2's complement) by the PCMSEL pin or PCMSEL (CR11-B1) bit. The sync format can be selected as normal-sync or short-frame-sync by the SYNCSEL pin. Timing is the same as for the PCMO pin (refer to Figure 3). SYNCSEL This is the sync timing selection pin for digital data communication. A logic "0" selects normal-sync timing and a logic "1" selects short-frame-sync timing. Refer Figure 3 for the timing. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7) PCMSEL This is the coding format selection pin for digital data communication. A logic "1" selects -law PCM and a logic "0" selects 16-bit linear (2's complement) coding format. When an internal clock is selected, the BCLK signal determines the output clock frequency. If the digital interface is not used, set this pin to logic "0" to select 16-bit linear coding format. If the pin setting is changed, reset must be performed by either the PDN/RST pin or the PDN/RST bit (CR0-B7). This pin is logically ORed with the PCMSEL bit (CR11-B1). Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". SLPTHR This is the "through mode" control pin for the transmit slope filter. In the "through mode", the filter is halted and data is directly output. A logic "0" selects the normal mode (slope filter operation) and a logic "1" selects the "through mode". The slope filter decreases noises of low frequencies and improves speech quality. Refer to the slope filter frequency characteristics. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. For further details, refer to the electrical characteristics. This pin is ORed with the CR1-B1 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". 7/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 SYNC BCLK PCMI PCMEI PCMO PCMEO D15 D14 D13 D12 D15 D14 D13 D12 D2 D1 D0 D2 D1 D0 D15 D14 D15 D14 Hi-Z (a) 16-bit linear coding format timing (normal sync) SYNC BCLK PCMI PCMEI PCMO PCMEO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D7 D6 Hi-Z (b) -law PCM coding format timing (normal sync) SYNC BCLK PCMI PCMEI D15 D14 D13 D3 D2 D1 D0 D3 D2 D1 D0 D15 D15 PCMO D15 D14 D13 PCMEO Hi-Z Hi-Z (c) 16-bit linear coding format timing (short-frame sync) SYNC BCLK PCMI PCMEI D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 PCMO PCMEO Hi-Z D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z (d) -law PCM coding format timing (short-frame sync) Figure 3 Digital Interface Timing 8/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 ECSEL This is the echo canceler mode selection pin. A logic "1" selects the single echo canceler mode and a logic "0" selects the dual echo canceler mode. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7). If the single echo canceler mode is selected, echo canceler control on the line-side is unnecessary. This pin is ORed with the CR0-B0 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". LTHR/ATHR This is the "through mode" control pin for the echo canceler. In the "through mode", SinL/A and RinL/A data is directly output to SoutL/A and RoutL/A respectively while each respective echo coefficient is maintained. A logic "0" selects the normal mode (echo canceler operation) and a logic "1" selects the "through mode". In the through mode, the functions of HD, HLD, ATT and GC are invalid. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin is ORed with the CR4-B7 and CR5-B7 bits of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". LHD/AHD LHD AHD This pin turns ON or OFF the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. A logic "0" turns the function ON and a logic "1" turns the function OFF. This function is valid when the LTHR/ATHR pin is in the normal mode. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin is ORed with the CR4-B4 and CR4-B4 and CR5-B4 bits of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". LATT This pin turns ON or OFF the ATT function to prevent howling by means of attenuators (ATTsL, ATTrL) provided in the RinL inputs and SoutL outputs of the echo canceler. A logic "0" turns ON and a logic "1" turns OFF the ATT function. If input is only to RinL, the ATTsL for SoutL is activated. If input is only to SinL, or if there is input to both SinL and RinL, the ATTrL for RinL input is activated. The ATT value of each attenuator is approximately 6 dB. This function is valid when the LTHR pin is in the normal mode. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin setting is logically ORed with the CR4-B1 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". AATT This is the ATT atlenuation selection pin to prevent howling by means of attenuators (ATTsA, ATTrA) provided in the RinA inputs and SoutA outputs of the echo canceler. A logic "0" selects 6 dB and a logic "1" selects 12 dB. If input is only to RinA, the ATTsA for SoutA is activated. If input is only to SinA, or if there is input to both SinA and RinA, the ATTrA for RinA input is activated. This function is valid when the ATHR pin is in the normal mode. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin setting is logically ORed with the CR5-B1 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". 9/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 LGC/AGC LGC AGC This pin turns ON or OFF the gain control function to control the input level and prevent howling by means of gain controls (GainL/A) provided in the RinL/A inputs of the echo canceler. The gain controller adjusts the RinL/A input level when it is -10 dBm0 or above, and it has the control range of 0 to -8.5 dB. A logic "0" turns the function ON and a logic "1" turns the function OFF. This function is valid when the LTHR/ATHR pin is in the mormal mode. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin is ORed with the CR4-B0 and CR5-B0 bits of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". Notes: Lxx/Axx : In the above, Lxx refers to line echo canceler control pins and Axx to acoustic echo canceler control pins. xxL/xxA : In the above pin descriptions, xxL refers to line echo canceler functions and xxA to acoustic echo canceler functions. GLPADTHR This is the mode control pin for the attenuators (LPADL/A) provided in the SinL/A inputs and the amplifiers (GPADL/A) provided in the SoutL/A outputs of the echo canceler. A logic "0" selects the "through mode" and a logic "1" selects the normal mode (PAD operation). The levels are set by the CR10 register. Settings of 18, 12, 6 and 0 dB are possible. The default setting is 12 dB. If the echo return loss (value of returned echo) is amplified, set the LPAD level such that echo return loss will be attenuated. It is recommended to set the GPAD level to the positive level equal to the LPAD level. If the pin setting is changed, the coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin is ORed with the CR1-B2 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". RST This input pin resets coefficients of the echo canceler and noise canceler. A logic "0" causes the reset state to be entered. At this time, the filter coefficients for the echo canceler and noise canceler are reset. Control register contents are preserved. While reset is being processed, there is not sound. During normal operation, set this pin to a logic "1". Use this pin in cases where the echo path changes (due to line switching during a telephone conversation, etc.), or when resuming telephone communication. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. This pin is ORed (negative logic) with the CR0-B6 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". 10/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 NCSEL1, NCSEL2 These are the noise attenuation selection pins. In the "through mode" the noise canceler is halted and data is directly output. In the "normal mode" the noise canceler operates normally. Since the noise attenuation in the normal mode is selected after the initial mode has been released, the change of the noise attenuation during normal operation is invalid. If the noise attenuation is changed, reset must be activated by the RDN/RST pin or the PDN/RST bit (CR0-B7). Changing to the through mode during normal operation and returning to the normal mode are possible. The NCSEL1 pin is ORed with the CR1-B0 bit of the control register and the NCSEL2 pin is ORed with the CR12-B2 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". Note: Since there is a trade-off between noise attenuation and sound quality after canceling the noise, select the noise attenuation appropriate to the sound quality. NCSEL2 0 1 1 0 NCSEL1 0 1 0 1 NC Mode Normal Mode Normal Mode Normal Mode Through Mode Attenuation (dB) 17 13.5 8 -- Quality Better Best -- NCPAD1, NCPAD2 These are the noise canceler I/O gain adjusting pins. The gain adjustment is valid for tone control after canceling the noise. The bigger the input level of the noise canceler is, the better the sound quality is. The NCPAD1 pin is ORed with the CR4-B2 bit of the control register and the NCPAD2 pin is ORed with the CR5-B2 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". NCPAD2 0 0 1 1 NCPAD1 0 1 0 1 GPADNC (dB) 0 6 12 18 LPADNC (dB) 0 -6 -12 -18 DEN, DEN EXCK, DIN, DOUT This is the serial port for the microcontroller interface. 13 bytes of control registers are provided in this IC device. There pins are used to write and read data from an external microcontroller. The DEN pin is an enable signal input pin, the EXCK pin is a clock signal input pin for data shifting, the DIN pin is an address and data input pin, the DOUT pin is a data output pin. If the mirrocontroller interface is not used, set the DEN pin to a logic "1" and the EXCK and DIN pins to a logic "0". In addition, use the MCUSEL pin to specify the "unused" setting of the microcontroller interface. Figure 4 shows the input timing. MCUSEL This pin selects whether the microcontroller interface is used or unused. A logic "0" specifies that the microcontroller interface is used and a logic "1" specifies that it is not used. If the microcontroller interface is not used, this pin must be set to a logic "1". This pin is ORed with the CR0-B1 bit of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". 11/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 DEN EXCK DIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 W A6 A5 A4 A3 A2 A1 A0 Hi-Z B7 B6 B5 B4 B3 B2 B1 B0 (a) Data Write Timing 1 (8-bit MCU) DEN EXCK DIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 W A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Hi-Z (b) Data Write Timing 2 (16-bit MCU) DEN EXCK DIN DOUT 1 R 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A6 A5 A4 A3 A2 A1 A0 Hi-Z B7 B6 B5 B4 B3 B2 B1 B0 Hi-Z (c) Data Read Timing 1 (8-bit MCU) DEN EXCK DIN DOUT 1 R 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A6 A5 A4 A3 A2 A1 A0 Hi-Z B7 B6 B5 B4 B3 B2 B1 B0 Hi-Z (d) Data Read Timing 2 (16-bit MCU) Figure 4 Microcontroller Interface I/O Timing 12/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 RPAD4, RPAD3, RPAD2, RPAD1 These are the receive signal gain adjusting and mute setting pins. Refer to Table 1 for the settings. Set these pins to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. For further details, refer to the electrical characteristics. These pins are ORed with the CR2-B3, B2, B1 and B0 bits of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". TPAD4, TPAD3, TPAD2, TPAD1 These are the transmit signal gain adjusting and mute setting pins. Refer to Table 1 for the settings. Set these pins to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 s or longer. For further details, refer to the electrical characteristics. These pins are ORed with the CR3-B3, B2, B1 and B0 bits of the control register. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". Table 1 RPAD/TPAD Setting RPAD4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RPAD3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 RPAD2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 RPAD1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TPAD4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TPAD3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 TPAD2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 TPAD1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Level 21 dB 18 dB 15 dB 12 dB 9 dB 6 dB 3 dB 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB MUTE TEST1-4 Test inputs. Set these pins to a logic "0". TEST9 Test output. 13/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Digital Input Voltage Digital output Voltage Storage Temperature Symbol VDD VIN VOUT TSTG Condition -- -- -- -- Rating -0.3 to +5.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 Unit V V V C RECOMMENDED OPERATING CONDITION Parameter Power Supply Voltage Operating Temperature Input High Voltage Symbol VDD Ta VIH Condition -- -- SYNC, BCLK input pins MCK/X1 input pin Other digital input pins Input Low Voltage Digital Input Rise Time Digital Input Fall Time Master Clock Frequency Master Clock Duty Ratio Bit Clock Frequency Bit Clock Duty Ratio Synchronous Signal Frequency Synchronous Signal Width Transmit/Receive Sync Signal Setting Time VIL tIR tIf fMCK DMCK fBCK DCK fSYNC tWS tBS tSB RDL Digital Output Load CDL1 CDL2 Bypass Condenser for SG CSG MCK/X1 input pin Other digital input pins All digital inputs All digital inputs MCK/X1 MCK/X1 BCLK (during output) BCLK (during output) SYNC (during output) SYNC (during output) BCLK to SYNC (during input) SYNC to BCLK (during input) DOUT, PCMO, PCMEO DOUT, PCMO, PCMEO SYNC, BCLK (during output) SG to AG Min. 2.7 -40 0.5xVDD 0.65xVDD 0.45xVDD 0 -- -- -100 ppm 40 64 40 -100 ppm 1 BCLK 100 100 1 -- -- 10+0.1 -- -- -- +19.2 50 -- 50 8 -- -- -- -- -- -- -- 0.35xVDD 0.16xVDD 20 20 +100 ppm 60 2048 60 +100 ppm 100 -- -- -- 50 20 -- V ns ns MHz % kHz % kHz ns ns ns k pF pF F -- VDD V Typ. -- +25 Max. 3.6 +85 Unit V C 14/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 to 3.6 V, Ta = -25 to +85C) Parameter Power Supply Current 1 Power Supply Current 2 Input Leakage Current High Level Digital Output Voltage Low Level Digital Output Voltage Digital Output Leakage Current Input Capacitance Symbol IDD1 IDD2 IIH IIL VOH VOL IO CIN Condition Operating, no signal (VDD = 3.0 V) Power down mode (VDD = 3.0 V, MCK = 0 V) VI = VDD VI = 0 V IOH = 0.4 mA (other than x2) IOL = 3.2 mA (other than x2) DOUT, PCMO, PCMEO -- Min. -- -- -- -- 0.5xVDD --0 -- -- Typ. 35 0.02 -- -- -- 0.2 -- 5 Max. 50 1 2 2 VDD 0.4 10 -- Unit mA mA A A V V A pF Analog Interface Characteristics (VDD = 2.7 to 3.6 V, Ta = -25 to +85C) Parameter Input Resistance Symbol RINA RINL RLA1 Output Load Resistance RLA2 RLL1 RLL2 Output Load Capacitance CLA1 CLL1 VOA1 Output Voltage Level (*1) VOA2 VOL1 VOL2 VOFA1 Offset Voltage VOFA2 VOFL1 VOFL2 SG Output Voltage SG Output Impedance VSG RSG Condition AIN, APWI LIN, LPWI AGSX, AVFRO AOUT LGSX, LVFRO LOUT AGSX, AVFRO, AOUT LGSX, LVFRO, LOUT AGSX, AVFRO AOUT LGSX, LVFRO LOUT AVFRO AOUT LVFRO LOUT SG SG RL = 20 k RL = 1.2 k RL = 20 k RL = 1.2 k Min. 10 10 20 1.2 20 1.2 -- -- -- -- -- -- -100 -20 -100 -20 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.4 40 Max. -- -- -- -- -- -- 100 100 1.3 2.6 1.3 2.6 +100 +20 +100 +20 -- 80 Unit M M k k k k pF pF Vpp Vpp Vpp Vpp mV mV mV mV V k Note*1: 0.320 Vrms = 0 dBm0, +3.14 dBm0 = 1.30 VPP 15/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Digital Interface Characteristics (1/3) (VDD = 2.7 to 3.6 V, Ta = -25 to +85C) Parameter Power-down/Reset Signal Pulse Width Power-down/Reset Start Time Power down/Reset End Time Power-down/Reset Internal Setting Time Control Pulse Width Control Start Time Control End Time Symbol tRSTW tPDND tPDNH tPDNS tPARW tPARD tPARH (*2) Condition PDN/RST pin PDN/RST control bit PDN/RST pin and PDN/RST control bit PDN/RST pin and PDN/RST control bit SYNC pin (input mode) Min. 1 1.6 -- -- 140 250 -- -- Typ. -- -- -- -- -- -- -- Max. -- 50 200+ 180 -- 250 250 Unit S nS mS S S S S : Crystal activation PDN/RST Timing PDN/RST pin PDN/RST control bit Internal Operation PCMO, PCMEO tPDND Power Down Hi-Z tPDNH Initial Mode TRSTW PDN/RST set timing SYNC (Ext. clock) BCLK (Ext. clock) PDN/RST control bit (Internal Write) tPDNS Control Timing (*2) Pin/control bit tPARW tPARD tPARH Internal operation Internal processing Note*2: Applies to the following pins/control bits: LINEEN, SLPTHR, NCTHR, GLPADTHR, TPAD6-1, RPAD6-1, RST, ATHR, AATT, AHLD, AHD, AGC, LTHR, LATT, LHLD, LHD, LGC pins, and control bits. 16/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Digital Interface Characteristics (2/3) (VDD = 2.7 to 3.6 V, Ta = -25 to +85C) Parameter Symbol Condition CDL = 20 pF (output mode, PCM) CDL = 20 pF (output mode, linear) CDL = 20 pF (output mode) CDL = 20 pF (output mode) CDL = 20 pF (output mode) BCLK to SYNC (output mode) SYNC to BCLK (output mode) -- -- RDL = 1 k, CDL = 50 pF RDL = 1 k, CDL = 50 pF RDL = 1 k, CDL = 50 pF RDL = 1 k, CDL = 50 pF Min. -- -- 40 -- 40 100 100 100 100 -- -- -- -- Typ. 64 128 50 8 50 -- -- -- -- -- -- -- -- Max. -- -- 60 -- 60 -- -- -- -- 100 100 100 100 Unit kHz kHz % kHz % ns ns ns ns ns ns ns ns Bit Clock Frequency fBCK Bit Clock Duty Ratio Sync signal frequency Sync signal Duty Ratio Transmit/Receive Sync Signal Setting Time Input Setup Time Input Hold Time Digital Output Delay Time Digital Output Hold Time DCK fSYNC DSYNC tBS tSB tDS tDH tSDX tXD1 tXD2 tXD3 Digital Input Timing (Normal-sync) BCLK 0 tBS 1 tSB tWS SYNC PCMI PCMEI 2 3 4 5 6 7 8 9 10 tDS MSB tDH LSB Digital Input Timing (Short-frame-sync) BCLK 0 tBS 1 tSB tWS SYNC PCMI PCMEI 2 3 4 5 6 7 8 9 10 tDS MSB tDH LSB 17/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Digital Output Timing (Normal-sync) 0 tBS 1 tSB tWS SYNC PCMO PCMEO tSDX tXD1 MSB tXD2 LSB tXD3 Hi-Z 2 3 4 5 6 7 8 9 10 BCLK Hi-Z Digital Output Timing (Short-frame-sync) BCLK 0 tBS 1 tSB 2 tWS 3 4 5 6 7 8 9 10 SYNC PCMO PCMEO tXD1 MSB Hi-Z tXD2 tXD3 LSB Hi-Z Digital Interface Characteristics (3/3) (VDD = 2.7 to 3.6 V, Ta = -25 to +85C) Parameter Symbol tM1 tM2 tM3 tM4 MCU Interface Digital Input/Output Setting Time tM5 tM6 tM7 tM8 tM9 tM10 tM11 EXCK Clock Frequency fEXCK Condition -- -- -- -- -- -- RD = 1 k, CDL = 20 pF RD = 1 k, CDL = 20 pF -- RD = 1 k, CDL = 20 pF -- -- Min. 20 20 50 100 50 50 -- 0 50 -- 100 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- 30 -- -- 30 -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns MHz 18/53 1 Semiconductor DEN tM9 tM11 tM4 Microcontroller Interface I/O Timing tM1 EXCK tM5 tM6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tM2 tM3 DIN tM7 tM8 W/R A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 tM10 DOUT B7 B6 B5 B4 B3 B2 B1 B0 FEDL7731-02-04 MSM7731-02 19/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 AC Characteristic (Line side CODEC/Acoustic side CODEC) (VDD = 2.7 to 3.6 V, Ta = -40 to +85C) Parameter Symbol LOSST1 LOSST2 LOSST3 LOSST4 LOSST5 LOSST6 LOSSR1 LOSSR2 LOSSR3 LOSSR4 LOSSR5 SD T1 SD T2 SD T3 SD T4 SD T5 SD R1 SD R2 SD R3 SD R4 SD R5 GT T1 GT T2 GT T3 GT T4 GT T5 GT R1 GT R2 GT R3 GT R4 GT R5 NIDLT Idle Channel Noise NIDLR Absolute Signal Amplitude Power Supply Noise Rejection Ratio AVT AVR PSRRT PSRRR 1020 Noise Freq: 0 to 50 kHz 0 Noise Level: 50 mVPP -- -- (*3, *4) A/LGSX (*3) A/LVFRO (*3) (*3) -- 0.285 0.285 30 30 Freq. (Hz) 0 to 60 300 to 3000 1020 3300 3400 3968.75 0 to 3000 1020 3300 3400 3968.75 Condition Level (dBm0) Others Min. 25 -0.15 0 (*3) -0.15 0 13 -0.15 -0.15 0 13 35 35 35 28 23 35 35 35 28 23 -0.2 -0.2 -0.5 -1.2 -0.2 -0.2 -0.5 -1.2 -- Typ. Max. Unit Transmit Frequency Response Receive Frequency Response 0 (*3) Transmit Signal to Distortion Ratio 1020 Receive Signal to Distortion Ratio 1020 Transmit Gain Tracking 1020 Receive Gain Tracking 1020 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -- (*3, *4) (*3, *4) (*3) (*3) -- (*3, *4) -- -- -- +0.20 Reference -- +0.80 -- 0.80 -- -- -- +0.20 Reference -- +0.80 -- 0.80 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- +0.2 Reference -- +0.2 -- +0.5 -- +1.2 -- +0.2 Reference -- +0.2 -- +0.5 -- +1.2 -68 -- (-75.7) -72 -- (-79.7) 0.32 0.359 0.32 -- -- 0.359 -- -- dB dB dB dB dB dB dBm0p (dBmp) Vrms Vrms dB dB Note: *3. CODEC input/output gain = 1 *4. P-message weighted filter used 0.320 Vrms = 0 dBm0 = -7.7 dBm 20/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Noise Canceler Characteristics (VDD = 2.7 to 3.6 V, Ta = -40 to +85C) Parameter Noise Attenuation Symbol Nres Condition White Noise, voice band Min. 13 Typ. 17 Max. -- Unit dB Measurement System Block Diagram White noise generator Analog AIN NC LOUT MSM7731-02 L.P.F. 5 kHz Analog Level meter Power supply voltage 3 V CODEC input gain = 1 CODEC output gain = 1 Echo Canceler Characteristics (VDD = 2.7 to 3.6 V, Ta = -40 to +85C) Parameter Symbol Condition Acoustic Line side (when CODEC or 16-bit linear data interface is used) Line side (-law PCM used) Cancelable Echo Delay Time Tacoud Tacoud Tlined Single mode Dual mode (acoustic side) Dual mode (line side) -- -- -- Min. Typ. 35 30 -- -- -- 59 59-Tlined 27 mS mS mS Max. Unit Echo Attenuation Eres -- -- dB Measurement System Block Diagram White noise generator MSM7731-02 L.P.F. 5 kHz Analog RIN ROUT Analog TD Delay Level meter Analog Line or Acoustic EC SOUT SIN Echo delay time Analog ATT Power supply voltage 3 V CODEC input gain = 1 CODEC output gain = 1 E.R.L (echo return loss) 21/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Rin input level vs. echo attenuation (Measuring Conditions) Rin signal E.R.L Delay time ATT, GC Noise floor : 5 kHz band white noise : -6 dB : 4 ms : OFF : -60 dBm (P-message filter unused) RIN input level vs. echo attenuation 45 40 Echo attenuation [dB] 35 30 25 20 15 10 5 0 -50 -45 -40 -35 -30 -25 Rin input level [dBm] -20 -15 -10 E.R.L level vs. echo attenuation (with GLPAD) (Measuring Condition) Rin signal Rin input level : 5 kHz band white noise : -20 dBm (with GLPAD = 0 dB) : -26 dBm (with GLPAD = 6 dB) : -32 dBm (with GLPAD = 12 dB) : -38 dBm (with GLPAD = 18 dB) : 4 mS : OFF : -60 dBm (P-message filter unused) Delay time ATT, GC Noise floor E.R.L vs. echo attenuation (with GLPAD) 45 40 35 Echo attenuation [dB] 30 25 20 15 10 5 0 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 E.R.L [dB] GLPAD=0dB GLPAD=6dB GLPAD=12dB GLPAD=18dB 22/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Echo delay time vs. echo attenuation (Dual echo canceler mode/acoustic side) (Measuring Condition) Rin signal Rin input level E.R.L ATT, GC Noise floor : 5 kHz band white noise : -16 dBm : -6 dB : OFF : -60 dBm (P-message filter unused) Echo delay time vs. echo attenuation Dual echo canceler mode (acoustic side) 45 Echo attenuation [dB] 40 35 30 25 20 15 10 5 0 5 10 15 20 25 30 35 Echo delay time [ms] 40 45 50 55 60 Echo delay time vs. echo attenuation (Dual echo canceler mode/line side) (Measuring Condition) Rin signal Rin input level E.R.L ATT, GC Noise floor : 5 kHz band white noise : -16 dBm : -6 dB : OFF : -60 dBm (P-message filter unused) Echo delay time vs. echo attenuation Dual echo canceler mode (line side) 45 Echo attenuation [dB] 40 35 30 25 20 15 10 5 0 5 10 15 20 25 30 35 Echo delay time [ms] 40 45 50 55 60 23/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Echo delay time vs. echo attenuation (Single echo canceler mode) (Measuring Condition) Rin signal Rin input level E.R.L ATT, GC Noise floor : 5 kHz band white noise : -16 dBm : -6 dB : OFF : -60 dBm (P-message filter unused) Echo delay time vs. echo attenuation Single echo canceler mode 45 40 Echo attenuation [dB] 35 30 25 20 15 10 5 0 5 10 15 20 25 30 35 Echo delay time [ms] 40 45 50 55 60 Slope filter frequency characteristic (with CODEC filter frequency characteristic) (Measuring Condition) Rin input level Noise floor : -16 dBm : -60 dBm (P-message filter unused) Slope filter frequency characteristic 10 0 Gain [dB] -10 -20 -30 -40 -50 -60 1 501 1001 1501 2001 2501 Frequency [ms] 3001 3501 24/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Echo Canceler Characteristics Data 1 (Line Echo, White Noise) (Measuring Condition) Rin signal Rin input level E.R.L ATT, GC Noise floor : 5 kHz band white noise : -20 dBm : 0 dB : OFF : -60 dBm (P-message filter unused) Echo attenuation = 40 dB Echo Canceler Characteristics Data 2 (Line Echo, Voice) (Measuring Condition) Rin signal Rin input level E.R.L ATT, GC Noise floor : voice : about -20 dBm : 0 dB : OFF : -60 dBm (P-message filter unused) Echo attenuation = 34 dB Echo Canceler Characteristics Data 3 (Acoustic echo, Voice) (Measuring Condition) Rin signal Rin input level Speaker output level Distance from microphone and speaker GC ATT, Noise Canceler Noise floor : voice : about -20 dBm : 80 dB (A) (at 1 m) : 5 cm : OFF : OFF : -60 dBm (P-message filter unused) Echo attenuation = 34 dB Measurement System Block Diagram (Acoustic Echo) 3V M7731 EC SOUT RIN SIN ROUT AIN AGSX AVFRO APWI AOUT RV4 10 k R7 100 C9 10 + R8 2.2 k J1 MIC 5V U13LM4861 1 8 2 7 3 6 4 5 R17 470 k MIC R9 22 k C10 RV1 1 0.734 k R13 22 k R15 R14 1.2 k 22 k R16 10 k J3 SP SP C13 C14 0.1 0.1 AG C15 10 p AG 25/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 FUNCTIONAL DESCRIPTION Control Registers Table 2 Control Register Map Reg Name A6 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 Address A3 0 0 0 0 0 0 0 0 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 B7 *PDN/RST #DMWR -- -- *LTHR *ATHR A15 A7 D15 D7 GPADA2 READY -- B6 *RST -- -- -- -- -- A14 A6 D14 D6 GPADA1 -- -- B5 *#LINEEN -- RPAD6 TPAD6 LHLD AHLD A13 A5 D13 D5 LPADA2 -- -- B4 #CLKEN -- RPAD5 TPAD5 *LHD *AHD A12 A4 D12 D4 LPADA1 -- -- Contents R/W B3 #PCMEN -- *RPAD4 *TPAD4 LCLP ACLP A11 A3 D11 D3 GPADL2 -- -- B2 #PCMEEN *GLPADTHR *RPAD3 *TPAD3 *NCPAD1 *NCPAD2 A10 A2 D10 D2 GPADL1 -- *#NCSEL2 B1 OPE *#MCUSEL *SLPTHR *RPAD2 *TPAD2 *LATT *AATT A9 A1 D9 D1 LPADL2 *#PCMSEL -- B0 OPE *#ECSEL *#NCSEL1 *RPAD1 *TPAD1 *LGC *AGC A8 A0 D8 D0 LPADL1 #SYPDN -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note * : Shared control bits with port (pin) - : Reserved bits. Do not change the initial value ("0"). # : Control bit that can be changed only in the initial mode. 26/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (1) CR0 (basic operating mode setting) B7 CR0 Initial Value (*5) PDN/RST 0 B6 RST 0 B5 LINEEN 0 B4 CLKEN 0 B3 PCMEN 0 B2 PMCEEN 0 B1 OPE MCUSEL 0 B0 OPE ECSEL 0 Note*5: Initial values are the values set when reset is activated by the PDN/RST pin. (Initial values are also set in the same manner, except for CR0-B7, when reset by the PDN/RST bit of B7.) B7 Power-down and Reset 0: power-on 1: power-down reset During power-down reset, this device enters the power-down state. At this time all control register bits, internal variables, and the coefficients for the echo canceler and noise canceler are reset. After powerdown reset is released, this device enters the initial mode. This bit is internally ORed with the inverted PDN/RST signal. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". Reset control 0: normal operation 1: reset At reset, the coefficients for the echo canceler and noise canceler and noise canceler are reset. Control register contents preserved. While reset is being processed, there is no sound. Use this bit in cases where the echo path changes (due to line switching during a telephone conversation, etc.), or when resuming telephone communication. Because data is read by this bit in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the inverted RST signal. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". B6 B5 Line CODEC power-down control 0: normal operation 1: power-down During power-down, the line CODEC is in the power-down state, the line CODEC output pin is at high impedance and line CODEC input pin is internally processed as an idle pattern input. This bit is internally ORed with the LINEEN pin. When the line CODEC is not used, this control results in low consumption of electrical power. This bit can only be set to "0" or "1" during power-down reset and initial mode. Refer to the section "RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS". SYNC, BCLK output control 0: ON 1: OFF When OFF, the SYNC and BCLK output pins are in the high impedance state. This control is valid when the CLKSEL pin is at a logic "0" and has selected the internal clock mode. When the SYNC and BCLK clocks are not used externally, this control results in low consumption of electrical power. This bit can only be set to "0" or "1" during power-down reset and the initial mode. PCMI/O control 0:ON 1: OFF When OFF, the PCMO output pin is in the high impedance state and the PCMI input pin is internally processed as an idle pattern input. When the line digital interface is not used, this control results in low consumption of electrical power. This bit can only be set to "0" or "1" during power-down reset and the initial mode. PCMEI/O control 0:ON 1: OFF When OFF, the PCMEO output pin is in the high impedance state and the PCMEI input pin is internally processed as an idle pattern input. When the line digital interface is not used, this control results in low consumption of electrical power. This bit can only be set to "0" or "1" during power-down reset and the initial mode. B4 B3 B2 27/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 B1, B0 Operation mode selection (0, 0): Initial mode Approximately 200 ms after power-down reset is released, the initial mode is entered. Only in this mode can the contents of the internal default value store memory be modified and CR0-B5 to CR0-B0, CR1-B7, CR1-B0, CR11-B1, CR11-B0, and CR12-B2 be set. In this mode, digital signal output pins are at high impedance, digital communication input pins are internally processed as idle pattern inputs, and neither the echo canceler nor the noise canceler operates. This mode is skipped when the MCUSEL pin is a logic "1". This mode is released by setting the modes shown below. Refer to the flow chart of Figure 5. (1, 0): Dual echo canceler mode The acoustic echo canceler, line echo canceler and other functions can be operated by control from the control registers. Refer to Figure 6. The initial setting for cancelable echo delay time is as follows: Acoustic delay time = 44 ms Line delay time = 15 ms (1, 1): Single echo canceler mode The acoustic echo canceler and other functions can be operated by control from the control registers. Control of the line echo canceler is unnecessary in this mode .Refer to Figure 7. The initial setting for cancelable echo delay time is as follows: Acoustic delay time = 59 ms (Other): Reserved bit (cannot be used) Note: The MCUSEL pin is internally ORed with B1, and the ECSEL pin is internally ORed with B0. To return to the initial mode after it has been released, activate power-down reset. PDN/RST Power-down state PDN/RST release Wait for 200 ms Control registers are reset. Internal variables are reset. Initial Mode READY(CR11-B7) = 1 Automatic setting Acoustic CODEC Acoustic Echo Canceler Noise Canceler Slope Filter Line Echo Canceler Line CODEC Figure 6 Dual Echo Canceler Mode Set control register Acoustic Acoustic Echo Canceler Noise Canceler Slope Filter Modify default store memory CODEC Line CODEC CR0-B1=1 YES NO Figure 7 Single Echo Canceler Mode READY(CR11-B7) = 0 Automatic setting Start Normal Operation Figure 5 Initial Mode Flowchart 28/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (2) CR1 B7 CR1 Initial Value DMWR 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 -- 0 B2 GLPADTHR B1 SLPTHR 0 B0 NCSEL1 0 0 B7 Internal data memory write control 0: write inhibited 1: write In internal data memory, the data set in CR8 (D15 to D8) and CR9 (D7 to D0) is written to the memory address set in CR6 (A15 to A8) and CR7 (A7 to A0). Writing is possible only during the initial mode. For further details, refer to the internal data memory access method. Reserved bits. Modification of initial values is inhibited. B6, B5, B4, B3 B2 Echo Canceler I/O PAD control 0: "through mode" 1: normal mode This bit controls the attenuators (LPADL/A) provided in the SinL/A inputs and the amplifiers (GPADL/A) provided in the SoutL/A outputs of the echo canceler. Levels are set by the CR10 register, and 18, 12, 6 and 0 dB can be set. The default value is 12 dB. Use this bit when the echo return loss (value of returned echo) is amplified. If the pin setting is changed, the coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because data is read by this bit in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the GLPADTHR pin. Slope filter control 0: normal mode (slope filter operation) 1: "through mode" This bit controls operation of the transmit slope filter. In the "through mode", the filter is halted and data is output directly. The slope filter decreases noises of low frequencies and improves the speech quality. Refer to the frequency characteristics of slope filter. Because data is read by this bit in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the SLPTHR pin. Noise attenuation selection control 0: normal mode 1: "through mode" This bit selects the noise attenuation of the noise canceler. In the "through mode", the noise canceler is halted and data is output directly. In the "normal mode" the noise canceler operates normally. Since the noise attenuation in the normal mode is selected after the initial mode has been released, the change of the noise attenuation during normal operation is invalid. If the noise attenuation is changed, reset must be activated by the RDN/RST pin or the PDN/RST bit (CR0-B7). Changing to the through mode during normal operation and returning to the normal mode are possible. This bit is internally ORed with NCSEL1 pin. (Refer to the NCSEL2 pin of CR12-B2.) Since there is a trade-off between noise attenuation and sound quality after canceling the noise, select the noise attenuation appropriate to the sound quality. NCSEL2 0 1 1 0 NCSEL1 0 1 0 1 NC Mode Normal Mode Normal Mode Normal Mode Through Mode Attenuation (dB) 17 13.5 8 -- Quality Better Best -- B1 B0 Note: 29/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (3) CR2 (Receive side level control) B7 CR2 Initial Value -- 0 B6 -- 0 B5 RPAD6 0 B4 RPAD5 0 B3 RPAD4 0 B2 RPAD3 0 B1 RPAD2 0 B0 RPAD1 0 B7, B6 Reserved bit. Modification of initial values is inhibited. B5, B4, B3, B2, B1,B0 Receive side level setting (RPAD) These bits adjust the receive signal gain and set the mute level. Notice that only the mute level setting differs from pin control. Because data is read by these bits in synchronization with the rising edge of the SYNC signal, hold the data in these bits for 250 s or longer. When using this register, set the TPAD, 3, 2, 1 pins to a logic "0". (0, 0, 1, 0, 1, 0): (0, 0, 1, 0, 0, 1): (0, 0, 1, 0, 0, 0): (0, 0, 0, 1, 1, 1): (0, 0, 0, 1, 1, 0): (0, 0, 0, 1, 0, 1): (0, 0, 0, 1, 0, 0): (0, 0, 0, 0, 1, 1): (0, 0, 0, 0, 1, 0): (0, 0, 0, 0, 0, 1): (0, 0, 0, 0, 0, 0): (1, 1, 1, 1, 1, 1): (1, 1, 1, 1, 1, 0): (1, 1, 1, 1, 0, 1): (1, 1, 1, 1, 0, 0): (1, 1, 1, 0, 1, 1): (1, 1, 1, 0, 1, 0): (1, 1, 1, 0, 0, 1): (1, 1, 1, 0, 0, 0): (1, 1, 0, 1, 1, 1): (1, 1, 0, 1, 1, 0): (1, 1, 0, 1, 0, 1): (1, 1, 0, 1, 0, 0): (1, 1, 0, 0, 1, 1): (1, 1, 0, 0, 1, 0): (1, 1, 0, 0, 0, 1): (1, 1, 0, 0, 0, 0): (1, 0, 1, 1, 1, 1): (1, 0, 1, 1, 1, 0): (1, 0, 1, 1, 0, 1): (1, 0, 1, 1, 0, 0): (1, 0, 1, 0, 1, 1): 30 dB 27 dB 24 dB 21 dB 18 dB 15 dB 12 dB 9 dB 6 dB 3 dB 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB -24 dB -27 dB -30 dB -33 dB -36 dB -39 dB -42 dB -45 dB -48 dB -51 dB -54 dB -57 dB -60 dB MUTE 30/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (4) CR3 (Transmit Gain Adjustment) B7 CR3 Initial Value -- 0 B6 -- 0 B5 TPAD6 0 B4 TPAD5 0 B3 TPAD4 0 B2 TPAD3 0 B1 TPAD2 0 B0 TPAD1 0 B7, B6 Reserved bits. Modification of initial values is inhibited. B5, B4, B3, B2, B1, B0 Transmit side level setting (TPAD) These bits adjust the transmit signal gain and set the mute level. Notice that only the mute level setting differs from pin control. Because data is read by these bits in synchronization with the rising edge of the SYNC signal, hold the data in these bits for 250 s or longer. When using this register, set the TPAD4, 3, 2, 1 pins to a logic "0". (0, 0, 1, 0, 1, 0): (0, 0, 1, 0, 0, 1): (0, 0, 1, 0, 0, 0): (0, 0, 0, 1, 1, 1): (0, 0, 0, 1, 1, 0): (0, 0, 0, 1, 0, 1): (0, 0, 0, 1, 0, 0): (0, 0, 0, 0, 1, 1): (0, 0, 0, 0, 1, 0): (0, 0, 0, 0, 0, 1): (0, 0, 0, 0, 0, 0): (1, 1, 1, 1, 1, 1): (1, 1, 1, 1, 1, 0): (1, 1, 1, 1, 0, 1): (1, 1, 1, 1, 0, 0): (1, 1, 1, 0, 1, 1): (1, 1, 1, 0, 1, 0): (1, 1, 1, 0, 0, 1): (1, 1, 1, 0, 0, 0): (1, 1, 0, 1, 1, 1): (1, 1, 0, 1, 1, 0): (1, 1, 0, 1, 0, 1): (1, 1, 0, 1, 0, 0): (1, 1, 0, 0, 1, 1): (1, 1, 0, 0, 1, 0): (1, 1, 0, 0, 0, 1): (1, 1, 0, 0, 0, 0): (1, 0, 1, 1, 1, 1): (1, 0, 1, 1, 1, 0): (1, 0, 1, 1, 0, 1): (1, 0, 1, 1, 0, 0): (1, 0, 1, 0, 1, 1): 30 dB 27 dB 24 dB 21 dB 18 dB 15 dB 12 dB 9 dB 6 dB 3 dB 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB -24 dB -27 dB -30 dB -33 dB -36 dB -39 dB -42 dB -45 dB -48 dB -51 dB -54 dB -57 dB -60 dB MUTE 31/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (5) CR4 (Line echo canceler setting) B7 CR4 Initial Value LTHR 0 B6 -- 0 B5 LHLD 0 B4 LHD 0 B3 LCLP 0 B2 NCPAD1 0 B1 LATT 0 B0 LGC 0 B7 "Through mode" control 1: "through mode" 0: normal mode (echo canceler operation) This is the "through mode" control bit for the line echo canceler. In the "through mode", RinL and SinL data is output directly to RoutL and SoutL respectively while each echo coefficient is maintained . In the through mode, the functions of LHD, LHLD, LATT and LGC are invalid. Because data is read by this bit in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the LTHR pin. Reserved bit. Modification of initial values is inhibited. B6 B5 Coefficient update control 1: fixed coefficients 0: updated coefficients This bit selects whether the adaptive FIR filter (AFR) coefficients for the line echo canceler will be updated. This unction is valid when the ATHR pin is in the normal mode. Because data is read into this bit by synchronization with the rising edge of the SYNC signal, hold the data at the bit for 250 s or longer. Howling detector control 1: OFF 0: ON This bit controls the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. This function is valid when the LTHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the LHD pin. Center clip control 1: ON 0: OFF When the SoutL output of the line echo canceler is -57 dBm0 or less, the center clip function forcibly sets it to the minimum positive value. This function is valid when the LTHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. NCPAD control This bit adjusts the noise canceler I/O gain. The gain adjustment is valid for tone control after canceling the noise. The bigger the input level of the noise canceler is, the better the sound quality is. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the NCPAD1 pin. (Refer to the NCPAD2 pin of CR5-B2.) NCPAD2 0 0 1 1 NCPAD1 0 1 0 1 GPADNC (dB) 0 6 12 18 LPADNC (dB) 0 -6 -12 -18 B4 B3 B2 32/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 B1 Attenuator control 1: ATT OFF 0: ATT ON This bit turns ON or OFF the ATT function to prevent howling by means of attenuators (ATTsL, ATTrL) provided in the RinL input and SoutL output of the line echo canceler. If input is only to RinL, the ATT for SoutL (ATTsL) is activated. If input is only to SinL, or if there is input to both SinL and RinL, the ATT for RinL input (ATTrL) is activated. The ATT value of each attenuator is approximately 6 dB. This function is valid when the LTHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the LATT pin. Gain controller 1: GC OFF 0: GC ON This bit turns ON or OFF the gain control function to control the RinL input level and prevent howling by means of a gain controller (GainL) provided in the RinL input of the line echo canceler. The gain controller adjusts the RIN input level when it is -10 dBm0 or above, and it has the control range of 0 to -8.5 dB. This function is valid when the LTHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the LGC pin. B0 33/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (6) CR5 (Acoustic echo canceler setting) B7 CR5 Initial Value ATHR 0 B6 -- 0 B5 AHLD 0 B4 AHD 0 B3 ACLP 0 B2 NCPAD2 0 B1 AATT 0 B0 AGC 0 B7 "Through mode"control 1: "through mode" 0: normal mode (echo canceler operation) This is the "Through mode" control bit for the acoustic echo canceler. In the "through mode", RinA and SinA data is output directly to RoutA and SoutA respectively while each echo coefficient is maintained. In the through mode, the functions of AHD, AHLD, AATT and AGC are invalid. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the ATHR pin. Reserved bit. Modification of initial values is inhibited. B6 B5 Coefficient update control 1: fixed coefficients 0: updated coefficients This bit selects whether the adaptive FIR filter (AFR) coefficients for the acoustic echo canceler will be updated. This function is valid when the ATHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. Howling detector control 1: OFF 0: ON This bit controls the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. This function is valid when the ATHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the AHD pin. Center clip control 1: ON 0: OFF When the SoutA output of the acoustic echo canceler is -57 dBm0 or less, the center clip function forcibly sets it to the minimum positive value. This function is valid when the ATHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. NCPAD control This bit adjusts the noise canceler I/O gain. The gain adjustment is valid for tone control after canceling the noise. The bigger the input level of the noise canceler is, the better the sound quality is. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the NCPAD2 pin. (Refer to the NCPAD1 pin of CR4-B2.) NCPAD2 0 0 1 1 NCPAD1 0 1 0 1 GPADNC (dB) 0 6 12 18 LPADNC (dB) 0 -6 -12 -18 B4 B3 B2 34/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 B1 Attenuator control 1: ATT 12 dB 0: ATT 6 dB This bit selects the attenuation of the ATT function to prevent howling by means of attenuators (ATTsA, ATTrA) provided in the RinA input and SoutA output of the acoustic echo canceler. If input is only to RinA, the ATT for SoutA (ATTsA) is activated. If input is only to SinA, or if there is input to both SinA and RinA, the ATT for RinA input (ATTrA) is activated. The ATT value of each attenuator is approximately 6 dB or 12 dB. This function is valid when the ATHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the AATT pin. Gain controller control 1: GC OFF 0: GC ON This bit turns ON or OFF the gain control function to control the RinA input level and prevent howling by means of a gain controller (GainA) provided in the RinA input of the acoustic echo canceler. The gain controller adjusts the RIN input level when it is -10 dBm0 or above, and it has the control range of 0 to -8.5 dB. This function is valid when the ATHR pin is in the normal mode. Because this bit is read in synchronization with the rising edge of the SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the AGC pin. B0 35/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (7) CR6 (Internal data memory write register) B7 CR6 Initial Value A15 0 B6 A14 0 B5 A13 0 B4 A12 0 B3 A11 0 B2 A10 0 B1 A9 0 B0 A8 0 B7 to B0 Memory upper address control This register sets the upper address of memory. For the writing method, refer to the Method of Internal Data Memory Access section. (8) CR7 (Internal data memory write register) B7 CR7 Initial Value A7 0 B6 A6 0 B5 A5 0 B4 A4 0 B3 A3 0 B2 A2 0 B1 A1 0 B0 A0 0 B7 to B0 Memory lower address control This register sets the lower address of memory. For the writing method, refer to the Method of Internal Data Memory Access section. (9) CR8 (Internal data memory write register) B7 CR8 Initial Value D15 0 B6 D14 0 B5 D13 0 B4 D12 0 B3 D11 0 B2 D10 0 B1 D9 0 B0 D8 0 B7 to B0 Memory upper data control This register sets the memory's upper data. For the writing method, refer to the Method of Internal Data Memory Access section. (10) CR9 (Internal data memory write register) B7 CR9 Initial Value D7 0 B6 D6 0 B5 D5 0 B4 D4 0 B3 D3 0 B2 D2 0 B1 D1 0 B0 D0 0 B7 to B0 Memory lower data control This register sets the memory's lower data. For the writing method, refer to the Method of Internal Data Memory Access section. 36/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (11) CR10 (Echo canceler I/O level setting) B7 CR10 Initial Value GPADA2 0 B6 GPADA1 0 B5 LPADA2 0 B4 LPADA1 0 B3 GPADL2 0 B2 GPADL1 0 B1 LPADL2 0 B0 LPADL1 0 B7, 6 Acoustic output level control These bits control the PAD level of the gain of the acoustic echo canceler's SoutA output. PAD is turned ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). It is recommended to set the level to the positive level equal to LPADA2 and LPADA1. If the pin setting is changed, the coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because these bits are read in synchronization with the rising edge of the SYNC signal, hold the data in these bits for 250 s or longer. (0, 1): + 18 dB (0, 0): + 12 dB (1, 1): + 6 dB (1, 0): 0 dB Acoustic input level control These bits control the PAD level of the loss of the acoustic echo canceler's SinA input. PAD is turned ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). Set the level so that echo return loss (value of returned echo) will be attenuated. If the pin setting is changed, the coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because these bits are read in synchronization with the rising edge of the SYNC signal, hold the data in these bits for 250 s or longer. (0, 1): - 18 dB (0, 0): - 12 dB (1, 1): - 6 dB (1, 0): 0 dB Line output level control These bits control the PAD level of the loss of the line echo canceler's SoutL output. PAD is turned ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). It is recommended to set the level to the positive level equal to LPADL2 and LPADL1. If the pin setting is changed, the coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because these bits are read in synchronization with the rising edge of the SYNC signal, hold the data in these bits for 250 s or longer. (0, 1): + 18 dB (0, 0): + 12 dB (1, 1): + 6 dB (1, 0): 0 dB Line input level control These bits control the PAD level of the loss of the line echo canceler's SinL output. PAD is turned ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). Set the level so that echo return loss (value of returned echo) will be attenuated. If the pin setting is changed, the coefficient reset must be activated by either the RST pin or the RST bit (CR0-B6). Because these bits are read in synchronization with the rising edge of the SYNC signal, hold the data in these bits for 250 s or longer (0, 1): - 18 dB (0, 0): - 12 dB (1, 1): - 6 dB (1, 0): 0 dB B5, 4 B3, 2 B1, 0 37/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (12) CR11 (SYNC power-down control register) B7 CR11 Initial Value READY 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 -- 0 B2 -- 0 B1 PCMSEL 0 B0 SYPDN 0 B7 Data write flag 1: write enabled 0: write disabled After power-down reset is released, this device enters the initial mode. This bit becomes "1" only during the initial mode, enabling access to the internal data memory. Checking this bit will detect whether writing by an external microcomputer is possible. Modification of initial values is inhibited. B6 to B2 Reserved bits. B1 PCM coding format control 1: -law PCM 0: 16-bit linear This is the coding format selection bit for digital data communication. A logic "1" selects -law PCM and a logic "0" selects 16-bit linear (2's complement) coding format. The BCLK signal determines the output clock frequency to be used when internal clock is selected. If the digital interface is not used, set this bit to logic "0" to select 16-bit linear coding format. Since this bit is ORed with the PCMSEL pin, set this bit to logic "0" when controlling by the pin. If this bit setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7). SYNC-PDWN control 1: PDN/RST power-down 0: PDWN power-down This bit controls the function that automatically enters the power-down state when the SYNC signal is fixed to a logic "1" or "0". This function is valid when the external clock mode has been selected by the CLKSEL pin. Two kinds of power-down modes can be selected. * PDN/RST power-down mode If the SYNC signal is fixed at 8 kHz or longer, this device automatically writes a logic 1 to the control register PDN/RST bit (CR0-B7) and enters the power-down reset state. To return to the normal operation, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-7). The state after returning to the normal operation is the same as that reset after power-on. * PDWN power-down mode If the SYNC signal is fixed at 8 kHz or longer, this device automatically enters the power-down state. During the power-down, the analog output is "0" output (mute) and the SG output holds about 1.4 V. To return to the normal operation, detect the SYNC signal rise. In the state after returning to the normal operation, internal variables and coefficients of the echo canceler and noise canceler are reset. Each bit of the control register is held and operates normally after about 200 ms. PDN/RST power-down PDWN power-down 0 Mute control SYNC rising edge -Reset Internal coefficient. Echo canceler coefficient. Noise canceler coefficient. -Hold Each bit of CR. TBD B0 SYPDN (CR11-B0) Internal process Power-down removal method 1 PDN/RST (CR0-B7) = 1 PDN/RST pin or bit -Reset Each bit of CR. Internal coefficient. Echo canceler coefficient. Noise canceler coefficient. Typ. 0.02 mA After removing power-down Operating Current 38/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 (13) CR12 (Reserved register) B7 CR12 Initial Value -- 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 -- 0 B2 NCSEL2 0 B1 -- 0 B0 -- 0 B7 to B3 Reserved bits. B2 Modification of initial values is inhibited. Noise attenuation selection control This bit selects the noise attenuation of the noise canceler. In the "through mode", the noise canceler is halted and data is output directly. In the "normal mode" the noise canceler operates normally. Since the noise attenuation in the normal mode is selected after the initial mode has been released, the change of the noise attenuation during normal operation is invalid. If the noise attenuation is changed, reset must be activated by the RDN/RST pin or the PDN/RST bit (CR0-B7). Changing to the through mode during normal operation and returning to the normal mode are possible. This bit is internally ORed with the NCSEL2. (Refer to the NCSEL1 pin of CR1-B0.) Note: Since there is a trade-off between noise attenuation and sound quality after canceling the noise, select the noise attenuation appropriate to the sound quality. NCSEL2 0 1 1 0 NCSEL1 0 1 0 1 NC Mode Normal Mode Normal Mode Normal Mode Through Mode Attenuation (dB) 17 13.5 8 -- Quality Better Best -- B1, B0 Reserved bits. Modification of initial value is inhibited. 39/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS In this device, the same function is controlled by either a pin or a control register. For example, when a function is controlled by a pin, setting of the corresponding control register is important. Table 3 shows the relationship between settings of pins when functions are controlled by control registers and setting of control registers when functions are controlled by pins. The setting value of a control register when a function is controlled by a pin is equal to its initial value when the device is reset by the PDN/RST pin or the PDN/RST bit (CR0-B7). Table 3 Relationship between pins and control registers Function LINEEN PDN/RST PCMSEL ECSEL LTHR/ATHR LHD/AHD LATT/AATT LGC/AGC GLPADTHR SLPTHR RST MCUSEL RPAD4-1 TPAD4-1 NCSEL1, 2 NCPAD1, 2 Setting of pin when function is controlled by control register Logic "0" Logic "1" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "1" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Setting of control register when function is controlled by pin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 CONTROL METHOD BY MCU START Power supply ON Set PDN/RST Cancel PDN/RST CR11-B7 = 1 Yes Write internal memory? No No Yes Set CR6 Set CR7 Initial mode Set CR8 Internal memory write Set CR9 CR1 = 80h CR1 = 00h Yes Set other memory? No Yes No Set CR1 to CR12 Set CR0 CR11-B7 = 0 Yes No Start telecommunication 41/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 METHOD OF INTERNAL DATA MEMORY ACCESS The default values such as the cancelable echo delay time, echo attenuation and noise attenuation can be changed during the initial mode (CR0-B1, CR0-B0 = "00"). Refer to the procedure below. 1. Set the address of the default value store memory. (CR6, 7) 2. Set the modified values (data). (CR8, 9) 3. Set the write command. (CR1-B7 = "1") After the write operation is complete, the write command (CR1-B7) is cleared to "0". Consecutive writes are possible. (Example) In the case of changing the acoustic delay time in a single echo canceler mode to 30 ms. Address: 009Bh, Data: 00F0h START Upper address setting CR6 = 00h CR7 = 9Bh Lower address setting CR8 = 00h Upper data setting CR9 = F0h Lower data setting CR1 = 80h CR1 = 00h Yes Set other memory? Write control No Write complete confirmation Yes No END 42/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Echo Canceler Delay Time Cancelable echo delay time is as follows. (1) Single echo canceler mode Acoustic echo canceler Default : 59 ms Variable range : 0.5 to 59 ms (in 0.5 ms steps) Line echo canceler operation is halted. (2) Dual echo canceler mode (operation of acoustic and line echo cancelers) Condition : acoustic delay time + line delay time 59 ms Acoustic echo canceler Default : 44 ms Variable range : 0.5 to 58.5 ms (in 0.5 ms steps) Line echo canceler Default : 15 ms Variable range : 0.5 to 27 ms (in 0.5 ms steps) Memory addresses are shown below. (1) Single echo canceler mode Memory address of acoustic echo canceler delay time : 009Bh (2) Dual echo canceler mode (operation of acoustic and line echo cancelers) Memory address of acoustic echo canceler delay time : 0099h Memory address of line echo canceler delay time : 009Ah The method for calculating delay time is shown below. delay time [s] x 8000 = delay time data (HEX) Example of 30 ms: 0.03 x 8000 = 240 (DEC) = 00F0 (HEX) Echo canceler mode Dual echo canceler Single echo canceler Echo canceler Acoustic side Line side Acoustic side Line side Address 0099h 009Ah 009Bh -- Default time 44 ms 15 ms 59 ms -- Default data 0160h 0078h 01D8h -- Changeable range 0.5 to 58.5 ms 0.5 to 27.0 ms 0.5 to 59.0 ms -- Notes : Dual echo canceler mode condition Acoustic echo canceler delay time + line echo canceler delay time 59 ms : Setting delay time condition 0.5 ms steps (increment width) 43/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 Noise Attenuation There is a trade-off between noise attenuation and sound quality. In other words, increasing the noise attenuation deteriorates sound quality, and decreasing the noise attenuation improves sound quality. The following combinations of noise attenuation levels can be selected with this device. Select the noise attenuation appropriate to the sound quality. When selecting the following combinations by the method of internal data memory access, set the NCSEL1/NCSEL2 pin and bit as follows: NCSEL1 pin and bit (CR1-B0) = 0 NCSEL2 pin and bit (CR12-B2) = 0 Noise attenuation [dB] address 17 (default) 14 13.5 12 11 10 9 8 8 8 7 7 6 Data 1 01C8h 2000h 3333h 3333h 4666h 4666h 5999h 6666h 5999h 2000h 3333h 4666h 5999h 6666h Data 2 01C2h 0005h 0005h 0004h 0005h 0003h 0005h 0005h 0002h 0001h 0001h 0001h 0001h 0001h Best Voice quality Better Attenuation of ATT Function The attenuation (ATT values) of echo canceler ATT functions (ATTsL/ATTrL, ATTsA/ATTrA) can be selected from the following combinations. When selecting the attenuation, take note of the following. 1. Increasing the attenuation causes almost half duplex. 2. Increasing the attenuation causes the sound of the beginning and ending of words to be cut. 3. Increasing the attenuation remarkably changes the sound volume of background noise. (by turning On or OFF the ATTs/ATTr) When selecting the following combinations by the method of internal data memory access, set the AATT pin and bit as follows: AATT pin and bit (CR5-B1) = 0 ATT attenuation [dB] address 6 (default) 12 18 24 Data 1 0199h 4000h 2000h 1000h 0800h Data 2 019Ch 4200h 4000h 4000h 4000h Data 3 019Fh 4200h 2200h 2000h 2000h Data 4 01A2h 4200h 2200h 1200h 1000h Data 5 01A5h 4000h 2000h 1000h 0800h 44/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 GAIN ADJUSTMENT OF EXTERNAL SPEAKER AMPLIFIER The overflow (clipping) of speaker amplifier output occurred in the echo path between the echo canceler output (e.g. AVFRO) and the echo canceler input (e.g. AGSX) decreases the echo attenuation remarkably. In other words, when an external speaker amplifier is used, do gain adjusting without overflow of speaker amplifier output. Adjusting Method 1 Be careful of the following. 1. Echo canceler output pin (AVFRO/LVFRO) Adjust the AGSX/LGSX gain or RPAD/TPAD so as to set the output level to less than 1.3 Vpp (typical level = -20 dBm0). 2. External speaker amplifier output pin Adjust the gain so as to set the output level to less than the maximum output amplitude. Adjusting Method 2 The speaker amplifier output can be adjusted appropriately by making the echo canceler input signal clipped intentionally when the speaker amplifier output is small. 1. External speaker amplifier gain The analog maximum output amplitude of the MSM7731 and the maximum output amplitude of external speaker amplifier determine the speaker amplifier gain. (Example) AVFRO maximum output amplitude = 1.3 Vpp Gain of APWI and AOUT = 1 Maximum output amplitude of external speaker amplifier = 10 Vpp External speaker amplifier gain = speaker amplifier maximum output amplitude/AVFRO maximum output amplitude = 10/1.3 = less than 7.6 2. Speaker output adjustment Adjust the volume with the echo canceler input (RPAD). The following shows the circuit diagram. MSM7731 AVFRO Echo Canceler RPAD CODEC APWI AOUT 20 k 20 k C 10 k - + Speaker Amplifier Speaker 68 k 45/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 DIFFERENCE BETWEEN MSM7731-01 AND MSM7731-02 Function Control method MSM7731-01 variable by initial download 17 dB or through selectable by NCTHR bit 17 dB or through selectable by NCTHR pin None None variable by initial download 0 dB or 6 dB selectable by AATT bit 0 dB or 6 dB selectable by AATT pin ON or OFF selectable by AHLD, LHLD bit ON or OFF selectable by AHLD, LHLD pin Power down function (PDN/RST) ON or OFF selectable by SYPDN bit *1 None MSM7731-02 variable by initial download 17 dB, 13.5 dB, 8 dB or through selectable by NCSEL1, 2 bits 17 dB, 13.5 dB, 8 dB or through selectable by NCSEL1, 2 pins 0 dB, 6 dB, 12 dB or 18 dB selectable by NCPAD1, 2 bits 0 dB, 6 dB, 12 dB or 18 dB selectable by NCPAD1, 2 pins variable by initial download 6 dB or 12 dB selectable by AATT bit 6 dB or 12 dB selectable by AATT pin ON or OFF selectable by AHLD, LHLD bits always updated (ON) Power down function (PDN/RST) ON or OFF selectable by SYPDN bit *1 always operated (ON) *1 Power down function (PDWN) MCU Control Noise Attenuation Selection Pin Control MCU Control Pin Control MCU Control Pin Control Line Acoustic Echo Canceler Coefficient Update Function MCU Control Pin Control Noise Canceler I/O Gain Adjustment Function Acoustic Echo Canceler Attenuator Function MCU Control SYNC Power-down Pin Control Note*1: Refer to the description of "(12) CR11 (SYNC-PDWN Control Register)" of this data sheet. 1. Pins (MSM7731-01) NCTHR TEST8 LHLD AHLD 2. Control registers CR1-B0 CR12-B2 CR4-B2 CR5-B2 CR4-B5 CR5-B5 (MSM7731-01) NCTHR X LHLD AHLD X X (MSM7731-02) NCSEL1 NCSEL2 NCPAD1 NCPAD2 LHLD AHLD (MSM7731-02) NCSEL1 NCSEL2 NCPAD1 NCPAD2 46/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 3. Functions Noise attenuation selection Noise canceler I/O gain adjustment Acoustic echo canceler coefficient update Line echo canceler coefficient update Accoustic echo canceler attenuator SYNC power-down (MSM7731-02) Function added (17, 13.5, 8 dB, THR-selectable) Function added (0, 6, 12, 18 dB-selectable) Pin control disabled Pin control disabled Attenuation changed, OFF function deleted (6, 12 dB selectable) Control changed (PDN/RST power-down, PDWN power-down) 47/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 NOTES ON USE 1. Use a stabilized power supply with a low level of noises (especially spike noises and pulse noises of high frequencies) in order to prevent this device from malfunction or degradation in characteristics. Place a good characteristic of bypass-capacitor for the power supply near the pins of this device in order to assure its electrical characteristics. Place a good characteristic of bypass-capacitor for the analog signal ground (SG pin) near the pins of this device in order to assure its electrical characteristics. Connect the AGND, DGND1 and DGND 2 to the system ground at a shortest distance and in a low impedance state. Use a separate power supply for an external speaker amplifier so as not to be disturbed by externally generated noises. When an external speaker amplifier is used, do gain adjusting without overflow (saturation) of speaker amplifier output. The overflow of speaker amplifier output decreases the echo attenuation. Set the analog signal input level to less than 1.3 VPP to prevent overlow. Otherwise, voice will be distorted. Set the echo return loss (ERL) to be attenuated. If the echo return loss is to be amplified, the GLPAD function should be used. The ERL refers to echo attenuation (loss) between the echo canceler output (RoutA/RoutL) and the echo canceler input (SinA/SinL). Refer to Characteristics Diagram for the ERL vs. echo attenuation. The input level should be -10 to -20 dBm0. Refer to Characteristics Diagram for the ERL vs. echo attenuation. 2. 3. 4. 5. 6. 7. 8. 9. 10. Adjust the volume at the position of the echo canceler input (RinA/RinL). When in Dual Echo Canceler mode : Adjust the volume with TPAD and RPAD. When in Signal Echo Canceler mode : Adjust the volume with TPAD and RPAD, or with the analog input (LIN) that is set at less than 1.3 VPP. 11. When the echo path is changed (when resuming telephone communication), reset the device with the RST pin or the RST bit. 12. After turning on the power, be sure to reset the device with the PDN/RST pin or the PDN/RST bit. 13. In order to get the highest performance of this device, the following functions should be used. AATT/LATT AGC/LGC SLPTHR NCTHR RPAD6-1 TPAD6-1 : ON : ON : Normal mode (slope filter operation) : Normal mode (noise canceler operation) : Adjusting the volume of receive signal : Adjusting the volume of transmit signal 48/53 1 Semiconductor APPLICATION CIRCUIT MSM7731-02 NOISE SLOPE CANCELER FILTER LINER CODEC A-outL Rin Rout MIC LINE ECHO CANCELER LINEAR CODEC Sout ACOUSTIC ECHO CANCELER A-inA AFF Rin Sout Sin Sin SP (8 W) TPAD AFF A-outA RPAD P/S & Timing Gen MCU I/F EC/NC/PAD Controller Rout A-inL SPamp Clock Gen S/P PCMO PCMI PCMEO PCMEI MSM6679B Voice Recognition Processor LTHR * * * AHD DEN EXCK DIN DOUT MCUSEL PDN/RST MCK/XI X2 SYNC SYNCSEL BCLK CLKSEL PMCSEL Vocabulary Memory FEDL7731-02-04 MSM7731-02 49/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 APPLICATION CIRCUIT (1) In case of line analog interface and pin control (NCSEL = 13.5 dB, NCPAD = 6 dB, TRAD = 9 dB) MSM7731-02 20 k 20 k LVFRO LPWI LOUT AVFRO APWI AOUT AGSX AIN NCSEL1 NCSEL2 NCPAD1 NCPAD2 ATHR AHD AATT AGC LTHR LHD LATT LGC LINEEN PCMSEL SLPTHR MCUSEL ECSEL GLPADTHR TPAD1 TPAD2 TPAD3 TPAD4 RPAD1 RPAD2 RPAD3 20 k 20 k 20 k Speaker amplifier 1 F 1 k 3 V(D) Portable Line telephone Interface 20 k 3 V(D) 1 F 20 k SP LGSX LIN SYNC BCLK PCMI PCMO PCMEI PCMEO DEN EXCK DIN DOUT PDN/RST RST CLKSEL SYNCSEL TEST1 TEST2 TEST3 MIC RESET 3 V(D) 3 V(D) TEST4 TEST9 DVDD1 + 3 V(D) 0.1 F 10 F DVDD2 DGND1 10 k 3 V(A) 10 F 0.1 F 0.1F DGND210 F + AVDD AGND Rotary switch + 10 F SG MCK/X1 X2RPAD4 1 M 19.2 MHz 10 pF 10 pF 50/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 APPLICATION CIRCUIT (2) In case of line digital interface and MCU control MSM7731-02 AVFRO LVFRO LPWI LOUT LGSX 3 V(D) 20 k 20 k Speaker amplifier 1 F 1 k APWI AOUT AGSX AIN NCSEL1 NCSEL2 NCPAD1 NCPAD2 ATHR AHD AATT AGC LTHR LHD LATT LGC LINEEN PCMSEL SLPTHR MCUSEL ECSEL GLPADTHR TPAD1 TPAD2 TPAD3 TPAD4 RPAD1 RPAD2 RPAD3 20 k SP LIN SYNC BCLK PCMI PCMO PCMEI PCMEO DEN SYNC BCLK DIN DOUT MIC Controller EXCK DIN DOUT RESET PDN/RST RST CLKSEL SYNCSEL TEST1 TEST2 TEST3 3 V(D) TEST4 TEST9 DVDD1 + 0.1 F 10 F DVDD2 DGND1 DGND2 3 V(A) 10 F 0.1 F 0.1 F + AVDD AGND SG +10 F MCK/X1 X2 RPAD4 1 M 19.2 MHz 10 pF 10 pF 51/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 PACKAGE DIMENSIONS (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 m or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code, and desired mounting conditions (reflow method, temperature and times). 52/53 FEDL7731-02-04 1 Semiconductor MSM7731-02 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 53/53 |
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