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PM4341A
Summary Information
T1 TRANSCEIVER FEATURES
* Monolithic single chip device which integrates a full featured T1 framer with an on-chip analog line interface. * Supports SF, ESF, T1DM (DDS) and SLC(R)96 format DS1 signals. Supports unframed mode. Supports B8ZS or AMI line codes. * Recovers clock and data from the incoming DSX-1 signal, generates DSX-1 output signal. * Supports transfer of PCM and signalling to/from 1.544 Mbit/s and 2.048 Mbit/s backplane buses. Supports gapped data streams used in higher rate multiplexing. * Provides robbed bit signalling insertion/extraction, idle code substitution, digital milliwatt code substitution, data inversion and 2 superframes of signalling debounce on a per channel basis. * Pin compatible with the PM6341 E1XC E1 Transceiver. * Software compatible with the PM4344 TQUAD Quad T1 Framer and PM4388 TOCTL Octal T1 Framer. * Provides an 8-bit microprocessor bus interface for configuration, control and status monitoring. * Low-power 5V CMOS technology. * Avalable in a high density 80-pin (14 by14mm) PQFP or in a 68-pin PLCC package.
T1XC
RECEIVE SECTION
* Provides loss of signal, red alarm, yellow alarm and AIS alarm indication. Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192 bit window. * Supports line and path performance monitoring per Bellcore, AT&T and ANSI recommendations. * Accumulators are provided for ESF CRC-6 and framing bit errors, Line Code Violations and Loss Of Frame or Change Of Frame Alignment events. * Extracts the data link in ESF, T1DM and SLC(R)96 formats. Extracts the D-channel for primary rate interfaces. * Provides ESF bit-oriented code detection and an HDLC interface for terminating the ESF datalink. * Provides a 2 frame elastic store for jitter and wander attenuation. * Detects programmable in-band loopback codes.
TRANSMIT SECTION
* Provides per channel minimum ones density through Bell (Bit 7), GTE or DDS zero code suppression. * Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192 bit window. * Inserts the data link in ESF, T1DM and SLC(R)96 formats. Inserts the Dchannel for primary rate interfaces. * Generates AIS and yellow alarm in all formats. * Inserts the data link in ESF, T1DM and SLC(R)96 formats. Inserts the Dchannel for primary rate interfaces. * Generates ESF bit-oriented codes and provides an HDLC interface for generating the ESF datalink. * Inserts programmable in-band loopback codes. * Provides a FIFO buffer for jitter attenuation and rate conversion.
BLOCK DIAGRAM
TCLK I
TR A NS M ITT E R
BT PCM /BTD P BTSIG/B TDN BT FP BTCL K
BT IF BACKPLA NE TRANS M IT INTERFAC E XB AS BASICT RANS M IT TER : FRAM E GENERA TION , ALARM INS E RT ION , TRUN K CON DITIO NING LINE CO DING TO P S TIM ING OP TIONS
DJ AT DIG ITAL JIT TER ATTE NU ATO R
XPLS ANALO G DS X-1 PULS E GE NE RATOR
TA P
TA N
TPSC PER-C HA N CO NT : SIG ,IDL E, ZE RO CONT
X IB C IN-BA ND LO OP BACK CO DE GE NE RATOR
TC
A(7-0) RD B WRB CS B
M P IF M ICRO PROCE SSOR INT ERFACE XBO C BIT ORIENTED CO DE GEN .
APPLICATIONS
* T1 & T3 Multiplexers * T1 Frame Relay Interfaces * T1 ATM UNI Interfaces * Fractional T1 * T1 Channel Service Units (CSUs) and Data Service Units (DSUs) * Digital Access and Cross-Connect Systems (DACS) and Electronic Digital Cross-Connects (EDSX) * Digital Loop Carriers (DLCs) * SONET Add-Drop Multiplexers (ADM) * ISDN Primary Rate Interfaces (PRI) * Digital Private Branch Exchanges (PBX) * T1 & T3 Test Equipment
SLC(R)96 is a registered trademark of AT&T
XPD E PULSE DE N SIT Y ENFOR CE R
DT IF DIG IT AL DS -1 TRANSM IT INT ERF ACE
TCL KO TDP/T DD TDN/T FLG
ALE INT B RS T B
X F DL HDL C TRANS M ITT E R
TDLCLK / TDL UD R TDL SIG/ TDLINT
D(7-0) BRCLK
RE CE IV E R
BRF PI XCLK /VCLK
PMO N PERFOR M ANCE M ONIT OR CO UNT E RS E LS T ELAST IC ST ORE S IG X SIG NA LLING EXTR ACTOR
RA S RE F R RC
RS L C ANA LO G DS X-1 PULSE SLICER
BRPCM /BR DP
BR IF BA CKPLAN E RE CE IV E INTERFA CE
BRSIG /B RD N BRFPO
RC L K I RD P/RDD / SD P RD N/RL CV / S DN
DR IF DIG ITAL DS -1 RX INTERFAC E
CDRC CL O CK AND DA T A RE CO VERY
FR M R F RAM ER: FRA M E ALIGNM ENT , ALARM EXT RA CT FR A M FRA M ER/ SLIP BUFFE R R AM RPSC PER -CHANN EL CON TROL : TRUNK CO ND ITION
RDP CM /RPC M RCLK O RF P
IB C D IN-BAND LO OP BACK CO DE DE TE CTO R PDVD PULS E DE NS ITY VIO LATION DE TEC TOR
AL M I ALARM INT EGR ATOR
RB O C BIT ORIENTED CO D E DE TECTO R
RF D L HDL C RE CE IV ER
RD LS IG/ RD LINT RD LCLK/ RD LEO M
PMC-920108(R7)
(c) 1998 PMC-Sierra, Inc. March, 1998
PM4341A T1XC
Summary Information
T1 TRANSCEIVER TYPICAL APPLICATIONS:
1/0 CROSS-CONNECT WITH DSX-1 INTERFACE:
STo1
STo2
STo4
STo5
STo3
STo6
STo7 STi7
D ig ital C rosspo int Sw itch
STi2 STi3 STi4 STi5 STi6 STi1 STi8
BR SIG
STo8
BR SIG
BR SIG
BR PC M
BR PC M
BR PC M
PM C
PM 4341A T1XC
TAN R EF R AS TAP TAP
PM C
PM 434 1A T1XC
TAN R AS R EF TAP
PM C
PM 4341A T1XC
R AS R EF TAN TAP
PM C
PM 4341A T1XC
TAN R AS R EF
Receive DSX-1
Receive
Receive
Transmit
Transmit
Transmit
Receive
DSX-1
DSX-1
DSX-1
FULLY CHANNELIZED QUAD DS1 HDLC CARD:
DS1
PM C
PM 4341A T1XC
DS1
PM C
PM 4341A T1XC
Processor
PM C
PM 7366 FREEDM -8 H DLC Controlle r
DS1
PM C
PM 4341A T1XC
Packet M em o ry
DS1
PM C
PM 4341A T1XC PCI Bus
Head Office: PMC-Sierra, Inc. Suite 105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200
To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn:Document Coordinator
All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com
Transmit
DSX-1
DSX-1
DSX-1
DSX-1
BR PC M
BTPC M
BTPC M
BTPC M
BTPC M
BR SIG
BTSIG
BTSIG
BTSIG
BTSIG
PMC-920108(R7)
(c) 1998 PMC-Sierra, Inc. March, 1998

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