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Microcomputer Components
16-Bit CMOS Single-Chip Microcontroller
C167SR
Data Sheet 06.95 Advance Information
Edition 06.95 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
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C167SR Revision History: Previous Releases: Page 31 36 36 37 37 39 41...43 44 46 47 52 53 56, 57 58 61
Original Version: 06.95 (Advance Information) Data Sheet C167 06.94
Subjects (changes compared to C167) Register PICON added
VILS, VIHS, HYS, IOV added. RRST, IRWH, IRWL, IALEL, IALEH, IP6H, test cond. IOZx changed. IP6L, ICC, IID changed. ICC, IID typical values added
ADC specification changed. PLL description added. External Clock Drive specification changed.
t14, t15, t16, t17, t22, t39, t46 changed. t47 changed. t14, t15, t16, t17, t20, t21, t22 changed. t39, t46, t47, t55 changed. t53 changed to t68. t36 changed. t63 changed.
C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Advance Information C167SR 16-Bit Microcontroller
q q q q q q q q q q q q q q q q q q q q q q q q q q q q
C167SR
q q
High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 x 16 bit), 1 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Clock Generation via on-chip PLL or via direct clock input Up to 16 MBytes Linear Address Space for Code and Data 2 KBytes On-Chip Internal RAM (IRAM) 2 KBytes On-Chip Extension RAM (XRAM) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses Five Programmable Chip-Select Signals Hold- and Hold-Acknowledge Bus Arbitration Support 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns 16-Channel 10-bit A/D Converter with 9.7 s Conversion Time Two 16-Channel Capture/Compare Units 4-Channel PWM Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) Programmable Watchdog Timer Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 144-Pin MQFP Package (EIAJ)
This document describes the SAB-C167SR-LM, the SAF-C167SR-LM and the SAK-C167SR-LM. For simplicity all versions are referred to by the term C167SR throughout this document.
Semiconductor Group
1
06.95
C167SR
C167SR Revision History: Previous Releases: Page 31 36 36 37 37 39 41...43 44 46 47 52 53 56, 57 58 61
Original Version: 06.95 (Advance Information) Data Sheet C167 06.94
Subjects (changes compared to C167) Register PICON added
VILS, VIHS, HYS, IOV added. RRST, IRWH, IRWL, IALEL, IALEH, IP6H, test cond. IOZx changed. IP6L, ICC, IID changed. ICC, IID typical values added
ADC specification changed. PLL description added. External Clock Drive specification changed.
t14, t15, t16, t17, t22, t39, t46 changed. t47 changed. t14, t15, t16, t17, t20, t21, t22 changed. t39, t46, t47, t55 changed. t53 changed to t68. t36 changed. t63 changed.
Semiconductor Group
2
C167SR
Introduction The C167SR is a new derivative of the Siemens C16x Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip high-speed RAM and clock generation via PLL.
C167SR
Figure 1 Logic Symbol Ordering Information Type SAB-C167SR-LM Ordering Code Q67121-C952 Package P-MQFP-144-1 Function 16-bit microcontroller with 2 x 2 KByte RAM Temperature range 0 to + 70 C 16-bit microcontroller with 2 x 2 KByte RAM Temperature range - 40 to + 85 C 16-bit microcontroller with 2 x 2 KByte RAM Temperature range - 40 to + 125 C
SAF-C167SR-LM
Q67121-C953
P-MQFP-144-1
SAK-C167SR-LM
C
P-MQFP-144-1
Semiconductor Group
3
C167SR
Pin Configuration (top view)
C167SR
Figure 2
Semiconductor Group
4
C167SR
Pin Definitions and Functions Symbol P6.0 P6.7 Pin Input (I) Number Output (O) 18 I/O Function Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The following Port 6 pins also serve for alternate functions: P6.0 CS0 Chip Select 0 Output ... ... ... P6.4 CS4 Chip Select 4 Output P6.5 HOLD External Master Hold Request Input P6.6 HLDA Hold Acknowledge Output Bus Request Output P6.7 BREQ Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out ... ... ... P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: P7.0 POUT0 PWM Channel 0 Output ... ... ... P7.3 POUT3 PWM Channel 3 Output P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out ... ... ... P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out
1 ... 5 6 7 8 P8.0 P8.7 916
O ... O I O O I/O
9 ... 16 P7.0 P7.7 19 26
I/O ... I/O I/O
19 ... 22 23 ... 26
O ... O I/O ... I/O
Semiconductor Group
5
C167SR
Pin Definitions and Functions (cont'd) Symbol P5.0 P5.15 Pin Input (I) Number Output (O) 27 - 36 39 - 44 I I Function Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out ... ... ... P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out, EX0IN Fast External Interrupt 0 Input ... ... ... P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out, EX7IN Fast External Interrupt 7 Input T7IN CAPCOM2 Timer T7 Count Input
39 40 41 42 43 44 P2.0 P2.15 47 - 54 57 - 64
I I I I I I I/O
47 ... 54 57 ... 64
I/O ... I/O I/O I ... I/O I I
Semiconductor Group
6
C167SR
Pin Definitions and Functions (cont'd) Symbol P3.0 P3.13, P3.15 Pin Input (I) Number Output (O) 65 - 70, 73 - 80, 81 I/O I/O I/O Function Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.) Ext. Memory High Byte Enable Signal, P3.12 BHE WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line ... ... ... P4.4 A20 Least Significant Segment Addr. Line .. : : P4.7 A23 Most Significant Segment Addr. Line External Memory Read Strobe. RD is activated for every external instruction or data read access.
65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 P4.0 P4.7 85 - 92
I O I O I I I I I/O I/O O I/O O O I/O O I/O
85 ... 89 ... 92 RD 95
O ... O ... O O
Semiconductor Group
7
C167SR
Pin Definitions and Functions (cont'd) Symbol WR/ WRL Pin Input (I) Number Output (O) 96 O Function External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the C167SR to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. ROMless versions must have this pin tied to `0'. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0- P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15
READY
97
I
ALE
98
O
EA
99
I
PORT0: P0L.0 P0L.7, P0H.0 P0H.7
I/O 100 107 108, 111-117
Semiconductor Group
8
C167SR
Pin Definitions and Functions (cont'd) Symbol PORT1: P1L.0 P1L.7, P1H.0 P1H.7 Pin Input (I) Number Output (O) I/O 118 125 128 135 Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4 CC24IO CAPCOM2: CC24 Capture Input P1H.5 CC25IO CAPCOM2: CC25 Capture Input P1H.6 CC26IO CAPCOM2: CC26 Capture Input P1H.7 CC27IO CAPCOM2: CC27 Capture Input XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C167SR. An internal pullup resistor permits poweron reset using only a capacitor connected to VSS. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C167SR to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Reference voltage for the A/D converter. Reference ground for the A/D converter. Flash programming voltage. This pin accepts the programming voltage for flash versions of the C167SR. Note: This pin is not connected (NC) on non-flash versions.
132 133 134 135 XTAL1 XTAL2 138 137
I I I I I O
RSTIN
140
I
RSTOUT 141
O
NMI
142
I
VAREF VAGND VPP
37 38 84
- - -
Semiconductor Group
9
C167SR
Pin Definitions and Functions (cont'd) Symbol Pin Input (I) Number Output (O) 17, 46, - 56, 72, 82, 93, 109, 126, 136, 144 18, 45, - 55, 71, 83, 94, 110, 127, 139, 143 Function Digital Supply Voltage: + 5 V during normal operation and idle mode. 2.5 V during power down mode.
VCC
VSS
Digital Ground.
Semiconductor Group
10
C167SR
Functional Description The architecture of the C167SR combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C167SR. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section).
Figure 3 Block Diagram
Semiconductor Group
11
C167SR
Memory Organization The memory space of the C167SR is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C167SR is prepared to incorporate on-chip mask-programmable ROM or Flash Memory for code or constant data. Currently no ROM is integrated. 2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 x 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C16x family. 2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitadressable. The XRAM allows 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed - 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed - 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed - 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory TriState Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Up to 5 external CS signals can be generated in order to save external glue logic. Access to very slow memories is supported via a particular `Ready' function. A HOLD/HLDA protocol is available for bus arbitration. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.
Semiconductor Group
12
C167SR
Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C167SR's instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4 CPU Block Diagram
Semiconductor Group
13
C167SR
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C167SR instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Semiconductor Group
14
C167SR
Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C167SR is capable of reacting very fast to the occurence of nondeterministic events. The architecture of the C167SR supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C167SR has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible C167SR interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Note: Three nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
Semiconductor Group
15
C167SR
Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 Semiconductor Group
Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR
Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE 16
Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT
Vector Location 00'0040H 00'0044H 00'0048H 00'004CH 00'0050H 00'0054H 00'0058H 00'005CH 00'0060H 00'0064H 00'0068H 00'006CH 00'0070H 00'0074H 00'0078H 00'007CH 00'00C0H 00'00C4H 00'00C8H 00'00CCH 00'00D0H 00'00D4H 00'00D8H 00'00DCH 00'00E0H 00'00E4H 00'00E8H 00'00ECH 00'00E0H 00'0110H 00'0114H 00'0118H 00'0080H
Trap Number 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 44H 45H 46H 20H
C167SR
Source of Interrupt or PEC Service Request CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 X-Peripheral Node X-Peripheral Node X-Peripheral Node PLL Unlock
Request Flag T1IR T7IR T8IR T2IR T3IR T4IR T5IR T6IR CRIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR
Enable Flag T1IE T7IE T8IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE
Interrupt Vector T1INT T7INT T8INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT
Vector Location 00'0084H 00'00F4H 00'00F8H 00'0088H 00'008CH 00'0090H 00'0094H 00'0098H 00'009CH 00'00A0H 00'00A4H 00'00A8H 00'011CH 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'00FCH 00'0100H 00'0104H 00'0108H 00'010CH
Trap Number 21H 3DH 3EH 22H 23H 24H 25H 26H 27H 28H 29H 2AH 47H 2BH 2CH 2DH 2EH 2FH 3FH 40H 41H 42H 43H
A/D Conversion Complete ADCIR
Semiconductor Group
17
C167SR
The C167SR also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during runtime: Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction NMI STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS Trap Flag Trap Vector RESET RESET RESET Vector Location 00'0000H 00'0000H 00'0000H Trap Number 00H 00H 00H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH Trap Priority III III III II II II I I I I I
NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H
[2CH - 3CH] [0BH - 0FH] Any [00'0000H - 00'01FCH] in steps of 4H Any [00H - 7FH] Current CPU Priority
Semiconductor Group
18
C167SR
Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 400 ns (at 20-MHz system clock). The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Both of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin (except for CC24...CC27) to indicate the occurence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`capture'd) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.
Compare Modes Mode 0 Mode 1 Mode 2 Mode 3 Double Register Mode
Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.
Semiconductor Group
19
C167SR
*)
*) 12 outputs on CAPCOM2
Figure 5 CAPCOM Unit Block Diagram
Semiconductor Group
20
C167SR
PWM Module The Pulse Width Modulation Module can generate up to four PWM output signals using edgealigned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the PWM signals covers 4.8 Hz to 1 MHz (referred to a CPU clock of 20 MHz), depending on the resolution of the PWM output signal. The level of the output signals is selectable and the PWM module can generate interrupt requests.
General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20-MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking. Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer overflow/underflow. The state of these latches may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.
Semiconductor Group
21
C167SR
The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.
Figure 6 Block Diagram of GPT1
Semiconductor Group
22
C167SR
Figure 7 Block Diagram of GPT2
Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 s and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz). Semiconductor Group 23
C167SR
A/D Converter For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C167SR supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter.
Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). ASC0 is upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 KBaud and half-duplex synchronous communication up to 2.5 Mbaud on the @ 20-MHz system clock. The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20-MHz system clock. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel.
Semiconductor Group
24
C167SR
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.
Parallel Ports The C167SR provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. All port lines that are not used for these alternate functions may be used as general purpose IO lines.
Semiconductor Group
25
C167SR
Instruction Set Summary The table below lists the instructions of the C167SR in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C16x Family Instruction Set Manual". This document also provides a detailled description of each instruction.
Instruction Set Summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR Semiconductor Group Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR 26 Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2
C167SR
Instruction Set Summary (cont'd) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack und update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2/4 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Semiconductor Group
27
C167SR
Special Function Registers Overview The following table lists all SFRs which are implemented in the C167SR in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Special Function Registers Overview Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC Physical Address b FF98H b FFA0H FEA0H FE18H FE1AH FE1CH FE1EH b FF9AH 8-Bit Description Address CCH D0H 50H 0CH 0DH 0EH 0FH CDH 86H 8AH 8BH 8CH 8DH 25H 40H BCH 41H BDH 42H BEH A/D Converter End of Conversion Interrupt Control Register A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D Converter Overrun Error Interrupt Control Register Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Register CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Register CAPCOM Register 2 CAPCOM Register 2 Interrupt Control Register Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0XX0H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
F0A0H E 50H
BUSCON0 b FF0CH BUSCON1 b FF14H BUSCON2 b FF16H BUSCON3 b FF18H BUSCON4 b FF1AH CAPREL CC0 CC0IC CC1 CC1IC CC2 CC2IC FE4AH FE80H b FF78H FE82H b FF7AH FE84H b FF7CH
Semiconductor Group
28
C167SR
Special Function Registers Overview (cont'd) Name CC3 CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 CC7IC CC8 CC8IC CC9 CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CC16 CC16IC CC17 Physical Address FE86H b FF7EH FE88H b FF80H FE8AH b FF82H FE8CH b FF84H FE8EH b FF86H FE90H b FF88H FE92H b FF8AH FE94H b FF8CH FE96H b FF8EH FE98H b FF90H FE9AH b FF92H FE9CH b FF94H FE9EH b FF96H FE60H FE62H 8-Bit Description Address 43H BFH 44H C0H 45H C1H 46H C2H 47H C3H 48H C4H 49H C5H 4AH C6H 4BH C7H 4CH C8H 4DH C9H 4EH CAH 4FH CBH 30H 31H CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Register CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Register CAPCOM Register 5 CAPCOM Register 5 Interrupt Control Register CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Register CAPCOM Register 7 CAPCOM Register 7 Interrupt Control Register CAPCOM Register 8 CAPCOM Register 8 Interrupt Control Register CAPCOM Register 9 CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 CAPCOM Register 11 Interrupt Control Register CAPCOM Register 12 CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 CAPCOM Register 14 Interrupt Control Register CAPCOM Register 15 CAPCOM Register 15 Interrupt Control Register CAPCOM Register 16 CAPCOM Register 16 Interrupt Control Register CAPCOM Register 17 Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
b F160H E B0H
Semiconductor Group
29
C167SR
Special Function Registers Overview (cont'd) Name CC17IC CC18 CC18IC CC19 CC19IC CC20 CC20IC CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CC31IC Physical Address 8-Bit Description Address CAPCOM Register 17 Interrupt Control Register CAPCOM Register 18 CAPCOM Register 18 Interrupt Control Register CAPCOM Register 19 CAPCOM Register 19 Interrupt Control Register CAPCOM Register 20 CAPCOM Register 20 Interrupt Control Register CAPCOM Register 21 CAPCOM Register 21 Interrupt Control Register CAPCOM Register 22 CAPCOM Register 22 Interrupt Control Register CAPCOM Register 23 CAPCOM Register 23 Interrupt Control Register CAPCOM Register 24 CAPCOM Register 24 Interrupt Control Register CAPCOM Register 25 CAPCOM Register 25 Interrupt Control Register CAPCOM Register 26 CAPCOM Register 26 Interrupt Control Register CAPCOM Register 27 CAPCOM Register 27 Interrupt Control Register CAPCOM Register 28 CAPCOM Register 28 Interrupt Control Register CAPCOM Register 29 CAPCOM Register 29 Interrupt Control Register CAPCOM Register 30 CAPCOM Register 30 Interrupt Control Register CAPCOM Register 31 CAPCOM Register 31 Interrupt Control Register Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
b F162H E B1H FE64H FE66H FE68H FE6AH FE6CH FE6EH FE70H FE72H FE74H FE76H FE78H FE7AH FE7CH FE7EH 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH b F164H E B2H b F166H E B3H b F168H E B4H b F16AH E B5H b F16CH E B6H b F16EH E B7H b F170H E B8H b F172H E B9H b F174H E BAH b F176H E BBH b F178H E BCH b F184H E C2H b F18CH E C6H b F194H E CAH
Semiconductor Group
30
C167SR
Special Function Registers Overview (cont'd) Name CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 CP CRIC CSP DP0L DP0H DP1L DP1H DP2 DP3 DP4 DP6 DP7 DP8 DPP0 DPP1 DPP2 DPP3 EXICON MDC MDH MDL Physical Address b FF52H b FF54H b FF56H b FF58H b FF22H b FF24H b FF26H b FF28H FE10H b FF6AH FE08H 8-Bit Description Address A9H AAH ABH ACH 91H 92H 93H 94H 08H B5H 04H CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 5 CAPCOM Mode Control Register 6 CAPCOM Mode Control Register 7 CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (read only) P0L Direction Control Register P0H Direction Control Register P1L Direction Control Register P1H Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register Port 7 Direction Control Register Port 8 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H FC00H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 00H 00H 00H 00H 0000H 0001H 0002H 0003H 0000H 0000H 0000H 0000H
b F100H E 80H b F102H E 81H b F104H E 82H b F106H E 83H b FFC2H b FFC6H b FFCAH b FFCEH b FFD2H b FFD6H FE00H FE02H FE04H FE06H b FF0EH FE0CH FE0EH E1H E3H E5H E7H E9H EBH 00H 01H 02H 03H 87H 06H 07H
b F1C0H E E0H
Semiconductor Group
31
C167SR
Special Function Registers Overview (cont'd) Name ODP2 ODP3 ODP6 ODP7 ODP8 ONES P0L P0H P1L P1H P2 P3 P4 P5 P6 P7 P8 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PICON PP0 PP1 PP2 Physical Address 8-Bit Description Address Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Port 7 Open Drain Control Register Port 8 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Port 6 Register (8 bits) Port 7 Register (8 bits) Port 8 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port Input Threshold Control Register PWM Module Period Register 0 PWM Module Period Register 1 PWM Module Period Register 2 Reset Value 0000H 0000H 00H 00H 00H FFFFH 00H 00H 00H 00H 0000H 0000H 00H XXXXH 00H 00H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
b F1C2H E E1H b F1C6H E E3H b F1CEH E E7H b F1D2H E E9H b F1D6H E EBH FF1EH b FF00H b FF02H b FF04H b FF06H b FFC0H b FFC4H b FFC8H b FFA2H b FFCCH b FFD0H b FFD4H FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH 8FH 80H 81H 82H 83H E0H E2H E4H D1H E6H E8H EAH 60H 61H 62H 63H 64H 65H 66H 67H
F1C4H E E2H F038H E 1CH F03AH E 1DH F03CH E 1EH
Semiconductor Group
32
C167SR
Special Function Registers Overview (cont'd) Name PP3 PSW PT0 PT1 PT2 PT3 PW0 PW1 PW2 PW3 Physical Address 8-Bit Description Address PWM Module Period Register 3 CPU Program Status Word PWM Module Up/Down Counter 0 PWM Module Up/Down Counter 1 PWM Module Up/Down Counter 2 PWM Module Up/Down Counter 3 PWM Module Pulse Width Register 0 PWM Module Pulse Width Register 1 PWM Module Pulse Width Register 2 PWM Module Pulse Width Register 3 PWM Module Control Register 0 PWM Module Control Register 1 PWM Module Interrupt Control Register Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXH 0000H
F03EH E 1FH b FF10H 88H F030H E 18H F032H E 19H F034H E 1AH F036H E 1BH FE30H FE32H FE34H FE36H 18H 19H 1AH 1BH 98H 99H
PWMCON0 b FF30H PWMCON1 b FF32H PWMIC RP0H S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON
b F17EH E BFH b F108H E 84H FEB4H b FFB0H b FF70H FEB2H b FF6EH 5AH D8H B8H 59H B7H
System Startup Configuration Register (Rd. only) XXH Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register
b F19CH E CEH FEB0H b FF6CH FE12H b FFB2H 58H B6H 09H D9H
Serial Channel 0 Transmit Buffer Interrupt Control 0000H Register Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register 00H 0000H FC00H 0000H 0000H
F0B4H E 5AH
Semiconductor Group
33
C167SR
Special Function Registers Overview (cont'd) Name SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON T0 T01CON T0IC T0REL T1 T1IC T1REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON Physical Address b FF76H b FF74H b FF72H FE14H FE16H b FF12H FE50H b FF50H b FF9CH FE54H FE52H b FF9EH FE56H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H b FF64H FE46H b FF46H b FF66H FE48H b FF48H 8-Bit Description Address BBH BAH B9H 0AH 0BH 89H 28H A8H CEH 2AH 29H CFH 2BH 20H A0H B0H 21H A1H B1H 22H A2H B2H 23H A3H B3H 24H A4H SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Control Register CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register Reset Value 0000H XXXXH 0000H 0000H 0000H FA00H FC00H 0xx0H1) 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
F0B2H E 59H F0B0H E 58H
Semiconductor Group
34
C167SR
Special Function Registers Overview (cont'd) Name T6IC T7 T78CON T7IC T7REL T8 T8IC T8REL TFR WDT WDTCON XP0IC XP1IC XP2IC XP3IC ZEROS
1) 2)
Physical Address b FF68H b FF20H
8-Bit Description Address B4H 90H GPT2 Timer 6 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Control Register CAPCOM Timer 7 Interrupt Control Register CAPCOM Timer 7 Reload Register CAPCOM Timer 8 Register CAPCOM Timer 8 Interrupt Control Register CAPCOM Timer 8 Reload Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register X-Peripheral 0 Interrupt Control Register X-Peripheral 1 Interrupt Control Register X-Peripheral 2 Interrupt Control Register PLL Interrupt Control Register Constant Value 0's Register (read only)
Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 000XH2) 0000H 0000H 0000H 0000H 0000H
F050H E 28H b F17AH E BEH F054H E 2AH F052H E 29H b F17CH E BFH F056H E 2BH b FFACH FEAEH FFAEH D6H 57H D7H
b F186H E C3H b F18EH E C7H b F196H E CBH b F19EH E CFH b FF1CH 8EH
The system configuration is selected during reset. Bit WDTR indicates a watchdog timer triggered reset.
Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
Semiconductor Group
35
C167SR
Absolute Maximum Ratings Ambient temperature under bias (TA): SAB-C167SR-LM............................................................................................................0 to + 70 C SAF-C167SR-LM ....................................................................................................... - 40 to + 85 C SAK-C167SR-LM..................................................................................................... - 40 to + 125 C Storage temperature (TST)........................................................................................ - 65 to + 150 C Voltage on VCC pins with respect to ground (VSS) ..................................................... - 0.5 to + 6.5 V Voltage on any pin with respect to ground (VSS) .................................................- 0.5 to VCC + 0.5 V Input current on any pin during overload condition .................................................. - 10 to + 10 mA Absolute sum of all input currents during overload condition.............................................. |100 mA| Power dissipation..................................................................................................................... 1.5 W
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings.
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167SR and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C167SR will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C167SR.
Semiconductor Group
36
C167SR
DC Characteristics
VCC = 5 V 10 %; VSS = 0 V; fCPU = 20 MHz; TA = 0 to + 70 C for SAB-C167SR-LM TA = - 40 to + 85 C for SAF-C167SR-LM TA = - 40 to + 125 C for SAK-C167SR-LM
Parameter Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage, all except RSTIN and XTAL1 (TTL) Input high voltage RSTIN Input high voltage XTAL1 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Symbol min.
Reset active
Limit Values max. 0.2 VCC - 0.1 2.0
Unit V V V V V V mV V
Test Condition - - - - - - -
VIL
SR - 0.5
VILS SR - 0.5 VIH
SR 0.2 VCC + 0.9
VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5
- 0.45
VIH1 SR 0.6 VCC VIH2 SR 0.7 VCC VIHS SR 0.8 VCC
- 0.2
HYS
400
VOL CC - Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT)
Output low voltage (all other outputs)
IOL = 2.4 mA
VOL1 CC -
0.45 -
V V
IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA
0.45V < VIN < VCC 0.45V < VIN < VCC
5) 8)
VOH CC 0.9 VCC Output high voltage 2.4 (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT)
Output high voltage (all other outputs)
1)
VOH1 CC 0.9 VCC
2.4
- 200 500 5 250 - 40 - 40 - - 40
V V nA nA mA k A A A A A
Input leakage current (Port 5) Input leakage current (all other) Overload current RSTIN pullup resistor Read/Write inactive current Read/Write active current ALE inactive current 4) ALE active current 4) Port 6 inactive current
4) 4) 4)
IOZ1 CC - IOZ2 CC - IOV IRWH IRWL IALEL IALEH IP6H
SR -
2) 3) 2) 3) 2)
RRST CC 50
- - 500 - 500 -
-
VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V
Semiconductor Group
37
C167SR
Parameter Port 6 active current 4) PORT0 configuration current XTAL1 input current Pin capacitance 5) (digital inputs/outputs) Power supply current Idle mode supply current Power-down mode supply current
4)
Symbol min.
Limit Values max. - - 10 - 20 10 20 + 5 x fCPU 20 + 2 x fCPU 100 - 500 - - 100
Unit A A A A pF mA mA A
Test Condition
IP6L IP0H IP0L IIL
3) 2) 3)
VOUT = VOL1max VIN = VIHmin VIN = VILmax
0 V < VIN < VCC
CC -
CIO CC - ICC IID IPD
- - -
f = 1 MHz TA = 25 C
RSTIN = VIL2 fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6)
VCC = 5.5 V 7)
Notes
1)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. Not 100 % tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VCCmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VCC - 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA.
2) 3) 4)
5) 6)
7)
8)
Semiconductor Group
38
C167SR
Figure 8 Supply/Idle Current as a Function of Operating Frequency
Semiconductor Group
39
C167SR
A/D Converter Characteristics
VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB-C167SR-LM TA = - 40 to + 85 C for SAF-C167SR-LM TA = - 40 to + 125 C for SAK-C167SR-LM 4.0 V VAREF VCC + 0.1 V; VSS - 0.1 V VAGND VSS + 0.2 V
Parameter Analog input voltage range Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Symbol Limit Values min. max. Unit V Test Condition
1) 2) 4) 3) 4)
VAIN SR VAGND tS tC
CC - CC -
VAREF
2 tSC 14 tCC + tS + 4TCL 2
TUE CC -
LSB k k pF
5)
RAREF SR - RASRC SR - CAIN CC -
tCC / 165
- 0.25
tCC in [ns] 6) 7) tS in [ns] 2) 7)
7)
tS / 330
- 0.25 33
Sample time and conversion time of the C167SR's ADC are programmable. The table below should be used to calculate the above timings. ADCON.15|14
(ADCTC)
Conversion Clock tCC TCL x 24 Reserved, do not use
TCL x 96 TCL x 48
ADCON.13|12
(ADSTC)
Sample Clock tSC
00 01 10 11
00 01 10 11
tCC tCC x 2 tCC x 4 tCC x 8
Semiconductor Group
40
C167SR
Notes
1)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively. During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tSC depend on programming and can be taken from the table above. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the table above. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results from the programmed conversion timing. Not 100 % tested, guaranteed by design characterization.
2)
3)
4) 5)
6)
7)
Semiconductor Group
41
C167SR
Testing Waveforms
AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 9 Input Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 10 Float Waveforms
Semiconductor Group
42
C167SR
AC Characteristics Definition of Internal Timing The internal operation of the C167SR is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below).
Phase Locked Loop Operation fXTAL fCPU
TCL TCL
Direct Clock Drive fXTAL fCPU
TCL TCL
Figure 11 Generation Mechanisms for the CPU Clock The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the C167SR. Direct Drive When pin P0.15 (P0H.7) is low (`0') during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fXTAL x DCmin (DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/fXTAL. Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin. Semiconductor Group 43
C167SR
Phase Locked Loop When pin P0.15 (P0H.7) is high (`1') during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by 4 (i.e. fCPU = fXTAL x 4). With every fourth transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothely, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N x TCL the minimum value is computed using the corresponding deviation DN: TCLmin = TCLNOM x (1 - DN / 100) DN = (4 - N /15) [%], where N = number of consecutive TCLs and 1 N 40.
So for a period of 3 TCLs (i.e. N = 3): D3 = 4 - 3/15 = 3.8 %, and TCLmin = TCLNOM x (1 - 3.8 / 100) = TCLNOM x 0.962 (24.1 nsec @ fCPU = 20 MHz). This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.
Figure 12 Approximated Maximum PLL Jitter
Semiconductor Group
44
C167SR
AC Characteristics External Clock Drive XTAL1
VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB-C167SR-LM TA = - 40 to + 85 C for SAF-C167SR-LM TA = - 40 to + 125 C for SAK-C167SR-LM
Parameter Oscillator period High time Low time Rise time Fall time
1) 2)
Symbol
Direct Drive 1:1 min. max. 1000
1) 2)
PLL 1:4 min. 200 10 10 - - max. 333 - - 10 2) 10
2)
Unit ns ns ns ns ns
tOSC SR 50 t1 t2 t3 t4
SR 23 SR - SR - SR 23 1) 2)
- - 10 2) 10
2)
For temperatures above TA = +85 C the minimum value for t1 and t2 is 25 ns. The clock input signal must reach the defined levels VIL and VIH2.
Figure 13 External Clock Drive XTAL1
Semiconductor Group
45
C167SR
Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values
tA tC tF
TCL x 2TCL x (15 - ) 2TCL x (1 - )
AC Characteristics Multiplexed Bus
VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB-C167SR-LM TA = - 40 to + 85 C for SAF-C167SR-LM TA = - 40 to + 125 C for SAK-C167SR-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) Semiconductor Group max. - - - - - 5 30 - - 15 + tA 10 + tA 15 + tA 15 + tA - 10 + tA - - 40 + tC 65 + tC Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 15 + tA - TCL - 10 + tA - TCL - 10 + tA - - 10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - 5 TCL + 5 - - Unit
t5 t6 t7 t8 t9 t10 t11 t12 t13
CC CC CC CC CC CC CC CC CC
46
C167SR
Parameter
Symbol
Max. CPU Clock = 20 MHz min. max. 30 + tC 55 + tC 55 + tA + tC 70 + 2tA + tC - 35 + tF - - - - 10 - tA 55 + tC + 2tA - - - 0 25 25 + tC - - - - 0 - 25 + tC 35 + tF 35 + tF 35 + tF - 5 - tA - 60 + tF 20 + tA - 5 + tA - - - - - - - 0 -
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 15 + tF - - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 0 TCL 2TCL - 25 + tC
Unit
RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR
t14 t15 t16 t17 t18 t19 t22 t23
SR SR SR SR SR SR SR CC CC CC CC SR CC CC CC CC CC SR
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2TCL - 25 + tC 2TCL - 15 + tF 2TCL - 15 + tF 2TCL - 15 + tF - 5 - tA - 3TCL - 15 + tF TCL - 5 + tA -5 + tA - - -
ALE rising edge after RD, t25 WR Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay)
t27 t38 t39 t40 t42 t43
Address float after RdCS, t44 WrCS (with RW delay) Address float after RdCS, t45 WrCS (no RW delay) RdCS to Valid Data In (with RW delay)
t46
Semiconductor Group
47
C167SR
Parameter
Symbol
Max. CPU Clock = 20 MHz min. max. 50 + tC - - - - 30 + tF - - - 40 + tC 65 + tC 35 + tC 0 - 30 + tF 30 + tF -
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. 3TCL - 25 + tC - - - - 2TCL - 20 + tF - -
Unit
RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS
t47 t48 t49 t50 t51 t52 t54 t56
SR CC CC CC SR SR CC CC
ns ns ns ns ns ns ns ns
2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF
Semiconductor Group
48
C167SR
t5
ALE
t16
t25
t38
CSx
t39
t40
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS
t7 t18
Address Data In
t54 t19
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle BUS Address
t23
Data Out
t8
WR, WRL, WRH
t10
t56 t22 t12 t50 t48
t42
WrCSx
t44
Figure 14-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 49
C167SR
t5
ALE
t16 t38 t39
t25
t40
CSx
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS Address
t7 t18
Data In
t54 t19
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle BUS Address Data Out
t23
t8
WR, WRL, WRH
t10
t56 t22 t12 t50 t48
t42
WrCSx
t44
Figure 14-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 50
C167SR
t5
ALE
t16
t25
t38
CSx
t39
t40
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS
t7 t18
Address Data In
t54 t19
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle BUS Address
t23
Data Out
t9
WR, WRL, WRH
t56 t11 t22 t13 t45 t50 t49
t43
WrCSx
Figure 14-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 51
C167SR
t5
ALE
t16 t38 t39
t25
t40
CSx
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS Address
t7 t18
Data In
t54 t19
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle BUS Address Data Out
t23
t56 t9
WR, WRL, WRH
t11 t13
t22
t43
WrCSx
t45 t49
t50
Figure 14-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 52
C167SR
AC Characteristics Demultiplexed Bus
VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB-C167SR-LM TA = - 40 to + 85 C for SAF-C167SR-LM TA = - 40 to + 125 C for SAK-C167SR-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock = 20 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1)) Data float after RD rising edge (no RW-delay 1)) Data valid to WR Data hold after WR max. - - - - - - 30 + tC 55 + tC 55 + tA + tC 70 + 2tA + tC - 35 + tF 15 + tF - - 15 + tA 10 + tA 15 + tA - 10 + tA 40 + tC 65 + tC - - - - 0 - - 25 + tC 15 + tF Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 15 + tA - TCL - 10 + tA - 10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL - 25 + tC - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 15 + 2tA + tF 1) TCL - 10 + 2tA + tF 1) - Unit
t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 t24
CC CC CC CC CC CC SR SR SR SR SR SR SR CC CC
TCL - 10 + tF -
Semiconductor Group
53
C167SR
Parameter
Symbol
Max. CPU Clock = 20 MHz min. max. - - 10 - tA 55 + tC + 2tA - - - 10 + tF 0 + tF - 5 - tA - 10 + tF 20 + tA
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. - 10 + tF 0 + tF - 5 - tA - TCL - 15 + tF TCL - 5 + tA -5 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - - - 10 + tF TCL - 15 + tF max. - - 10 - tA 3TCL - 20 + tC + 2tA - -
Unit
ALE rising edge after RD, t26 WR Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RWdelay) ALE falling edge to RdCS, WrCS (no RWdelay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS
CC CC CC SR CC CC
ns ns ns ns ns ns
t28 t38 t39 t41 t42
t43
CC
- 5 + tA
-
-
ns
t46 t47 t48 t49 t50 t51 t53 t68 t55 t57
SR SR CC CC CC SR SR SR CC CC
- - 40 + tC 65 + tC 35 + tC 0 - - - 10 + tF 10 + tF
25 + tC 50 + tC - - - - 30 + tF 5 + tF - -
2TCL - 25 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - -
ns ns ns ns ns ns ns ns ns ns
1)
RW-delay and tA refer to the next following bus cycle.
Semiconductor Group
54
C167SR
t5
ALE
t16
t26
t38
CSx
t39
t41
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t20 t18
Data In
t8
RD
t14 t12
t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH
t24
Data Out
t57 t8 t12 t42 t50 t48 t22
WrCSx
Figure 15-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 55
C167SR
t5
ALE
t16 t38 t39
t26
t41
CSx
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t20 t18
Data In
t8
RD
t14 t12 t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH
t24
Data Out
t57 t8 t12 t42 t50 t48 t22
WrCSx
Figure 15-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 56
C167SR
t5
ALE
t16
t26
t38
CSx
t39
t41
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t21 t18
Data In
t9
RD
t15 t43 t13 t47 t49 t51 t68
RdCSx
Write Cycle BUS (D15-D8) D7-D0
t24
Data Out
t9
WR, WRL, WRH
t57 t22 t13 t50 t49
t43
WrCSx
Figure 15-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 57
C167SR
t5
ALE
t16 t38 t39
t26
t41
CSx
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t21 t18
Data In
t9
RD
t15 t13 t51 t68
t43
RdCSx
t47 t49
Write Cycle BUS (D15-D8) D7-D0
t24
Data Out
t57 t9 t22 t13 t43 t50 t49
WR, WRL, WRH
WrCSx
Figure 15-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 58
C167SR
AC Characteristics CLKOUT and READY
VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB-C167SR-LM TA = - 40 to + 85 C for SAF-C167SR-LM TA = - 40 to + 125 C for SAK-C167SR-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF
Parameter Symbol Max. CPU Clock = 20 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) max. 50 - - 5 5 10 + tA - - - - - 0 + 2tA + tF
2)
Variable CPU Clock 1/2TCL = 1 to 20 MHz min. 2TCL TCL - 5 TCL - 10 - - 0 + tA 15 0 2TCL + 15 15 0 0 max. 2TCL - - 5 5 10 + tA - - - - - TCL - 25 + 2tA + tF
2)
Unit
t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60
CC CC CC CC CC CC SR SR SR SR SR SR
50 20 15 - - 0 + tA 15 0 65 15 0 0
ns ns ns ns ns ns ns ns ns ns ns ns
Notes
1) 2)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA refer to the next following bus cycle.
Semiconductor Group
59
C167SR
Running cycle 1)
READY waitstate
MUX/Tristate 6)
CLKOUT
t32 t30 t34
t33 t31 t29
7)
ALE
Command RD, WR
2)
t35
Sync READY
3)
t36
t35
3)
t36
t58
Async READY
3)
t59
t58
3) 5)
t59
t60
4)
t37
see 6)
Figure 16 CLKOUT and READY
Notes
1) 2) 3)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. The next external bus cycle may start here.
4)
5)
6)
7)
Semiconductor Group
60
C167SR
AC Characteristics External Bus Arbitration
VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB-C167SR-LM TA = - 40 to + 85 C for SAF-C167SR-LM TA = - 40 to + 125 C for SAK-C167SR-LM CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF
Parameter Symbol Max. CPU Clock = 20 MHz min. HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive max. - 20 20 20 25 20 25 20 - - - -5 - -5 20 - - - -5 - -5 Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. - 20 20 20 25 20 25 ns ns ns ns ns ns ns Unit
t61 t62 t63 t64 t65 t66 t67
SR CC CC CC CC CC CC
Semiconductor Group
61
C167SR
CLKOUT
t61
HOLD
t63
HLDA 1)
t62
BREQ
2)
t64
CSx (On P6.x)
3)
t66
Other Signals
1)
Figure 17 External Bus Arbitration, Releasing the Bus
Notes
1) 2) 3)
The C167SR will complete the currently running bus cycle before granting bus access. This is the first possibility for BREQ to get active. The CS outputs will be resistive high (pullup) after t64.
Semiconductor Group
62
C167SR
CLKOUT
2)
t61
HOLD
t62
HLDA
t62
BREQ
t62
1)
t63
t65
CSx (On P6.x)
t67
Other Signals Figure 18 External Bus Arbitration, (Regaining the Bus)
Notes
1)
This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C167SR requesting the bus. The next C167SR driven bus cycle may start here.
2)
Semiconductor Group
63

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