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CXD2434TQ
Timing Generator for Progressive Scan CCD Image Sensor For the availability of this product, please contact the sales office.
Description The CXD2434TQ is an IC developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. Features * External trigger function * Electronic shutter function * Supports non-interlaced operation * 30 frames/s * Built-in driver for the horizontal (H) clock * Base oscillation 1560 fH (24.5454 MHz) Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX084AK, ICX084AL 48 pin TQFP (Plastic)
Absolute Maximum Ratings (Ta = 25 C) * Supply voltage VCC VSS -0.5 to +7.0 * Input voltage VI VSS -0.5 to VDD +7.0 * Output voltage VI VSS -0.5 to VDD +7.0 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -55 to +150 Recommended Operating Conditions * Supply voltage VDD 4.75 to 5.25 * Operating temperature Topr -20 to +75
V V V C C
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E95605-TE
CXD2434TQ
XCPDM
XCPOB
STDBY
Block Diagram
BUSY WEN PBLK ID
SMDE
26
36
35
34
33
32
31
47
HD
46
42
29
FSE
25
VD
WM
RG H1 H2 XSHP XSHD XRS XV1 XV2 XV3 XSG CLD CL CKO
10 13 14 21 22 23 18 17 16 19 39 38 40 1/2 GATE COUNTER PULSE GENERATOR DECODE TG REGISTER
3 4 5 7 8 9
PS STRB DCLK DATA SMD1 SMD2
11
XSUB
28 TEST1 48 TEST2 41 TEST3
1
OSCO
2
OSCI
43
44
45
6
VSS
12
15
20
24
27
30
37
ESG
TRIG
XCPOB
XCPDM
TEST1
BUSY
PBLK
WEN
SMDE
Pin Configuration (Top View)
ID
EFS
VDD
VDD
VDD
36 VSS CL CLD CKO TEST3 STDBY CXD2434TQ TRIG ESG EFS HD VD TEST2 48 37
VSS
25 24 VSS XRS XSHD XSHP VDD XSG XV1 XV2 XV3 VSS H2 13 H1
1
SMD1 PS DATA OSCO SMD2 STRB XSUB OSCI VSS DCLK RG
12
--2--
VDD
FSE
WM
VDD
VSS
VSS
VSS
VSS
CXD2434TQ
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Symbol OSCO OSCI PS STRB DCLK VSS DATA SMD1 SMD2 RG XSUB VDD H1 H2 VSS XV3 XV2 XV1 XSG VDD XSHP XSHD XRS VSS FSE SMDE VSS TEST1 WM VDD XCPDM XCPOB PBLK ID WEN BUSY VSS CL CLD I/O O I I I I -- I I I O O -- O O -- O O O O -- O O O -- I I -- I I -- O O O O O O -- O O Description Inverter output for oscillation. Inverter input for oscillation. Switching for electronic shutter speed input method. (With pull-up resistor) Low: Serial input, High: Parallel input Shutter speed setting. (With pull-up resistor) Shutter speed setting. (With pull-up resistor) GND Shutter speed setting. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) Reset gate pulse output. CCD discharge pulse output. Power supply. Clock output for horizontal CCD drive. Clock output for horizontal CCD drive. GND Clock output for vertical CCD drive. Clock output for vertical CCD drive. Clock output for vertical CCD drive. Sensor charge readout pulse output. Power supply. Sample-and-hold pulse output. Sample-and-hold pulse output. Sample-and-hold pulse output. GND Switching for external trigger discharge operation. (With pull-up resistor) Low: No high-speed discharge, High: High-speed discharge Switching for readout timing. (With pull-up resistor) Low: ESG input valid, High: ESG input invalid GND Test. (With pull-down resistor) WEN mode setting. (With pull-down resistor) Low: Effective line, High: XSG synchronization Power supply. Clamp pulse output. Clamp pulse output. Blanking cleaning pulse output. Line identification output. Write enable output. Trigger mode flag output. GND 780 fH clock output. AD conversion pulse output.
--3--
CXD2434TQ
Pin No. 40 41 42 43 44 45 46 47 48
Symbol CKO TEST3 STDBY TRIG ESG EFS HD VD TEST2
I/O O I I I I I I I I 1560 fH clock output.
Description
Test. (With pull-up resistor) Standby. (With pull-up resistor) Low: Internal clock supply stopped, High: Normal External trigger input. (With pull-up resistor) External readout input. (With pull-up resistor) Vertical CCD discharge input. (With pull-up resistor) Horizontal sync signal input. Vertical sync signal input. Test. (With pull-up resistor)
Note) Pins with built-in pull-up or pull-down resistors should be connected to VDD or VSS in locations with high noise.
Electrical Characteristics 1. DC Characteristics VDD = 4.75 V to 5.25 V Topr = -20 to +75 C Min. 4.75 0.7 VDD 0.7 VDD 0.3 VDD VDD-0.4 0.4 VDD-0.4 0.4 VDD-0.4 0.4 VDD-0.4 0.4 VDD/2 VDD/2 1M 50 k 50 k 40 100 k 100 k Typ. 5.0 Max. 5.25 0.3 VDD Unit V V V V V V V V V V V V V V V mA
Item Symbol Conditions Supply voltage VDD Input voltage 1 VIH1 (Input pins other than those listed below) VIL1 Input voltage 2 VIH2 (Pin 2) VIL2 Output voltage 1 VOH1 IOH = -2.5 mA (Output pins other than those listed below) VOL1 IOL = 4.5 mA Output voltage 2 VOH2 IOH = -5.0 mA (Pins 21, 22, 23, 38, 39 and 40) VOL2 IOL = 9.0 mA Output voltage 3 VOH3 IOH = -7.5 mA (Pin 10) VOL3 IOL = 13.5 mA Output voltage 4 VOH4 IOH = -14.0 mA (Pins 13 and 14) VOL4 IOL = 24.0 mA Output voltage 5 VOH5 (Pin 1) VOL5 Feedback resistor RFB VIN = VSS or VDD Pull-up resistor RPU VIL = 0 V Pull-down resistor RPD VIH = VDD Current consumption IDD VDD = 5 V
--4--
CXD2434TQ
2. AC Characteristics 1) Waveform characteristics of H1, H2 and RG
0.9VDD
H1 0.1VDD tRH1 tWH1 tFH1
0.9VDD H2 0.1VDD tFH2 tWH2 tRH2
0.9VDD RG 0.1VDD tRRG tWRG tFRG
VDD = 5.0 V, Topr = 25 C, load capacitance of H1 and H2 = 100 pF, load capacitance of RG = 10 pF Symbol Definition Min. Typ. Max. Unit tRH1 H1 rise time 6 15 ns tFH1 H1 fall time 5 15 ns tWH1 H1 high level time 25 35 ns tRH2 H2 rise time 6 15 ns tFH2 H2 fall time 5 15 ns tWH2 H2 low level time 25 35 ns tRRG RG rise time 2 5 ns tFRG RG fall time 2 5 ns tWRG RG high level time 10 15 20 ns
--5--
CXD2434TQ
2) Phase characteristics of H1, H2, RG, XSHP, XSHD, XRS, CL, CLD and CKO
tH1 0.5VDD 0.5VDD 0.5VDD
H1
H2 tPD3 0.5VDD tPD4 tW1 XSHP 0.5VDD 0.5VDD
0.5VDD tPD1 tPD2
0.5VDD
RG
tPD5
0.5VDD tW2 tPD6
XSHD
0.5VDD tPD7 0.5VDD
0.5VDD
0.5VDD tPD8 tPD9 0.5VDD tW3
XRS
CLD tPD10 tW4 CL 0.5VDD
0.5VDD
0.5VDD tW5
CKO
0.5VDD tPD11
0.5VDD 0.5VDD
tW5 tPD11
0.5VDD
VDD = 5.0 V, Topr = 25 C, load capacitance of CL and CKO = 30 pF, load capacitance of CLD, XSHP, XSHD, XRS and RG = 10 pF Symbol tH1 tPD1 tPD2 tPD3 tPD4 tPD5 tPD6 tPD7 tPD8 tPD9 tPD10 tPD11 tW1 tW2 tW3 tW4 tW5 Definition H1 cycle H2 rising delay, activated by the falling edge of H1 H2 falling delay, activated by the rising edge of H1 H1 rising delay, activated by the rising edge of RG XSHP falling delay, activated by the falling edge of RG H1 falling delay, activated by the rising edge of XSHP H1 rising delay, activated by the rising edge of XSHD CLD falling delay, activated by the falling edge of XSHD CLD falling delay, activated by the rising edge of XRS XRS falling delay, activated by the falling edge of CLD CL falling delay, activated by the rising edge of H1 H1 rising (falling) delay, activated by the rising edge of CKO XSHP pulse width XSHD pulse width CLD pulse width CL pulse width CKO pulse width --6-- Min. -5 -5 -5 -2 -7 -5 -5 17 0 -5 -5 13 15 17 38 17 Typ. 82 0 0 0 4 2 2 2 22 8 0 2 18 20 22 41 20 Max. 5 5 5 10 7 7 7 27 15 5 7 23 25 27 45 24 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CXD2434TQ
3) Phase conditions of HD, VD, TRIG, EFS and ESG
CL
0.5VDD tSETUP tHOLD
HD, VD, TRIG, EFS, ESG
0.5VDD
0.5VDD
VDD = 5.0 V, Topr = 25 C, load capacitance of CL = 30 pF Symbol tSETUP tHOLD Definition HD, VD, TRIG, EFS and ESG setup time, activated by CL HD, VD, TRIG, EFS and ESG hold time, activated by CL Min. 20 5 Typ. Max. Unit ns ns
4) Phase characteristics of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID
CL
0.5VDD
0.5VDD
tPDCL1 XV1, XV2, XV3 0.5VDD
tPDCL2 BUSY, WEN, ID 0.5VDD
tPDCL3 XSG, PBLK, XCPDM, XCPOB 0.5VDD
VDD = 5.0 V, Topr = 25 C, load capacitance of CL = 30 pF, load capacitance of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID = 10 pF Symbol Definition tPDCL1 XV1, XV2 and XV3 delay, activated by the falling edge of CL tPDCL2 BUSY, WEN and ID delay, activated by the rising edge of CL XSG, PBLK, XCPDM and XCPOB delay, activated by the tPDCL3 rising edge of CL Min. 30 40 40 Typ. Max. 65 60 55 Unit ns ns ns
--7--
CXD2434TQ
Description of Functions 1. Progressive Scan CCD drive pulse generation * Combining this IC with a crystal oscillator generates a fundamental frequency of 24.5454 MHz. * CCD drive pulse generation is synchronized with the HD and VD inputs. Set fCL to 780 fHD and fHD to 525 fVD. * The various operations are performed by the TRIG, EFS and ESG inputs. (See the following items.)
CL 1 HD 35
H1 T1 Detection timing for VD, TRIG, EFS and ESG
After HD input is detected, the status of VD, TRIG, ESG and EFS is detected during T1. Do not change the status of VD, TRIG, ESG and EFS during T1. When input is from a non-synchronized system, the low level period for each pulse should be set to 63.5 s or longer to prevent misoperation.
--8--
CXD2434TQ
2. Electronic shutter The electronic shutter has the following four shutter modes. * Electronic shutter off: Exposure time is 1/30 s. * High-speed electronic shutter: Exposure time is shorter than 1/30 s. * Low-speed electronic shutter: Exposure time is longer than 1/30 s. * Flickerless: Exposure time is 1/50 s. This is a special feature of the high-speed electronic shutter, and reduces flicker from fluorescent lights, etc. in areas with 50 Hz power supply PS = Low: Serial input; set by the STRB, DCLK and DATA pins. The SMD1 and SMD2 pins are not used. PS = High: Parallel input; set by the STRB, DCLK, DATA, SMD1 and SMD2 pins. 2-1. [Serial input] Serial input is set by the STRB, DCLK and DATA pins. The electronic shutter mode and the meanings of the numbers indicated by D0 to 9 vary according to the SMD1 and SMD2 setting of the internal register.
STRB DCLK DATA
SMD2 SMD1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SMD1 H L H
SMD2 H H L
Mode Electronic shutter off (1/30 s accumulation) High-speed electronic shutter Low-speed electronic shutter
D0 to 9 -- Number of exposed lines (Note 1) Number of exposed frames (Note 2)
Note 1) Relationship between the number of exposed lines and the exposure time The relationship between the number of exposed lines and the exposure time is as follows. (Exposure time) = (Number of exposed lines) x (One horizontal scan period) + (Accumulation time for the readout lines) In this formula, one horizontal scan period equals the HD falling interval, and the accumulation time for the readout lines is the time from the rising edge of XSUB to the rising edge of XSG (456 bits). Also, (Number of exposed lines) should be set to greater than 1 but less than 524. Note 2) The number of exposed frames should be set to greater than 1 but less than 1023. However, when the number of exposed frames is 1 and SMDE is set to high, external trigger mode does not function. Timing Chart (Serial input)
STRB tWD DCLK tSDD DATA tHDD tSDS tWS
--9--
CXD2434TQ
AC characteristics for serial input Symbol tSDD tHDD tSDS tWS tWD Definition DATA setup time, activated by the rising edge of DCLK DATA hold time, activated by the rising edge of DCLK DCLK setup time, activated by the falling edge of STRB STRB pulse width DCLK pulse width Min. 10 ns 10 ns 10 ns 82 ns 82 ns Max. -- -- -- -- --
2-2. [Parallel input] Mode Electronic shutter off Flickerless PS H H H H H H H H H H H H H H H H H H SMD1 H L L L L L L L L L H H H H H H H H SMD2 H L H H H H H H H H L L L L L L L L STRB X X H L H L H L H L H L H L H L H L DCLK X X H H L L H H L L H H L L H H L L DATA X X H H H H L L L L H H H H L L L L Exposure time 1/30 s 1/50 s 1/60 s 1/125 s 1/250 s 1/500 s 1/1000 s 1/2000 s 1/4000 s 1/10000 s 2 FRM 3 FRM 4 FRM 5 FRM 6 FRM 7 FRM 8 FRM 9 FRM
High-speed shutter
Low-speed shutter
--10--
CXD2434TQ
3. External trigger mode External trigger mode starts exposure in sync with the external trigger input. No special pins are required to set this mode. The IC prepares to shift to external trigger mode with the falling edge of the TRIG pin (Note). The timing to shift to external trigger mode varies according to the mode setting. (See the table.) The BUSY pin maintains high status during external trigger mode. Whether or not to discharge the vertical CCD charge is set by FSE. Note) See the detection timing for VD, TRIG, EFS and ESG. Mode settings during external trigger (Note 1) PS SMD1 SMD2 Description of operation L L X The IC is shifted to external trigger mode by HD, exposure is finished after the set H L H time, and XSG is output. (Note 2) The IC is shifted to external trigger mode by HD, exposure is finished 1/50 s later, H L L and XSG is output. The IC is shifted to external trigger mode by VD and exposure is finished in sync X H L with VD after the set time. (Note 2) X H H Trigger input is not accepted. Note 1) The SMD1 and SMD2 setting method varies according to the PS status. See "2. Electronic shutter". PS = Low: Set by serial input. PS = High: Set by the SMD1 and SMD2 pins. Note 2) The exposure time setting method is the same as the exposure time setting for the electronic shutter.
During external trigger mode, the previously exposed signal charge sometimes remains in the vertical CCD when exposure finishes. In this case, the image shot with external trigger mode is output overlapped with the previously shot image. Setting FSE to high performs discharge operation for signal charges remaining in the vertical CCD after trigger input. Discharge operation is not performed when FSE is low. This setting is only valid when SMD1 is low. During external trigger mode, exposure can be finished in sync with the falling edge of ESG (Note). If SMDE is set to low, the XSG pulse is output regardless of the electronic shutter setting, when the falling edge of ESG is detected. ESG should be fixed to high status at all times other than during external trigger mode. Do not change SMDE while BUSY is high. Note) See the detection timing for VD, TRIG, EFS and ESG. After high-speed external trigger mode is finished, the exposure time differs from that performed by the electronic shutter setting. This is because the start and finish of external trigger mode are not synchronized to VD input.
--11--
CXD2434TQ
4. Discharge of the vertical CCD During EFS=L, the signal charges of the vertical CCD are discharge line by line. The IC detects the transition from High to Low. Note) See the detection timing for VD, TRIG, EFS and ESG. Vertical CCD discharge is started in sync with HD input after the falling edge of EFS (Note). 3420 ns (81.4 ns x 42 clock pulses) are required to transfer one line vertically. Note) See the detection timing for VD, TRIG, EFS and ESG. Since the operation uses 42 clock pulses as one unit, when the rising edge of EFS is detected in interval [n], discharge operation stops from interval [n + 1]. Timing Chart 1
n-1 EFS n n+1
XV1
XV3
Timing Chart 2
n CL
n+1
XV3
The number of lines transferred by discharge transfer and normal transfer during the following period should not exceed 4096 lines. Period: The period from when the XSG pin becomes low until XSG becomes low again or the TRIG pin becomes low. 5. Internal logic stop (standby mode) When the STDBY pin is set to low, clock supply is stopped to a part of the internal logic. However, output from the oscillation cell (OSCI and OSCO pins) as well as the CL and CKO pins does not stop. The status of each output pin when STDBY is low is shown below. High: Low: XSUB, XSG RG, H1, H2, XV1, XV2, XV3, XSHP, XSHD, XRS, XCPOB, XCPDM, PBLK, ID, WEN, BUSY, CLD Not stopped: OSCO, CL, CKO
--12--
CXD2434TQ
6. Mode settings 6-1. VD input-related BUSY SMD1 L H H L X X
SMD2 H L H X
SMDE X L H X
EFS X
H L
VD input Invalid Exposure is started from the first VD input. Readout operation or the number of accumulated frames is counted. Readout operation is performed. Invalid
Note 1) When PS is high, SMD1 and SMD2 indicate the status of the SMD1 and SMD2 pins, respectively. When PS is low, these are the corresponding internal register values. See "2. Electronic shutter". Note 2) Operation when PS = high, SMD1 = low and SMD2 = low conforms to that when SMD1 = low and SMD2 = high.
6-2. TRIG, ESG and EFS input-related BUSY Discharge period (Note 1) H Exposure period Signal output period Before TRIG input L After TRIG input (Note 2) (Note 3) IC shifted to external trigger mode (Note 3) Prohibited SMDE X H L Prohibited Readout operation (Note 4) Prohibited Discharge operation (Note 6) Prohibited (Note 5) Prohibited TRIG ESG Prohibited EFS Invalid
X
Note 1) Only when FSE is high. Note 2) Valid only during low-speed shutter. Note 3) See "3. External trigger mode". Note 4) ESG input is valid only one time after TRIG input. Do not input ESG two times or more. Note 5) Fix ESG to high status when BUSY is low. Note 6) When EFS is low, readout is not activated by VD input. See "6-1. VD input-related".
6-3. WEN mode switching by WM WM Description of WEN operation L Lines for which the signal from the CCD is valid output high; all other lines output low. H Output is synchronized with XSG.
--13--
Application Circuit
+5V
36 24 23
35
34
33
32
31
30
29
28
27
26
25
37
38 22 21 20 19 CXD2434TQ 18
CXD2311AR
39
40
41
42
43 17 16 15 14 13
CXA1690Q
--14--
2 3 5 7
10 11
44
45
46
47
48
1
4
6
8
9
12 +15V
100k 1000p
CXD1267AN
ICX084AK/AL
CXD2434TQ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.
Normal Operation (vertical synchronization)
VD
HD
1
14
508 510
494
OUT
123456781234
XV1
XV2
XV3
XSG
--15--
XSUB
PBLK
XCPOB
XCPDM
ID
WEN (WM=High)
WEN (WM=Low) CXD2434TQ
BUSY
Normal Operation (horizontal synchronization)
HD
1
CL 35 71 83 47 59 95 72 95
XV1
XV2
XV3
XSG (=High) XSUB
H1
H2
--16--
35 31 93
RG
XSHP
XSHD
XRS
PBLK 120 109 119
780
12
XCPOB
XCPDM
ID
WEN
BUSY CXD2434TQ
35
1
107
78
Normal Operation: readout timing (horizontal synchronization)
HD
35 107
83 78
CL
35 71
XV1
XV2
47 59
XV3
520 576
XSG
72 551
XSUB
95
H1
H2
--17--
31 93
RG
XSHP
XSHD
XRS
780 1
1
PBLK (=Low) XCPOB
12
109 119
XCPDM
ID
WEN (=Low)
BUSY =High(trig) Low(others)
CXD2434TQ
External Trigger Mode: high-speed electronic shutter, discharge (FSE = high, SMDE = high, SMD1 = low, SMD2 = high)
TRIG
VD
HD
1
27
1
14
OUT 123456781234
RG
XV1
XV2
XV3
--18--
XSG
XSUB
PBLK
XCPOB
XCPDM
ID
WEN (WM=High)
WEN (WM=Low)
CXD2434TQ
BUSY
See "2. Electronic Shutter" for the time from TRIG input to XSG.
508
External Trigger Mode: high-speed electronic shutter, when discharge starts (FSE = high, SMD1 = low, SMD2 = high)
1
2
3
TRIG
780 1
HD
CL 35 77 56 63 63 49 72 95 42
XV1
XV2
XV3
XSG (=High) XSUB
H1
--19--
35 31 93
H2
RG
XSHP
XSHD
XRS
PBLK
12
XCPOB
XCPDM
ID
WEN
BUSY CXD2434TQ
35
External Trigger Mode: high-speed electronic shutter, when discharge finishes (FSE = high, SMD1 = low, SMD2 = high)
499
500
HD
CL
XV1
XV2
XV3
XSG (=High) XSUB
H1
H2
--20--
RG
XSHP
XSHD
XRS
PBLK =(Low) XCPOB (=High) XCPDM (=High) ID
WEN (=Low) BUSY (=High) CXD2434TQ
External Trigger Mode: high-speed electronic shutter, no discharge (FSE = low, SMDE = high, SMD1 = low, SMD2 = X)
TRIG
VD
HD
1
14
OUT
123456781234
RG
XV1
XV2
XV3
--21--
XSG
XSUB
PBLK
XCPOB
XCPDM
ID
WEN (WM=High) WEN (WM=Low)
CXD2434TQ
BUSY
See "2. Electronic Shutter" for the time from TRIG input to XSG.
508
External Trigger Mode: low-speed electronic shutter (FSE = X, SMDE = high, SMD1 = high, SMD2 = low
TRIG
VD
HD
1
1
8
14
508
14
508
OUT 1234567812
123456781234
RG
XV1
XV2
XV3
--22--
XSG
XSUB
PBLK
XCPOB
XCPDM
ID
WEN (WM=High)
WEN (WM=Low)
CXD2434TQ
BUSY
See "2. Electric Shutter" for the time from XSG after TRIG input to the next XSG output.
510
Example during ESG Input (FSE = high, SMDE = low, SMD1 = low, SMD2 = X)
TRIG
ESG
VD
HD
1
27
1
14
OUT
123456781234
RG
XV1
XV2
--23--
XV3
XSG
XSUB
PBLK
XCPOB
XCPDM
ID
WEN (WM=High) WEN (WM=Low)
CXD2434TQ
BUSY
508
Example during EFS Input (trigger mode: FSE = high, SMDE = high, SMD1 = low, SMD2 = X)
TRIG
EFS 42 bits x 104 times
VD
HD
1
27
1
6
13
98 99
339
256
340
OUT
RG
XV1
XV2
--24--
XV3
XSG
XSUB
PBLK
XCPOB
XCPDM
ID
WEN (WM=High)
WEN (WM=Low)
CXD2434TQ
BUSY
264
During EFS Input, when discharge starts
EFS
CL 35 77 56 63 70 49 72 95 42
XV1
XV2
XV3
XSG (=High) XSUB
H1
H2
--25--
35 31 93
RG
XSHP
XSHD
XRS
PBLK
780
1
12
XCPOB
XCPDM
ID
WEN
BUSY CXD2434TQ
35
107
HD
During EFS Input, when discharge finishes
EFS
HD
CL
XV1
XV2
XV3
XSG (=High) XSUB
H1
H2
--26--
RG
XSHP
XSHD
XRS
PBLK =(Low) XCPOB (=High)
XCPDM (=High) ID
WEN (=Low) BUSY (=Low) CXD2434TQ
CXD2434TQ
Package Outline
Unit : mm
48PIN TQFP (PLASTIC)
9.0 0.4 7.0 0.2 36 25
1.27 MAX 1.0 0.1
0.1 37 24
A 48 13
1 0.5
12 0.2 0.1 0.08 M 0.125 0.05
0.1 0.1
+ 7 3 - 3 DETAIL A
0.5 0.2
1.0 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
TQFP-48P-L071 TQFP048-P-0707-AN
--27--

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