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* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4534B LSI Real time 5-decade counter
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Real time 5-decade counter
DESCRIPTION The HEF4534B is a 5-decade ripple counter. The binary outputs of the decade counters are time-multiplexed by an internal scanner on four BCD outputs (O0 to O3). The selected decade is indicated by a logic HIGH on the appropriate digit select output (OS0: units, 1; OS1: tens, 10; OS2: hundreds, 102; OS3: thousands, 103; OS4: ten thousands, 104). The binary outputs (O0 to O3) and the select outputs (OS0 to OS4) are 3-state controlled via enable inputs EO and EOS respectively, allowing interface with other bus orientated devices. Cascading may be accomplished by using the carry out (TC). The counter is triggered by a LOW to HIGH transition on the decade clock (CPA) and is reset by a HIGH level on the master reset (MR). The
HEF4534B LSI
scanner is triggered by a LOW to HIGH transition on the scanner clock (CPS) and is reset (select ten thousand counter) by a HIGH level on the scanner reset (MRsc). The counter can operate in four modes depending on the state of the mode select inputs (SA, SB). The error detector will detect an error when a positive edge on CPA is not accompanied by a negative edge on the error detector clock CPE or vice versa, within time limits adjusted by external capacitors connected to Cext 1 and Cext 2. Three or more detected errors result in a HIGH level on the error output (OER). The error detector is reset by a HIGH level on MR. Schmitt-trigger action in the clock inputs makes the circuit highly tolerant to slower clock rise and fall times.
Fig.1 Pinning diagram.
PINNING HEF4534BP(N): HEF4534BD(F): HEF4534BT(D): 24-lead DIL; plastic (SOT101-1) 24-lead DIL; ceramic (cerdip) (SOT94) 24-lead SO; plastic (SOT137-1) O1 to O3 OS0 to OS3 OER CPA CPS CPE SA, SB MR MRsc TC BCD outputs digit select outputs error output decade clock input scanner clock input error detector clock input mode select inputs master reset input scanner reset input carry out
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category LSI See Family Specifications January 1995 2
Philips Semiconductors
Product specification
Real time 5-decade counter
HEF4534B LSI
Fig.2 Functional block diagram.
January 1995
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Philips Semiconductors
Product specification
Real time 5-decade counter
MODE CONTROL FUNCTION TABLE SELECT INPUTS SA L SB L 1ST DECADE OUTPUT normal count and display inhibited CARRY TO 2ND STAGE CARRY TO 4TH STAGE
HEF4534B LSI
MODE
at 9 to 0 transition of the 1st decade input clock
at 9 to 0 transition of the 3rd decade input clock
5-decade counter test purposes: clock directly into stages 1, 2 and 4 4-decade counter
L
H
H
H
inhibited display counts:
at 4 to 5 transition of the 1st decade
at 9 to 0 transition of the 3rd decade
with / 10 and roundoff at front end
H
L
3, 4, 5, 6, 7 = 5 8, 9, 0, 1, 2 = 0
at 7 to 8 transition of the 1st decade
at 9 to 0 transition of the 3rd decade
1
4-decade counter; 2-pence capability
Fig.3 Error detection timing diagram.
The skew time is the time difference between the LOW to HIGH transition of CPA and the HIGH to LOW transition of CPE or vice versa (see Fig.4). The skew time is typically proportional to the external capacitor (Cext) connected from Cext1 and Cext2 (pins 1 and 22) to VSS. The error detector will count an error when a positive edge on the counter clock CPA is not succeeded by a negative edge on
the error detector clock CPE within a skew time tSK1 (adjustable by Cext1 at pin 1). The same holds for a negative edge at CPE succeeded by a positive on CPA within a skew time tSK2 (adjustable by Cext2 at pin 22). If error detection is not needed, CPE must be either HIGH or LOW and no Cext is applied. For further information see Fig.5.
Fig.4
Skew times timing diagram; tWCPA > tSK1; tWCPE > tSK2.
January 1995
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Philips Semiconductors
Product specification
Real time 5-decade counter
HEF4534B LSI
Note 1: Skew in this area results in counted error. Note 2: Skew in the area between max. and min. curves may or may not result in counted error. Note 3: Skew in this area results in no error counted.
Fig.5
Typical clock skew as a function of the supply voltage. This graph is accurate for Cext 100 pF and Tamb = 25 C.
Fig.6 Carry timing diagram.
January 1995
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Philips Semiconductors
Product specification
Real time 5-decade counter
HEF4534B LSI
Note: If SB = H, the 1st decade is inhibited and the cycle will be shortened to four stages (see dotted lines).
Fig.7 Scanner timing diagram.
Fig.8 Counter timing diagram.
January 1995
6
Philips Semiconductors
Product specification
Real time 5-decade counter
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CPA On D1 selected HIGH to LOW LOW to HIGH CPA On D5 selected HIGH to LOW LOW to HIGH CPA TC LOW to HIGH MR On HIGH to LOW MR OER HIGH to LOW CPS On HIGH to LOW 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 LOW to HIGH CPS OSn HIGH to LOW CPS OSn LOW to HIGH 10 15 5 10 15 5 10 15 tPLH tPHL tPLH tPHL tPHL tPHL tPLH tPLH tPHL tPLH tPHL 300 130 95 240 100 75 550 230 170 550 230 170 420 190 140 200 85 60 140 65 50 225 95 70 225 95 70 170 70 50 170 70 50 600 260 190 480 200 150 1100 460 340 1100 460 340 840 380 280 400 170 120 280 130 100 450 190 140 450 190 140 340 140 100 340 140 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX.
HEF4534B LSI
TYPICAL EXTRAPOLATION FORMULA 283 ns + (0,55 ns/pF) CL 119 ns + (0,23 ns/pF) CL 87 ns + (0,16 ns/pF) CL 213 ns + (0,55 ns/pF) CL 89 ns + (0,23 ns/pF) CL 67 ns + (0,16 ns/pF) CL 523 ns + (0,55 ns/pF) CL 219 ns + (0,23 ns/pF) CL 162 ns + (0,16 ns/pF) CL 523 ns + (0,55 ns/pF) CL 219 ns + (0,23 ns/pF) CL 162 ns + (0,16 ns/pF) CL 393 ns + (0,55 ns/pF) CL 179 ns + (0,23 ns/pF) CL 132 ns + (0,16 ns/pF) CL 173 ns + (0,55 ns/pF) CL 74 ns + (0,23 ns/pF) CL 52 ns + (0,16 ns/pF) CL 113 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 198 ns + (0,55 ns/pF) CL 84 ns + (0,23 ns/pF) CL 62 ns + (0,16 ns/pF) CL 198 ns + (0,55 ns/pF) CL 84 ns + (0,23 ns/pF) CL 62 ns + (0,16 ns/pF) CL 143 ns + (0,55 ns/pF) CL 59 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 143 ns + (0,55 ns/pF) CL 59 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL
January 1995
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Philips Semiconductors
Product specification
Real time 5-decade counter
HEF4534B LSI
MIN. TYP. 60 MAX. 120 60 40 120 60 40 ns ns ns ns ns ns TYPICAL EXTRAPOLATION FORMULA 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
VDD V Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15
SYMBOL
tTHL
30 20 60
tTLH
30 20
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V 3-state propagation delays Output disable times EO On; EOS OSn HIGH LOW Output enable times EO On; EOS OSn HIGH LOW Minimum clock pulse width; CPA, CPS HIGH Minimum reset pulse width; MR, MRsc HIGH Recovery time for MR Recovery time for MRsc 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 tRMR tRMR tWMRH tWCPH 70 40 30 90 60 40 120 60 50 60 40 30 tPZL tPZH 35 20 15 50 25 15 35 20 15 45 30 20 60 30 25 30 20 15 70 40 30 100 50 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 10 15 5 10 15 tPLZ tPHZ 30 25 20 40 25 20 60 50 40 80 50 40 ns ns ns ns ns ns SYMBOL MIN. TYP. MAX.
January 1995
8
Philips Semiconductors
Product specification
Real time 5-decade counter
HEF4534B LSI
MIN. 2,5 TYP. MAX. 5 12 16 MHz MHz MHz
VDD V Maximum clock pulse frequency CPA and CPS 5 10 15
SYMBOL
fmax
6 8
VDD V Dynamic power dissipation per package (P)(1) 5 10 15
TYPICAL FORMULA FOR P (W) 1 100 fi + (foCL) x VDD2 4 800 fi + (foCL) x 12 000 fi + (foCL) x VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V)
Note 1. Cext = 0.
January 1995
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Philips Semiconductors
Product specification
Real time 5-decade counter
APPLICATION INFORMATION
HEF4534B LSI
Fig.9
Two HEF4534B ICs connected for cascade operation. TC is HIGH for a single clock period when all five BCD decades go to zero. TC also goes HIGH when MR is applied.
Fig.10 Forcing a decade to the On outputs. When the On outputs of a given decade are required, this configuration will lock-up the selected decade within four clock cycles. The select line feed back may be hardwired or switched.
January 1995
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