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LH540204
FEATURES
* Fast Access Times: 20/25/35/50 ns * Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology * Input Port and Output Port Have Entirely Independent Timing * Expandable in Width and Depth * Full, Half-Full, and Empty Status Flags * Data Retransmission Capability * TTL-Compatible I/O * Pin and Functionally Compatible with Sharp LH5499 and with Am/IDT/MS7204 * Control Signals Assertive-LOW for Noise Immunity * Packages: 28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ * 32-Pin PLCC
CMOS 4096 x 9 Asynchronous FIFO
FUNCTIONAL DESCRIPTION
The LH540204 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 4096 nine-bit words. It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540204 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit. The input and output ports operate entirely independently of each other, unless the LH540204 becomes either totally full or else totally empty. Data flow at a port is initiated by asserting either of two asynchronous, assertive-LOW control inputs: Write (W) for data entry at the input port, or Read (R) for data retrieval at the output port. Full, Half-Full, and Empty status flags monitor the extent to which the internal memory has been filled. The system may make use of these status outputs to avoid the risk of data loss, which otherwise might occur either by attempting to write additional words into an already-full LH540204, or by attempting to read additional words from an already-empty LH540204. When an LH540204 is operating in a depth-cascaded configuration, the Half-Full Flag is not available.
PIN CONNECTIONS
NC*
28-PIN PDIP 28-PIN SOJ *
D3
D8
D4
W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
540204-2D
4 D2 D1 D0 XI FF Q0 Q1 NC Q2 5 6 7 8 9 10 11 12 13
3
2
1
32 31 30 29 28 27 26 25 24 23 22 21 D6 D7 NC FL/RT RS EF XO/HF Q7 Q6
14 15 16 17 18 19 20
NC*
Q8
VSS
NOTE: * = No external electrical connections are allowed.
540204-3D
Figure 1. Pin Connections for PDIP and SOJ * Packages
Figure 2. Pin Connections for PLCC Package
* This is a final data sheet; except that all references to the SOJ package have Advance Information status.
Q3
Q4
Q5
R
D5
W
TOP VIEW
VCC
32-PIN PLCC
TOP VIEW
1
LH540204
CMOS 4096 x 9 Asynchronous FIFO The Reset (RS) control signal returns the LH540204 to an initial state, empty and ready to be filled. An LH540204 should be reset during every system power-up sequence. A reset operation causes the internal FIFOmemory-array write-address pointer, as well as the readaddress pointer, to be set back to zero, to point to the LH540204's first physical memory location. Any information which previously had been stored within the LH540204 is not recoverable after a reset operation. A cascading (depth-expansion) scheme may be implemented by using the Expansion In (XI) input signal and the Expansion Out (XO/HF) output signal. This allows a deeper `effective FIFO' to be implemented by using two or more LH540204 devices, without incurring additional latency (`fallthrough' or `bubblethrough') delays, and without the necessity of storing and retrieving any given data word more than once. In this cascaded operating mode, one LH540204 device must be designated as the `firstload' or `master' device, by grounding its First-Load (FL/RT) control input; the remaining LH540204 devices are designated as `slaves,' by tying their FL/RT inputs HIGH. Because of the need to share control signals on pins, the Half-Full Flag and the retransmission capability are not available for either `master' or `slave' LH540204 devices operating in cascaded mode.
FUNCTIONAL DESCRIPTION (cont'd)
Data words are read out from the LH540204's output port in precisely the same order that they were written in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline. Since the addressing sequence for a FIFO device's memory is internally predefined, no external addressing information is required for the operation of the LH540204 device. Drop-in-replacement compatibility is maintained with both larger sizes and smaller sizes of industry-standard nine-bit asynchronous FIFOs. The only change is in the number of internally-stored data words implied by the states of the Full Flag and the Half-Full Flag. The Retransmit (RT) control signal causes the internal FIFO-memory-array read-address pointer to be set back to zero, to point to the LH540204's first physical memory location, without affecting the internal FIFO-memoryarray write-address pointer. Thus, the Retransmit control signal provides a mechanism whereby a block of data, delimited by the zero physical address and the current write-address-pointer value, may be read out repeatedly an arbitrary number of times. The only restrictions are that neither the read-address pointer nor the write-address pointer may `wrap around' during this entire process, i.e., advance past physical location zero after traversing the entire memory. The retransmit facility is not available when an LH540204 is operating in a depth-expanded configuration.
RS
RESET LOGIC INPUT PORT CONTROL WRITE POINTER
DATA INPUTS D0 - D8 OUTPUT PORT CONTROL READ POINTER
W
R
DUAL-PORT RAM ARRAY 4096 x 9
...
DATA OUTPUTS Q0 - Q8
FLAG LOGIC
EF FF
FL/RT XI
EXPANSION LOGIC
XO/HF
540204-1
Figure 3. LH540204 Block Diagram 2
CMOS 4096 x 9 Asynchronous FIFO
LH540204
PIN DESCRIPTIONS
PIN PIN TYPE 1 DESCRIPTION PIN PIN TYPE
1
DESCRIPTION
D0 - D8 Q0 - Q8 W R EF FF
I O/Z I I O O
Input Data Bus Output Data Bus Write Request Read Request Empty Flag Full Flag
XO/HF XI FL/RT RS VCC VSS
O I I I V V
Expansion Out/Half-Full Flag Expansion In First Load/Retransmit Reset Positive Power Supply Ground
NOTE: 1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
OPERATIONAL DESCRIPTION
Reset The LH540204 is reset whenever the Reset input (RS) is taken LOW. A reset operation initializes both the readaddress pointer and the write-address pointer to point to location zero, the first physical memory location. During a reset operation, the state of the XI and FL/RT inputs determines whether the device is in standalone mode or in depth-cascaded mode. (See Tables 1 and 2.) The reset operation forces the Empty Flag EF to be asserted (EF = LOW), and the Half-Full Flag HF and the Full Flag FF to be deasserted (HF = FF = HIGH); the Data Out pins (D0 - D8) are forced into a high-impedance state. A reset operation is required whenever the LH540204 first is powered up. The Read (R) and Write (W) inputs may be in any state when the reset operation is initiated; but they must be HIGH, before the reset operation is terminated by a rising edge of RS, by a time tRRSS (for Read) or tWRSS (for Write) respectively. (See Figure 10.) Write A write cycle is initiated by a falling edge of the Write (W) control input. Data setup times and hold times must be observed for the data inputs (D0 - D 8). Write operations may occur independently of any ongoing read operations. However, a write operation is possible only if the FIFO is not full, (i.e., if the Full Flag FF is HIGH). At the falling edge of W for the first write operation after the memory is half filled, the Half-Full Flag is asserted (HF = LOW). It remains asserted until the difference between the write pointer and the read pointer indicates that the data words remaining in the LH540204 are filling the FIFO memory to less than or equal to one-half of its total capacity. The Half-Full Flag is deasserted (HF = HIGH) by the appropriate rising edge of R. (See Table 3.) The Full Flag is asserted (FF = LOW) at the falling edge of W for the write operation which fills the last available location in the FIFO memory array. FF = LOW inhibits further write operations until FF is cleared by a valid read
operation. The Full Flag is deasserted (FF = HIGH) after the next rising edge of R releases another memory location. (See Table 3.) Read A read cycle is initiated by a falling edge of the Read (R) control input. Read data becomes valid at the data outputs (Q0 - Q8) after a time tA from the falling edge of R. After R goes HIGH, the data outputs return to a high-impedance state. Read operations may occur independently of any ongoing write operations. However, a read operation is possible only if the FIFO is not empty (i.e., if the Empty Flag EF is HIGH). The LH540204's internal read-address and writeaddress pointers operate in such a way that consecutive read operations always access data words in the same order that they were written. The Empty Flag is asserted (EF = LOW) after that falling edge of R which accesses the last available data word in the FIFO memory. EF is deasserted (EF = HIGH) after the next rising edge of W loads another valid data word. (See Table 3.) Data Flow-Through Read-data flow-through mode occurs when the Read (R) control input is brought LOW while the FIFO is empty, and is held LOW in anticipation of a write cycle. At the end of the next write cycle, the Empty Flag EF momentarily is deasserted, and the data word just written becomes available at the data outputs (Q0 - Q8) after a maximum time of tWEF + tA. Additional write operations may occur while the R input remains LOW; but only data from the first write operation flows through to the data outputs. Additional data words, if any, may be accessed only by toggling R. Write-data flow-through mode occurs when the Write (W) input is brought LOW while the FIFO is full, and is held LOW in anticipation of a read cycle. At the end of the read cycle, the Full Flag momentarily is deasserted, but then immediately is reasserted in response to W being held LOW. A data word is written into the FIFO on the rising edge of W, which may occur no sooner than tRFF + tWPW after the read operation. 3
LH540204
CMOS 4096 x 9 Asynchronous FIFO Table 2. Expansion-Pin Usage According to Grouping Mode
I/O PIN
STANDALONE
OPERATIONAL DESCRIPTION (cont'd)
Retransmit The FIFO can be made to reread previously-read data by means of the Retransmit function. A retransmit operation is initiated by pulsing the RT input LOW. Both R and W must be deasserted (HIGH) for the duration of the retransmit pulse. The FIFO's internal read-address pointer is reset to point to location zero, the first physical memory location, while the internal write-address pointer remains unchanged. After a retransmit operation, those data words in the region in between the read-address pointer and the write-address pointer may be reaccessed by subsequent read operations. A retransmit operation may affect the state of the status flags FF, HF, and EF, depending on the relocation of the read-address pointer. There is no restriction on the number of times that a block of data within an LH540204 may be read out, by repeating the retransmit operation and the subsequent read operations. The maximum length of a data block which may be retransmitted is 4096 words. Note that if the write-address pointer ever `wraps around' (i.e., passes location zero more than once) during a sequence of retransmit operations, some data words will be lost. The Retransmit function is not available when the LH540204 is operating in depth-cascaded mode, because the FL/RT control pin must be used for first-load selection rather than for retransmission control. Table 1. Grouping-Mode Determination During a Reset Operation
XI FL/ RT MODE XO/HF XI FL/RT USAGE USAGE USAGE
CASCADED CASCADED MASTER SLAVE
I
XI
Grounded
From XO (n-1st FIFO) To XI (n+1st FIFO)
From XO (n-1st FIFO) To XI (n+1st FIFO)
O
XO/HF
Becomes HF Becomes RT
I
FL/RT
Grounded Logic (Logic HIGH LOW)
Table 3. Status Flags
NUMBER OF UNREAD DATA WORDS PRESENT WITHIN 4096 x 9 FIFO FF
HF
EF
0 1 to 2048 2049 to 4095 4096
H H H L
H H L L
L H H H
H1 H1 L
H L X
Cascaded Slave 2 Cascaded Master 2 Standalone
XO XO HF
XI XI (none)
FL FL RT
NOTES: 1. A reset operation forces XO HIGH for the nth FIFO, thus forcing XI HIGH for the (n+1)st FIFO. 2. The terms `master' and `slave' refer to operation in depth-cascaded grouping mode. 3. H = HIGH; L = LOW; X = Don't Care.
4
CMOS 4096 x 9 Asynchronous FIFO
LH540204 Width Expansion Word-width expansion is implemented by placing multiple LH540204 devices in parallel. Each LH540204 should be configured for standalone mode. In this arrangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive `composite' flag values using external logic, since there may be minor speed variations between different actual devices. (See Figures 4, 5, and 6.)
OPERATIONAL MODES
Standalone Configuration When depth cascading is not required for a given application, the LH540204 is placed in standalone mode by tying the Expansion In input (XI) to ground. This input is internally sampled during a reset operation. (See Table 1.)
HF WRITE W R READ
DATA IN D0 - D8
9 LH540204
9
DATA OUT Q0 - Q8
FULL FLAG
FF
EF
EMPTY FLAG
RESET
RS
RT
RETRANSMIT
XI
540204-17
Figure 4. Standalone FIFO (4096 x 9)
DATA IN D0 - D17
18 9 WRITE FULL FLAG RESET W FF
HF 9 W R LH540204 RS RT 9 XI RS
HF
EF LH540204 R
EMPTY FLAG READ
RT 9 XI
RETRANSMIT
18
DATA OUT Q0 - Q17
540204-18
Figure 5. FIFO Word-Width Expansion (4096 x 18)
5
LH540204
CMOS 4096 x 9 Asynchronous FIFO all devices are tied together. Likewise, only one LH540204 is enabled during any given read cycle; thus, the common Data Out outputs of all devices are wireORed together. In depth-cascaded mode, external logic should be used to generate a composite Full Flag and a composite Empty Flag, by ANDing the FF outputs of all LH540204 devices together and ANDing the EF outputs of all devices together. Since FF and EF are assertive-LOW signals, this `ANDing' actually is implemented using an assertiveHIGH physical OR gate. The Half-Full Flag and the Retransmit function are not available in depth-cascaded mode.
OPERATIONAL MODES (cont'd)
Depth Cascading Depth cascading is implemented by configuring the required number of LH540204s in depth-cascaded mode. In this arrangement, the FIFOs are connected in a circular fashion, with the Expansion Out output (XO) of each device tied to the Expansion In input (XI) of the next device. One FIFO in the cascade must be designated as the `first-load' device, by tying its First Load input (FL/RT) to ground. All other devices must have their FL/RT inputs tied HIGH. In this mode, W and R signals are shared by all devices, while logic within each LH540204 controls the steering of data. Only one LH540204 is enabled during any given write cycle; thus, the common Data In inputs of
XO W DATA IN D0 - D8 9 9 FF RS XI 9 FULL FF RS XI 9 FF RS XI
540204-19
R 9 LH540204 EF FL XO 9 LH540204 EF FL XO 9 LH540204 EF FL Vcc EMPTY Vcc 9 DATA OUT Q0 - Q8
RS
Figure 6. FIFO Depth Cascading (12288 x 9)
6
CMOS 4096 x 9 Asynchronous FIFO
LH540204 LH540204 are tied to the corresponding Data Out outputs of another LH540204, which is operating in the opposite direction, to form a single bidirectional bus interface. Care must be taken to assure that the appropriate read, write, and flag signals are routed to each system. Both wordwidth expansion and depth cascading may be used in bidirectional applications.
OPERATIONAL MODES (cont'd)
Compound FIFO Expansion A combination of word-width expansion and depth cascading may be implemented easily by operating groups of depth-cascaded FIFOs in parallel. Bidirectional FIFO Operation Bidirectional data buffering between two systems may be implemented by operating LH540204 devices in parallel, but in opposite directions. The Data In inputs of each
Q0 - Q8
Q0 - Q17
Q0 - QN-10
Q0 - QN-1
DATA OUT
R W RS
LH540204 DEPTH EXPANSION BLOCK
LH540204 DEPTH EXPANSION BLOCK
LH540204 DEPTH EXPANSION BLOCK
DATA IN
ARRAY STORES N-BIT WORDS. D0 - DN-1 D9 - DN-1 D18 - DN-1 DN-9 - DN-1
540204-20
Figure 7. Compound FIFO Expansion
Wa FFa LH540204 RS Da0 - 8 XI SYSTEM A Qb0 - 8
Rb EFb HFb RTb
SYSTEM B
Qa0 - 8 Ra EFa HFa RTa XI LH540204
Db0 - 8 Wb FFb
RS
540204-21
Figure 8. Bidirectional FIFO Operation (4096 x 9 x 2)
7
LH540204
CMOS 4096 x 9 Asynchronous FIFO
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER RATING
Supply Voltage to VSS Potential Signal Pin Voltage to VSS Potential 2 DC Output Current
3
-0.5 V to 7 V -0.5 V to VCC + 0.5 V (not to exceed 7 V) 50 mA -65oC to 150oC 1.0 W -0.5 V to VCC + 0.5 V (not to exceed 7 V)
Storage Temperature Range Power Dissipation (Package Limit) DC Voltage Applied to Outputs In High-Z State
NOTES: 1. Stresses greater than those listed under `Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions outside of those indicated in the `Operating Range' of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGE
SYMBOL PARAMETER MIN MAX UNIT
TA VCC VSS VIL VIH
Temperature, Ambient Supply Voltage Supply Voltage Logic LOW Input Voltage Logic HIGH Input Voltage
1
0 4.5 0 -0.5 2.0
70 5.5 0 0.8 VCC + 0.5
C V V V V
NOTE: 1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT
ILI ILO VOH VOL ICC ICC2 ICC3
Input Leakage Current Output Leakage Current Output HIGH Voltage Output LOW Voltage Average Supply Current
1
VCC = 5.5 V, VIN = 0 V to VCC R VIH, 0 V VOUT V CC IOH = -2.0 mA IOL = 8.0 mA Measured at f = 33 MHz All Inputs = VIH All Inputs = VCC - 0.2 V
-10 -10 2.4
10 10
A A V
0.4 110 15 8
V mA mA mA
Average Standby Current 1 Power Down Current
1
NOTE: 1. ICC, ICC2, and ICC3 are dependent upon actual output loading and cycle rates. Specified values are with outputs open.
8
CMOS 4096 x 9 Asynchronous FIFO
LH540204
AC TEST CONDITIONS
PARAMETER RATING
+5 V 1.1 k DEVICE UNDER TEST
Input Pulse Levels Input Rise and Fall Times (10% to 90%) Input Timing Reference Levels Output Reference Levels Output Load, Timing Tests
VSS to 3 V 5 ns 1.5 V 1.5 V Figure 9
680
30 pF *
CAPACITANCE 1,2
PARAMETER RATING
* INCLUDES JIG AND SCOPE CAPACITANCES
5 pF 7 pF Figure 9. Output Load Circuit
540204-4
CIN (Input Capacitance) COUT (Output Capacitance)
NOTES: 1. Sample tested only. 2. Capacitances are maximum values at 25oC, measured at 1.0 MHz, with VIN = 0 V.
9
LH540204
CMOS 4096 x 9 Asynchronous FIFO
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range)
SYMBOL PARAMETER tA = 20 ns MIN MAX tA = 25 ns MIN MAX tA = 35 ns MIN MAX tA = 50 ns MIN MAX UNIT
READ CYCLE TIMING tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSR tRRSS tWRSS tRTC tRT tRTR tEFL tHFH,FFH tREF tRFF tWEF tWFF tWHF tRHF tXOL tXOH tXI tXIR tXIS Read Cycle Time Access Time Read Recovery Time Read Pulse Width
2 3
30 - 10 20 5 10 5 - 30 20 10 12 0 30 20 10 20 20 30
2
- 20 - - - - - 15 - - - - - - - - - -
5
35 - 10 25 5 10 5 - 35 25 10 15 0 35 25 10 25 25 35 25 10 - - - - - - - - - - 25 10 10
- 25 - - - - - 15 - - - - - - - - - - - - - 35 35 25 25 25 25 25 25 25 25 - - -
45 - 10 35 5 10 5 - 45 35 10 18 0 45 35 10 35 35 45 35 10 - - - - - - - - - - 35 10 15
- 35 - - - - - 15 - - - - - - - - - - - - - 45 45 35 35 35 35 35 35 35 35 - - -
65 - 15 50 5 10 5 - 65 50 15 30 0 65 50 15 50 50 65 50 15 - - - - - - - - - - 50 10 15
- 50 - - - - - 20 - - - - - - - - - - - - - 65 65 45 45 45 45 45 45 50 50 - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Bus Active from Read LOW
Data Bus Active from Write HIGH 3,4 Data Held Valid from Read Pulse HIGH Data Bus High-Z from Read HIGH 3 Write Cycle Time Write Pulse Width 2 Write Recovery Time Data Setup Time Data Hold Time Reset Cycle Time Reset Pulse Width 2 Reset Recovery Time Read HIGH to RS HIGH Write HIGH to RS HIGH Retransmit Cycle Time Retransmit Pulse Width Retransmit Recovery Time Reset LOW to Empty Flag LOW Reset LOW to Half-Full and Full Flags HIGH Read LOW to Empty Flag LOW Read HIGH to Full Flag HIGH Write HIGH to Empty Flag HIGH Write LOW to Full Flag LOW Write LOW to Half-Full Flag LOW Read HIGH to Half-Full Flag HIGH Expansion Out LOW Expansion Out HIGH Expansion In Pulse Width Expansion In Recovery Time Expansion in Setup Time
WRITE CYCLE TIMING
RESET TIMING
RETRANSMIT TIMING - - - 30 30 20 20 20 20 20 20 20 20 - - - 20 10 - - - - - - - - - - 20 10 10
FLAG TIMING
EXPANSION TIMING
NOTES: 1. All timing measurements are performed at `AC Test Condition' levels. 2. Pulse widths less than minimum value are not allowed. 3. Values are guaranteed by design; not currently tested. 4. Only applies to read-data flow-through mode. 5. See also Note 2, Figure 19.
10
CMOS 4096 x 9 Asynchronous FIFO
LH540204
TIMING DIAGRAMS
t RSC t RS
RS
R,W t RRSS t WRSS tEFL t RSR
EF t FFH , t HFH
FF,HF NOTES: 1. tRSC = tRS + tRSR. 2. W and R VIH around the rising edge of RS. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.
540204-14
Figure 10. Reset Timing
t RC tA t RR tA
t RPW
R t RLZ t DV t RHZ
Q0 - Q8
VALID DATA OUT t WC t WPW t WR
VALID DATA OUT
W t DS t DH
D0 - D8
VALID DATA IN
VALID DATA IN
540204-5
Figure 11. Asynchronous Write and Read Operation
11
LH540204
CMOS 4096 x 9 Asynchronous FIFO
TIMING DIAGRAMS (cont'd)
LAST WRITE R
FIRST READ
W t WFF
t RFF
FF
540206-6
Figure 12. Full Flag From Last Write to First Read
LAST READ W
FIRST WRITE
R t REF t WEF
EF NOTE: The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.
540204-7
Figure 13. Empty Flag From Last Read to First Write
12
CMOS 4096 x 9 Asynchronous FIFO
LH540204
TIMING DIAGRAMS (cont'd)
D0 - D8
VALID DATA IN
W
tRPE
R
EF t WEF t WLZ tA t REF
Q0 - Q8 NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.
VALID DATA OUT
540204-8
Figure 14. Read Data Flow-Through
R
tWPF
W t RFF
FF t WFF t DS t DH
D0 - D8 tA
VALID DATA IN
Q0 - Q8
VALID DATA OUT
NOTES: 1. tWPF = tWPW. 2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
540204-9
Figure 15. Write Data Flow-Through
13
LH540204
CMOS 4096 x 9 Asynchronous FIFO
TIMING DIAGRAMS (cont'd)
W t WEF
EF t RPE
R
NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW.
540204-10
Figure 16. Empty Flag Timing
R t RFF
FF t WPF
W NOTES: 1. tWPF = tWPW. 2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
540204-11
Figure 17. Full Flag Timing
14
CMOS 4096 x 9 Asynchronous FIFO
LH540204
TIMING DIAGRAMS (cont'd)
HALF-FULL OR LESS W
MORE THAN HALF-FULL
HALF-FULL OR LESS
R t WHF tRHF
HF
540204-12
Figure 18. Half-Full Flag Timing
t RT
RT t RTR R,W NOTES: 1. tRTC = tRT + tRTR. 2. FF, HF, and EF may change state during retransmit; but they will become valid by tRTC.
540204-13
Figure 19. Retransmit Timing
15
LH540204
CMOS 4096 x 9 Asynchronous FIFO
TIMING DIAGRAMS (cont'd)
WRITE TO LAST AVAILABLE LOCATION READ FROM LAST VALID LOCATION t XOL t XOH t XOL t XOH
W
R
XO
540204-15
Figure 20. Expansion-Out Timing
t XI
t XIR
XI t XIS WRITE TO FIRST AVAILABLE LOCATION
W
t XIS READ FROM FIRST VALID LOCATION
540204-16
R
Figure 21. Expansion-In Timing
16
CMOS 4096 x 9 Asynchronous FIFO
LH540204
PACKAGE DIAGRAMS
28DIP (DIP28-W-300) DETAIL
7.49 [0.295] 7.11 [0.280] 0 TO 15 34.80 [1.370] 34.54 [1.360] 0.30 [0.012] 0.20 [0.008] 7.62 [0.300] TYP.
3.30 [0.130] 4.57 [0.180] MAX 3.43 [0.135] 3.18 [0.125]
2.54 [0.100] TYP.
0.53 [0.021] 0.38 [0.015]
0.51 [0.020] MIN
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
28DIP-3
28-pin, 300-mil PDIP
28SOJ (SOJ28-P-300)
28 15
DETAIL
7.9 [0.311] 7.5 [0.295]
8.63 [0.340] 8.23 [0.324]
3.7 [0.146] 3.3 [0.130]
2.6 [0.102] 2.2 [0.087]
1 18.7 [0.736] 18.3 [0.720]
14
0.64 [0.025] MIN 0.8 [0.031] 0.6 [0.024] 0.102 [0.004]
0.20 [0.008] 1.15 [0.045] 0.85 [0.033]
1.27 [0.050] TYP. DIMENSIONS IN MM [INCHES]
0.53 [0.021] 0.33 [0.013] MAXIMUM LIMIT MINIMUM LIMIT
7.0 [0.276] 6.6 [0.260]
28SOJ300
28-pin, 300-mil SOJ
17
LH540204
CMOS 4096 x 9 Asynchronous FIFO
32PLCC (PLCC32-P-R450)
1.27 [0.050] 4 SIDES BSC
15.11 [0.595] 14.86 [0.585] 14.05 [0.553] 13.89 [0.547] 13.46 [0.530] 12.45 [0.490]
11.51 [0.453] 11.35 [0.447] 12.57 [0.495] 12.32 [0.485]
DETAIL
0.81 [0.032] 0.66 [0.026]
0.10 [0.004]
3.56 [0.140] 3.12 [0.123]
2.41 [0.095] 1.52 [0.060] 10.92 [0.430] 9.91 [0.390]
0.38 [0.015] MIN 0.53 [0.021] 0.33 [0.013]
MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT
32PLCC
32-pin, 450-mil PLCC
ORDERING INFORMATION
LH540204 Device Type X Package - ## Speed 20 25 35 50
Access Time (ns)
D 28-pin, 300-mil Plastic DIP (DIP28-W-300) K 28-pin, 300-mil SOJ * (SOJ28-P-300) U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450) CMOS 4096 x 9 FIFO * Contact a Sharp representative for availability of SOJ package. Example: LH540204U-25 (CMOS 4096 x 9 FIFO, 32-pin PLCC, 25 ns)
540204MD
18

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